coreboot-gerrit September 2021

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Change in coreboot[master]: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57349 ) Change subject: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Should we split the ADD_FSP_BINARIES for AMD & Intel? Select it only for intel boards if FSP_USE_RE […] in the Intel case ADD_FSP_BINARIES is default y if FSP_USE_REPO and I added select ADD_FSP_BINARIES if USE_AMD_BLOBS for Picasso which is currently the only AMD platform with published FSP. might be a good idea to rename FSP_USE_REPO to FSP_USE_INTEL_REPO, but I'm not sure if that'll break local configs -- To view, visit https://review.coreboot.org/c/coreboot/+/57349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 Gerrit-Change-Number: 57349 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add tpch device information under dptf
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57097 ) Change subject: soc/intel/alderlake: Add tpch device information under dptf ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Gerrit-Change-Number: 57097 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56809 ) Change subject: sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c Gerrit-Change-Number: 56809 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Introduce new thermal control mechanism for pch d...
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 ) Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57096/comment/14f1afb1_07e09574 PS5, Line 211: acpigen_emit_byte(RETURN_OP); : acpigen_write_package(0); : acpigen_write_package_end(); > We need this return value to resolve any kind of EVAL failure in DPTF ESIF shell. […] Can you add a comment then that the reason for returning a value here is a W/A for the ESIF shell? -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:16:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/gpio_banks: factor out gpio_mux_ptr
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56787 ) Change subject: soc/amd/common/block/gpio_banks: factor out gpio_mux_ptr ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6 Gerrit-Change-Number: 56787 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:16:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add PMC IPC commands for FIVR
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57095 ) Change subject: soc/intel/common: Add PMC IPC commands for FIVR ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Gerrit-Change-Number: 57095 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:15:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO access
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Michał Żygowski, Marshall Dawson, Felix Held, Piotr Król. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56786 ) Change subject: soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO access ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a Gerrit-Change-Number: 56786 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:15:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants: fix override values for power limits
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Sumeet Pawnikar, Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57290 ) Change subject: mb/google/brya/variants: fix override values for power limits ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57290/comment/5e224316_5748a69d PS4, Line 9: There are two different types of 682 SKU available with TDP of 28W and 45W. : This patch fix override values for power limits for these 682 SKU. : This patch also sets power limit values dynamically based on machine ID and : CPU TDP of SKU. reflow for 72 characters wide please -- To view, visit https://review.coreboot.org/c/coreboot/+/57290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Gerrit-Change-Number: 57290 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:14:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: set power limits dynamically for thermal
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57035 ) Change subject: soc/intel/alderlake: set power limits dynamically for thermal ...................................................................... soc/intel/alderlake: set power limits dynamically for thermal Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/systemagent.c 3 files changed, 57 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index eaaef07..ae85b91 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <device/pci_ids.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -20,14 +21,37 @@ /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { - ADL_P_POWER_LIMITS_282_CORE, - ADL_P_POWER_LIMITS_482_CORE, - ADL_P_POWER_LIMITS_682_CORE, - ADL_M_POWER_LIMITS_282_CORE, - ADL_M_POWER_LIMITS_242_CORE, + ADL_P_282_CORE, + ADL_P_482_CORE, + ADL_P_682_28W_CORE, + ADL_P_682_45W_CORE, + ADL_M_282_CORE, + ADL_M_242_CORE, ADL_POWER_LIMITS_COUNT }; +/* TDP values for different SKUs */ +enum soc_intel_alderlake_cpu_tdps { + TDP_9W = 9, + TDP_15W = 15, + TDP_28W = 28, + TDP_45W = 45 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int cpu_id; + enum soc_intel_alderlake_power_limits limits; + enum soc_intel_alderlake_cpu_tdps cpu_tdp; +} cpuid_to_adl[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, +}; + /* Types of display ports */ enum ddi_ports { DDI_PORT_A, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index eff64f1..c89fe6a 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,30 +2,36 @@ device cpu_cluster 0 on end - register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_P_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ + register "power_limits_config[ADL_P_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + .tdp_pl4 = 140, + }" + + register "power_limits_config[ADL_P_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, }" - register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_M_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 45, }" - register "power_limits_config[ADL_M_POWER_LIMITS_242_CORE]" = "{ + register "power_limits_config[ADL_M_242_CORE]" = "{ .tdp_pl1_override = 9, .tdp_pl2_override = 30, .tdp_pl4 = 68, diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index cfb6f79..6bd02ee 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <delay.h> #include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> @@ -56,6 +55,8 @@ struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + u8 tdp; + size_t i; config_t *config; /* Enable Power Aware Interrupt Routing */ @@ -72,31 +73,24 @@ sa = pcidev_path_on_root(SA_DEVFN_ROOT); sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; - /* Choose a power limits configuration based on the SoC SKU type, - * differentiated here based on SA PCI ID. */ - switch (sa_pci_id) { - case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_282_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_482_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: - soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_282_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_M_ID_2: - soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_242_CORE]; - break; - default: - printk(BIOS_ERR, "ADL: unknown SA ID: 0x%4x, skipping power limits configuration\n", + tdp = get_cpu_tdp(); + + /* Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_adl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_adl)) { + printk(BIOS_ERR, "ERROR: unknown SA ID: 0x%4x, skipped power limits configuration.\n", sa_pci_id); return; } - - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -- To view, visit https://review.coreboot.org/c/coreboot/+/57035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Gerrit-Change-Number: 57035 Gerrit-PatchSet: 10 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: get tdp of CPU for different SKUs
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57143 ) Change subject: soc/intel/common: get tdp of CPU for different SKUs ...................................................................... soc/intel/common: get tdp of CPU for different SKUs Get tdp value of CPU for different SKUs based on PKG POWER MSR. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 2fa25de..934eaa4 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -38,4 +38,6 @@ void set_power_limits(u8 power_limit_1_time, struct soc_power_limits_config *config); +u8 get_cpu_tdp(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */ diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index e6c65c3..417dd04 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -195,3 +195,18 @@ wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); } } + +u8 get_cpu_tdp(void) +{ + unsigned int power_unit, cpu_tdp; + + /* Get units */ + msr_t msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + cpu_tdp = msr.lo & 0x7fff; + + return cpu_tdp / power_unit; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/57143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Gerrit-Change-Number: 57143 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2021