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Change subject: [TESTME] soc/amd/common/block/gpio_banks: add remote GPIO support
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127450):
https://review.coreboot.org/c/coreboot/+/56810/comment/17ee399a_afefde21
PS3, Line 21: if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER ||
Comparisons should place the constant on the right side of the test
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127450):
https://review.coreboot.org/c/coreboot/+/56810/comment/43bcd093_9929a3fd
PS3, Line 43: if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER ||
Comparisons should place the constant on the right side of the test
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Change subject: mb/google/brya/variants/gimble: update fw_config.c for next build phase
......................................................................
Patch Set 1: Code-Review+2
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Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
Patch Set 16:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/57069/comment/4e817d12_5b78fb86
PS16, Line 263: rec->size = sizeof(*rec);
> Doesn't this need to include the ports?
`sizeof(*rec) + sizeof(struct type_c_port_info) * count`
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57291
to look at the new patch set (#2).
Change subject: [WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
......................................................................
[WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
Since bootblock_soc_early_init gets called before
bootblock_mainboard_early_init which does the early GPIO setup, external
I2C level shifters that are controlled by GPIOs might not be enabled yet.
Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure
that the early GPIO setup is already done when reset_i2c_peripherals is
called.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/picasso/early_fch.c
M src/soc/amd/stoneyridge/bootblock.c
3 files changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/57291/2
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50580 )
Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280
......................................................................
Patch Set 63: Code-Review+2
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Change subject: mb/google/guybrush: If not using PCIe WWAN, disable the port
......................................................................
Patch Set 1:
(3 comments)
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/57316/comment/f2787b7f_3716c324
PS1, Line 10: const
Do we need it to be const? I believe our intention is to prevent the caller(i.e. FSP) from modifying this descriptor. If so we have achieved that with the "const fsp_dxio_descriptor **dxio" in/out parameter.
If we remove const, then we can have one table and fill the WWAN descriptor if variant has PCIe WWAN or reset it if variant does not have PCIe WWAN. Finally return the updated dxio_descriptor. Thoughts?
https://review.coreboot.org/c/coreboot/+/57316/comment/5c4bfc86_b66c4473
PS1, Line 157: };
Nit: If you still prefer the double table approach, then please add a blank line.
https://review.coreboot.org/c/coreboot/+/57316/comment/c8e467f7_3e5e65d0
PS1, Line 191: if (variant_has_pcie_wwan()){
> space required before the open brace '{'
Please fix.
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