coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/qualcomm/sc7280: DDR One-Time-Training Support
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Ravi kumar, Paul Menzel, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54352 ) Change subject: soc/qualcomm/sc7280: DDR One-Time-Training Support ...................................................................... Patch Set 31: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54352/comment/9651be5d_58786cc8 PS16, Line 7: soc/qualcomm/sc7280: DDR One-Time-Training Support > Still not a statement. I think that the added explanation should clearly explain what's being added. -- To view, visit https://review.coreboot.org/c/coreboot/+/54352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Gerrit-Change-Number: 54352 Gerrit-PatchSet: 31 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:58:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpi/gpio: add warning for remote GPIO usage
by build bot (Jenkins) (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56817 ) Change subject: soc/amd/common/block/acpi/gpio: add warning for remote GPIO usage ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/block/acpi/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127451): https://review.coreboot.org/c/coreboot/+/56817/comment/c3747648_4479613a PS2, Line 14: if (SOC_GPIO_TOTAL_PINS >= AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER && Comparisons should place the constant on the right side of the test Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127451): https://review.coreboot.org/c/coreboot/+/56817/comment/2dcb2f80_803edfee PS2, Line 33: if (SOC_GPIO_TOTAL_PINS >= AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER && Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/c/coreboot/+/56817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2 Gerrit-Change-Number: 56817 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:56:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common/qspi: Add support for common QSPI driver
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Ravi kumar, Roja Rani Yarubandi, Paul Menzel, mturney mturney, Julius Werner, Rajesh Patil. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55323 ) Change subject: soc/qualcomm/common/qspi: Add support for common QSPI driver ...................................................................... Patch Set 23: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55323/comment/1120448e_fd0277d2 PS6, Line 15: TEST=Validated on qualcomm sc7180 and sc7280 development board > we are checking in Boot logs. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Gerrit-Change-Number: 55323 Gerrit-PatchSet: 23 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:56:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTME] soc/amd/common/block/gpio_banks: add remote GPIO support
by build bot (Jenkins) (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56810 ) Change subject: [TESTME] soc/amd/common/block/gpio_banks: add remote GPIO support ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/block/gpio_banks/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127450): https://review.coreboot.org/c/coreboot/+/56810/comment/17ee399a_afefde21 PS3, Line 21: if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER || Comparisons should place the constant on the right side of the test Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127450): https://review.coreboot.org/c/coreboot/+/56810/comment/43bcd093_9929a3fd PS3, Line 43: if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER || Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/c/coreboot/+/56810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db Gerrit-Change-Number: 56810 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: update fw_config.c for next build phase
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: YH Lin, Furquan Shaikh, Paul Fagerburg, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57360 ) Change subject: mb/google/brya/variants/gimble: update fw_config.c for next build phase ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d Gerrit-Change-Number: 57360 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:55:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Nico Huber, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 16: (1 comment) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/57069/comment/4e817d12_5b78fb86 PS16, Line 263: rec->size = sizeof(*rec); > Doesn't this need to include the ports? `sizeof(*rec) + sizeof(struct type_c_port_info) * count` -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 16 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:54:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/herobrine: Configure SDCC clock
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50585 ) Change subject: mainboard/google/herobrine: Configure SDCC clock ...................................................................... mainboard/google/herobrine: Configure SDCC clock Configure 384MHz for eMMC clock and 50MHz for SD card clock. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50585 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c 1 file changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 365fad4..dc60e6e 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "board.h" +#include <boardid.h> +#include <bootblock_common.h> +#include <soc/clock.h> +#include <console/console.h> #include <device/device.h> #include <bootblock_common.h> +#include <soc/clock.h> static void mainboard_init(struct device *dev) { - + /* Configure clock for eMMC */ + clock_configure_sdcc(1, 384 * MHz); + /* Configure clock for SD card */ + clock_configure_sdcc(2, 50 * MHz); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/50585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Gerrit-Change-Number: 50585 Gerrit-PatchSet: 66 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/kblrvp: Mark disabled SerialIO devices as `off`
by Michael Niewöhner (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57229 ) Change subject: mb/intel/kblrvp: Mark disabled SerialIO devices as `off` ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57229/comment/c8f04aeb_dee5eb33 PS1, Line 7: Disable disabled SerialIO devices > I like it way better :) -- To view, visit https://review.coreboot.org/c/coreboot/+/57229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf Gerrit-Change-Number: 57229 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:50:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57291 to look at the new patch set (#2). Change subject: [WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup ...................................................................... [WIP] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/stoneyridge/bootblock.c 3 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/57291/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Gerrit-Change-Number: 57291 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: Move to use common clock driver for sc7280
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50580 ) Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280 ...................................................................... qualcomm/sc7280: Move to use common clock driver for sc7280 It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 6 files changed, 914 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index e83f979..09cd95c 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -236,6 +236,29 @@ return CB_SUCCESS; } +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) +{ + setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); + + /* + * H/W requires a 1us delay between disabling the bypass and + * de-asserting the reset. + */ + udelay(1); + setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); + setbits32(cfg->reg_opmode, PLL_RUN_MODE); + + if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + return CB_ERR; + } + + setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK); + setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); + + return CB_SUCCESS; +} + /* Bring subsystem out of RESET */ void clock_reset_subsystem(u32 *misc, u32 shft) { diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h index b924194..0911827 100644 --- a/src/soc/qualcomm/common/include/soc/clock_common.h +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -155,6 +155,8 @@ bool enable, int br_enable); enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg); + struct aoss { u8 _res0[0x50020]; u32 aoss_cc_reset_status; diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 3c34be0..b44c754 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -3,6 +3,8 @@ all-y += ../common/timer.c all-y += spi.c all-y += ../common/gpio.c +all-y += ../common/clock.c +all-y += clock.c ################################################################################ bootblock-y += bootblock.c diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c new file mode 100644 index 0000000..871fb9b --- /dev/null +++ b/src/soc/qualcomm/sc7280/clock.c @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <timer.h> +#include <types.h> + +static struct clock_freq_config qspi_core_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = QCOM_CLOCK_DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(6), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(4), + }, + { + .hz = 200 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(3), + }, + { + .hz = 400 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(1.5), + }, +}; + +static struct clock_freq_config qupv3_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = QCOM_CLOCK_DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(1), + .m = 8, + .n = 75, + .d_2 = 75, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(1), + .m = 4, + .n = 25, + .d_2 = 25, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(1), + .m = 16, + .n = 75, + .d_2 = 75, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(1), + .m = 8, + .n = 25, + .d_2 = 25, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = QCOM_CLOCK_DIV(6), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = QCOM_CLOCK_DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = QCOM_CLOCK_DIV(1), + }, +}; + +static struct clock_freq_config sdcc1_core_cfg[] = { + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(3), + }, + { + .hz = 192 * MHz, + .src = SRC_GPLL10_MAIN_384MHZ, + .div = QCOM_CLOCK_DIV(2), + }, + { + .hz = 384 * MHz, + .src = SRC_GPLL10_MAIN_384MHZ, + .div = QCOM_CLOCK_DIV(1), + }, +}; + +static struct clock_freq_config sdcc2_core_cfg[] = { + { + .hz = 50 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = QCOM_CLOCK_DIV(6), + }, + { + .hz = 202 * MHz, + .src = SRC_GPLL9_MAIN_808MHZ, + .div = QCOM_CLOCK_DIV(4), + }, +}; + +static struct pcie pcie_cfg[] = { + [PCIE_1_GDSC] = { + .gdscr = &gcc->pcie_1.gdscr, + }, + [PCIE_1_SLV_Q2A_AXI_CLK] = { + .clk = &gcc->pcie_1.slv_q2a_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_SLV_Q2A_AXI_CLK_ENA, + }, + [PCIE_1_SLV_AXI_CLK] = { + .clk = &gcc->pcie_1.slv_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_SLV_AXI_CLK_ENA, + }, + [PCIE_1_MSTR_AXI_CLK] = { + .clk = &gcc->pcie_1.mstr_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_MSTR_AXI_CLK_ENA, + }, + [PCIE_1_CFG_AHB_CLK] = { + .clk = &gcc->pcie_1.cfg_ahb_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_CFG_AHB_CLK_ENA, + }, + [PCIE_1_AUX_CLK] = { + .clk = &gcc->pcie_1.aux_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_AUX_CLK_ENA, + }, + [AGGRE_NOC_PCIE_TBU_CLK] = { + .clk = &gcc->aggre_noc_pcie_tbu_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = AGGRE_NOC_PCIE_TBU_CLK_ENA, + }, + [AGGRE_NOC_PCIE_1_AXI_CLK] = { + .clk = &gcc->pcie_1.aggre_noc_pcie_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = AGGRE_NOC_PCIE_1_AXI_CLK_ENA, + }, + [DDRSS_PCIE_SF_CLK] = { + .clk = &gcc->pcie_1.ddrss_pcie_sf_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = DDRSS_PCIE_SF_CLK_ENA, + }, + [PCIE1_PHY_RCHNG_CLK] = { + .clk = &gcc->pcie_1.phy_rchng_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE1_PHY_RCHNG_CLK_ENA, + }, + [AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] = { + .clk = &gcc->pcie_1.aggre_noc_pcie_center_sf_axi_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en1, + .vote_bit = AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA, + }, + [PCIE_1_PIPE_CLK] = { + .clk = &gcc->pcie_1.pipe_cbcr, + .clk_br_en = &gcc->apcs_clk_br_en, + .vote_bit = PCIE_1_PIPE_CLK_ENA, + }, + [PCIE_CLKREF_EN] = { + .clk = &gcc->pcie_clkref_en, + .vote_bit = NO_VOTE_BIT, + }, + [GCC_PCIE_1_PIPE_MUXR] = { + .clk = &gcc->pcie_1.pipe_muxr, + .vote_bit = NO_VOTE_BIT, + }, +}; + +static struct clock_freq_config mdss_mdp_cfg[] = { + { + .hz = 200 * MHz, + .src = SRC_GCC_DISP_GPLL0_CLK, + .div = QCOM_CLOCK_DIV(3), + }, + { + .hz = 300 * MHz, + .src = SRC_GCC_DISP_GPLL0_CLK, + .div = QCOM_CLOCK_DIV(2), + }, +}; + +static struct clock_rcg_mnd *mdss_clock[MDSS_CLK_COUNT] = { + [MDSS_CLK_PCLK0] = &mdss->pclk0, + [MDSS_CLK_MDP] = &mdss->mdp, + [MDSS_CLK_VSYNC] = &mdss->vsync, + [MDSS_CLK_ESC0] = &mdss->esc0, + [MDSS_CLK_BYTE0] = &mdss->byte0, + [MDSS_CLK_BYTE0_INTF] = &mdss->byte0, + [MDSS_CLK_AHB] = &mdss->ahb, +}; + +static u32 *mdss_cbcr[MDSS_CLK_COUNT] = { + [GCC_DISP_AHB] = &gcc->disp_ahb_cbcr, + [GCC_DISP_HF_AXI] = &gcc->disp_hf_axi_cbcr, + [GCC_DISP_SF_AXI] = &gcc->disp_sf_axi_cbcr, + [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr, + [MDSS_CLK_MDP] = &mdss->mdp_cbcr, + [MDSS_CLK_VSYNC] = &mdss->vsync_cbcr, + [MDSS_CLK_BYTE0] = &mdss->byte0_cbcr, + [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr, + [MDSS_CLK_ESC0] = &mdss->esc0_cbcr, + [MDSS_CLK_AHB] = &mdss->ahb_cbcr, +}; + +static u32 *gdsc[MAX_GDSC] = { + [PCIE_1_GDSC] = &gcc->pcie_1.gdscr, + [MDSS_CORE_GDSC] = &mdss->core_gdsc, +}; + +static enum cb_err clock_configure_gpll0(void) +{ + struct alpha_pll_reg_val_config gpll0_cfg = {0}; + + gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl; + gpll0_cfg.user_ctl_val = (1 << PLL_POST_DIV_EVEN_SHFT | + 3 << PLL_POST_DIV_ODD_SHFT | + 1 << PLL_PLLOUT_EVEN_SHFT | + 1 << PLL_PLLOUT_MAIN_SHFT | + 1 << PLL_PLLOUT_ODD_SHFT); + + return clock_configure_enable_gpll(&gpll0_cfg, false, 0); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + + +void clock_enable_qup(int qup) +{ + struct qupv3_clock *qup_clk; + int s = qup % QUP_WRAP1_S0, clk_en_off; + + qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + if (qup < QUP_WRAP1_S6) { + clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en1, + clk_en_off); + } else { + clk_en_off = QUPV3_WRAP1_CLK_ENA_1_S(s); + clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en, + clk_en_off); + } +} + +void clock_configure_sdcc(enum clk_sdcc sdcc, uint32_t hz) +{ + if (sdcc == SDCC1_CLK) { + if (hz > CLK_100MHZ) { + struct alpha_pll_reg_val_config gpll10_cfg = {0}; + gpll10_cfg.reg_mode = &gcc->gpll10.mode; + gpll10_cfg.reg_opmode = &gcc->gpll10.opmode; + gpll10_cfg.reg_l = &gcc->gpll10.l; + gpll10_cfg.l_val = 0x14; + gpll10_cfg.reg_cal_l = &gcc->gpll10.cal_l; + gpll10_cfg.cal_l_val = 0x44; + gpll10_cfg.fsm_enable = true; + gpll10_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; + clock_configure_enable_gpll(&gpll10_cfg, true, 9); + } + clock_configure((struct clock_rcg *)&gcc->sdcc1, sdcc1_core_cfg, + hz, ARRAY_SIZE(sdcc1_core_cfg)); + clock_enable(&gcc->sdcc1_ahb_cbcr); + clock_enable(&gcc->sdcc1_apps_cbcr); + } else if (sdcc == SDCC2_CLK) { + if (hz > CLK_100MHZ) { + struct alpha_pll_reg_val_config gpll9_cfg = {0}; + gpll9_cfg.reg_mode = &gcc->gpll9.mode; + gpll9_cfg.reg_opmode = &gcc->gpll9.opmode; + gpll9_cfg.reg_alpha = &gcc->gpll9.alpha; + gpll9_cfg.alpha_val = 0x1555; + gpll9_cfg.reg_l = &gcc->gpll9.l; + gpll9_cfg.l_val = 0x2A; + gpll9_cfg.reg_cal_l = &gcc->gpll9.cal_l; + gpll9_cfg.cal_l_val = 0x44; + gpll9_cfg.fsm_enable = true; + gpll9_cfg.reg_apcs_pll_br_en = &gcc->apcs_pll_br_en; + clock_configure_enable_gpll(&gpll9_cfg, true, 8); + } + clock_configure((struct clock_rcg *)&gcc->sdcc2, sdcc2_core_cfg, + hz, ARRAY_SIZE(sdcc2_core_cfg)); + clock_enable(&gcc->sdcc2_ahb_cbcr); + clock_enable(&gcc->sdcc2_apps_cbcr); + } +} + +void clock_configure_dfsr(int qup) +{ + clock_configure_dfsr_table(qup, qupv3_wrap_cfg, + ARRAY_SIZE(qupv3_wrap_cfg)); +} + +static enum cb_err pll_init_and_set(struct sc7280_apss_clock *apss, u32 l_val) +{ + struct alpha_pll_reg_val_config pll_cfg = {0}; + int ret; + u32 gfmux_val, regval; + + pll_cfg.reg_l = &apss->pll.l; + pll_cfg.l_val = l_val; + + pll_cfg.reg_config_ctl = &apss->pll.config_ctl_lo; + pll_cfg.reg_config_ctl_hi = &apss->pll.config_ctl_hi; + pll_cfg.reg_config_ctl_hi1 = &apss->pll.config_ctl_u1; + + regval = read32(&apss->pll.config_ctl_lo); + pll_cfg.config_ctl_val = regval & + (~(0x2 << K_P_SHFT | 0x2 << K_I_SHFT)); + + regval = read32(&apss->pll.config_ctl_hi); + pll_cfg.config_ctl_hi_val = (regval | (BIT(KLSB_SHFT) | + BIT(RON_MODE_SHFT))) & (~(0x4 << KLSB_SHFT)); + + regval = read32(&apss->pll.config_ctl_u1); + pll_cfg.config_ctl_hi1_val = (regval | BIT(FAST_LOCK_LOW_L_SHFT)) & + ~BIT(DCO_BIAS_ADJ_SHFT); + + ret = clock_configure_enable_gpll(&pll_cfg, false, 0); + if (ret != CB_SUCCESS) + return CB_ERR; + + pll_cfg.reg_mode = &apss->pll.mode; + pll_cfg.reg_opmode = &apss->pll.opmode; + pll_cfg.reg_user_ctl = &apss->pll.user_ctl; + + ret = zonda_pll_enable(&pll_cfg); + if (ret != CB_SUCCESS) + return CB_ERR; + + gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; + gfmux_val |= APCS_SRC_EARLY; + write32(&apss->cfg_gfmux, gfmux_val); + + return CB_SUCCESS; +} + +enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type) +{ + if (gdsc_type > MAX_GDSC) + return CB_ERR; + + return enable_and_poll_gdsc_status(gdsc[gdsc_type]); +} + +enum cb_err mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz, + uint32_t source, uint32_t divider, uint32_t m, + uint32_t n, uint32_t d_2) +{ + struct clock_freq_config mdss_clk_cfg; + uint32_t idx; + + if (clk_type >= MDSS_CLK_COUNT) + return CB_ERR; + + /* Initialize it with received arguments */ + mdss_clk_cfg.div = divider ? QCOM_CLOCK_DIV(divider) : 0; + + if (clk_type == MDSS_CLK_MDP) { + for (idx = 0; idx < ARRAY_SIZE(mdss_mdp_cfg); idx++) { + if (hz <= mdss_mdp_cfg[idx].hz) { + source = mdss_mdp_cfg[idx].src; + mdss_clk_cfg.div = mdss_mdp_cfg[idx].div; + m = 0; + break; + } + } + } + mdss_clk_cfg.src = source; + mdss_clk_cfg.m = m; + mdss_clk_cfg.n = n; + mdss_clk_cfg.d_2 = d_2; + + return clock_configure((struct clock_rcg *)mdss_clock[clk_type], + &mdss_clk_cfg, hz, 0); +} + +enum cb_err mdss_clock_enable(enum clk_mdss clk_type) +{ + if (clk_type >= MDSS_CLK_COUNT) + return CB_ERR; + + /* Enable clock*/ + return clock_enable(mdss_cbcr[clk_type]); +} + +enum cb_err clock_enable_pcie(enum clk_pcie clk_type) +{ + int clk_vote_bit; + + if (clk_type >= PCIE_CLK_COUNT) + return CB_ERR; + + clk_vote_bit = pcie_cfg[clk_type].vote_bit; + if (clk_vote_bit < 0) + return clock_enable(pcie_cfg[clk_type].clk); + + clock_enable_vote(pcie_cfg[clk_type].clk, + pcie_cfg[clk_type].clk_br_en, + pcie_cfg[clk_type].vote_bit); + + return CB_SUCCESS; +} + +enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type) +{ + if (clk_type >= PCIE_CLK_COUNT) + return CB_ERR; + + /* Set clock src */ + write32(pcie_cfg[clk_type].clk, src_type); + + return CB_SUCCESS; +} + +static void speed_up_boot_cpu(void) +{ + /* 1516.8 MHz */ + if (!pll_init_and_set(apss_silver, L_VAL_1516P8MHz)) + printk(BIOS_DEBUG, "Silver Frequency bumped to 1.5168(GHz)\n"); + + /* 1190.4 MHz */ + if (!pll_init_and_set(apss_l3, L_VAL_1190P4MHz)) + printk(BIOS_DEBUG, "L3 Frequency bumped to 1.1904(GHz)\n"); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); + + speed_up_boot_cpu(); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 5b515bd..82c84ae 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -5,6 +5,13 @@ #include <stdint.h> +#define AOSS_CC_BASE 0x0C2A0000 +#define DISP_CC_BASE 0x0AF00000 +#define GCC_BASE 0x00100000 +#define L3_PLL_BASE 0x18284000 +#define QSPI_BASE 0x088DC000 +#define SHRM_SPROC_BASE 0x09051000 +#define SILVER_PLL_BASE 0x18280000 #define TLMM_TILE_BASE 0x0F100000 #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h new file mode 100644 index 0000000..a0694ba --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/clock.h @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <types.h> +#include <soc/clock_common.h> + +#ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__ +#define __SOC_QUALCOMM_SC7280_CLOCK_H__ + +#define SRC_XO_HZ (19200 * KHz) +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) +#define CLK_100MHZ (100 * MHz) + +/* CPU PLL */ +#define L_VAL_1516P8MHz 0x4F +#define L_VAL_1190P4MHz 0x3E + +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) +#define QUPV3_WRAP1_CLK_ENA_1_S(idx) (7 + idx) + +enum clk_pll_src { + SRC_XO_19_2MHZ = 0, + SRC_GPLL0_MAIN_600MHZ = 1, + SRC_GPLL9_MAIN_808MHZ = 2, + SRC_GCC_DISP_GPLL0_CLK = 4, + SRC_GPLL10_MAIN_384MHZ = 5, + SRC_GPLL0_EVEN_300MHZ = 6, +}; + +enum clk_pcie_src_sel { + PCIE_1_PIPE_SRC_SEL = 0, + PCIE_1_XO_SRC_SEL = 2, +}; + +enum apcs_branch_en_vote { + QUPV3_WRAP_0_M_AHB_CLK_ENA = 6, + QUPV3_WRAP_0_S_AHB_CLK_ENA = 7, + QUPV3_WRAP0_CORE_CLK_ENA = 8, + QUPV3_WRAP0_CORE_2X_CLK_ENA = 9, + AGGRE_NOC_PCIE_1_AXI_CLK_ENA = 11, + QUPV3_WRAP1_CORE_2X_CLK_ENA = 18, + AGGRE_NOC_PCIE_TBU_CLK_ENA = 18, + QUPV3_WRAP1_CORE_CLK_ENA = 19, + DDRSS_PCIE_SF_CLK_ENA = 19, + QUPV3_WRAP_1_M_AHB_CLK_ENA = 20, + QUPV3_WRAP_1_S_AHB_CLK_ENA = 21, + PCIE1_PHY_RCHNG_CLK_ENA = 23, + PCIE_1_SLV_Q2A_AXI_CLK_ENA = 25, + PCIE_1_SLV_AXI_CLK_ENA = 26, + PCIE_1_MSTR_AXI_CLK_ENA = 27, + PCIE_1_CFG_AHB_CLK_ENA = 28, + AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA = 28, + PCIE_1_AUX_CLK_ENA = 29, + PCIE_1_PIPE_CLK_ENA = 30, + NO_VOTE_BIT = -1, +}; + +struct sc7280_gpll { + u32 mode; + u32 l; + u32 cal_l; + u32 user_ctl; + u32 user_ctl_u; + u32 user_ctl_u1; + u32 config_ctl; + u32 config_ctl_u; + u32 config_ctl_u1; + u32 test_ctl; + u32 test_ctl_u; + u32 test_ctl_u1; + u8 _res0[0x38 - 0x30]; + u32 opmode; + u8 _res1[0x40 - 0x3c]; + u32 alpha; +}; + +struct sc7280_disp_cc { + u8 _res0[0x1004]; + u32 core_gdsc; + u8 _res1[0x1010 - 0x1008]; + u32 pclk0_cbcr; + u32 mdp_cbcr; + u8 _res2[0x102c - 0x1018]; + u32 vsync_cbcr; + u32 byte0_cbcr; + u32 byte0_intf_cbcr; + u32 esc0_cbcr; + u8 _res3[0x1050 - 0x103c]; + u32 ahb_cbcr; + u8 _res4[0x1078 - 0x1054]; + struct clock_rcg_mnd pclk0; + u8 _res5[0x1090 - 0x108c]; + struct clock_rcg_mnd mdp; + u8 _res6[0x10c0 - 0x1098]; + struct clock_rcg_mnd vsync; + u8 _res7[0x10d8 - 0x10c8]; + struct clock_rcg_mnd byte0; + u8 _res8[0x10f4 - 0x10ec]; + struct clock_rcg_mnd esc0; + u8 _res9[0x1170 - 0x1108]; + struct clock_rcg_mnd ahb; + u8 _res10[0x20000 - 0x1178]; +}; +check_member(sc7280_disp_cc, pclk0_cbcr, 0x1010); +check_member(sc7280_disp_cc, vsync_cbcr, 0x102c); +check_member(sc7280_disp_cc, ahb_cbcr, 0x1050); + +struct sc7280_pcie { + u32 pcie_1_bcr; + u32 gdscr; + u8 _res1[0x18d010 - 0x18d008]; + u32 slv_q2a_axi_cbcr; + u32 slv_axi_cbcr; + u8 _res2[0x18d01c - 0x18d018]; + u32 mstr_axi_cbcr; + u8 _res3[0x18d024 - 0x18d020]; + u32 cfg_ahb_cbcr; + u32 aux_cbcr; + u8 _res4[0x18d030 - 0x18d02c]; + u32 pipe_cbcr; + u8 _res5[0x18d038 - 0x18d034]; + u32 phy_rchng_cbcr; + u8 _res6[0x18d054 - 0x18d03c]; + u32 pipe_muxr; + u8 _res7[0x18d080 - 0x18d058]; + u32 ddrss_pcie_sf_cbcr; + u32 aggre_noc_pcie_axi_cbcr; + u32 aggre_noc_pcie_center_sf_axi_cbcr; + u8 _res8[0x18e01c - 0x18d08c]; + u32 phy_bcr; +}; +check_member(sc7280_pcie, slv_q2a_axi_cbcr, 0x10); +check_member(sc7280_pcie, mstr_axi_cbcr, 0x1c); +check_member(sc7280_pcie, pipe_cbcr, 0x30); +check_member(sc7280_pcie, ddrss_pcie_sf_cbcr, 0x80); +check_member(sc7280_pcie, phy_bcr, 0x101c); + +struct sc7280_gcc { + struct sc7280_gpll gpll0; + u8 _res0[0xf000 - 0x44]; + u32 usb30_prim_bcr; + u8 _res1[0x12000 - 0xf004]; + u32 qusb2phy_prim_bcr; + u32 qusb2phy_sec_bcr; + u8 _res2[0x14004 - 0x12008]; + u32 sdcc2_apps_cbcr; + u32 sdcc2_ahb_cbcr; + struct clock_rcg_mnd sdcc2; + u8 _res3[0x16004 - 0x14020]; + u32 sdcc4_apps_cbcr; + u32 sdcc4_ahb_cbcr; + struct clock_rcg_mnd sdcc4; + u8 _res4[0x17000 - 0x16020]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + struct qupv3_clock qup_wrap0_s[8]; + u8 _res5[0x18000 - 0x1798c]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct qupv3_clock qup_wrap1_s[8]; + u8 _res6[0x1c000 - 0x1898c]; + struct sc7280_gpll gpll9; + u8 _res7[0x1e000 - 0x1c044]; + struct sc7280_gpll gpll10; + u8 _res8[0x23000 - 0x1e044]; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct clock_rcg qup_wrap0_core_2x; + u8 _res9[0x23138 - 0x23014]; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_core_cdivr; + u32 qup_wrap1_core_2x_cbcr; + struct clock_rcg qup_wrap1_core_2x; + u8 _res10[0x27004 - 0x2314c]; + u32 disp_ahb_cbcr; + u8 _res11[0x2700c - 0x27008]; + u32 disp_hf_axi_cbcr; + u8 _res12[0x27014 - 0x27010]; + u32 disp_sf_axi_cbcr; + u8 _res13[0x4b000 - 0x27018]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct clock_rcg qspi_core; + u8 _res14[0x50000 - 0x4b014]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u8 _res15[0x52000 - 0x5000c]; + u32 apcs_clk_br_en; + u8 _res16[0x52008 - 0x52004]; + u32 apcs_clk_br_en1; + u8 _res17[0x52010 - 0x5200c]; + u32 apcs_pll_br_en; + u8 _res18[0x6a000 - 0x52014]; + u32 usb_phy_cfg_ahb2phy_bcr; + u8 _res19[0x75004 - 0x6a004]; + u32 sdcc1_ahb_cbcr; + u32 sdcc1_apps_cbcr; + struct clock_rcg_mnd sdcc1; + u8 _res20[0x8c004 - 0x75020]; + u32 pcie_clkref_en; + u8 _res21[0x8d000 - 0x8c008]; + struct sc7280_pcie pcie_1; + u8 _res22[0x90010 - 0x8e020]; + u32 aggre_noc_pcie_tbu_cbcr; + u8 _res23[0x9e000 - 0x90014]; + u32 usb30_sec_bcr; + u8 _res24[0x1000000 - 0x90014]; +}; +check_member(sc7280_gcc, qusb2phy_prim_bcr, 0x12000); +check_member(sc7280_gcc, sdcc2_apps_cbcr, 0x14004); +check_member(sc7280_gcc, sdcc4_apps_cbcr, 0x16004); +check_member(sc7280_gcc, qup_wrap0_bcr, 0x17000); +check_member(sc7280_gcc, qup_wrap1_bcr, 0x18000); +check_member(sc7280_gcc, qup_wrap1_core_cbcr, 0x23138); +check_member(sc7280_gcc, qspi_bcr, 0x4b000); +check_member(sc7280_gcc, usb3_phy_prim_bcr, 0x50000); +check_member(sc7280_gcc, apcs_clk_br_en1, 0x52008); +check_member(sc7280_gcc, apcs_pll_br_en, 0x52010); +check_member(sc7280_gcc, usb_phy_cfg_ahb2phy_bcr, 0x6a000); +check_member(sc7280_gcc, sdcc1_ahb_cbcr, 0x75004); +check_member(sc7280_gcc, pcie_clkref_en, 0x8c004); +check_member(sc7280_gcc, aggre_noc_pcie_tbu_cbcr, 0x90010); +check_member(sc7280_gcc, usb30_sec_bcr, 0x9e000); + + +struct sc7280_apss_pll { + u32 mode; + u32 l; + u32 alpha; + u32 user_ctl; + u32 config_ctl_lo; + u32 config_ctl_hi; + u32 config_ctl_u1; + u32 test_ctl_lo; + u32 test_ctl_hi; + u32 test_ctl_u1; + u32 opmode; + u8 _res0[0x38 - 0x2c]; + u32 status; +}; + +struct sc7280_apss_clock { + struct sc7280_apss_pll pll; + u8 _res0[0x84 - 0x3c]; + u32 cfg_gfmux; +}; + +struct pcie { + uint32_t *gdscr; + uint32_t *clk; + uint32_t *clk_br_en; + int vote_bit; +}; + +enum clk_sdcc { + SDCC1_CLK, + SDCC2_CLK, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP0_S6, + QUP_WRAP0_S7, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, + QUP_WRAP1_S6, + QUP_WRAP1_S7, +}; + +enum clk_gdsc { + MDSS_CORE_GDSC, + PCIE_1_GDSC, + MAX_GDSC +}; + +enum clk_mdss { + GCC_DISP_AHB, + GCC_DISP_HF_AXI, + GCC_DISP_SF_AXI, + MDSS_CLK_PCLK0, + MDSS_CLK_MDP, + MDSS_CLK_VSYNC, + MDSS_CLK_BYTE0, + MDSS_CLK_BYTE0_INTF, + MDSS_CLK_ESC0, + MDSS_CLK_AHB, + MDSS_CLK_COUNT +}; + +enum clk_pcie { + PCIE_1_SLV_Q2A_AXI_CLK, + PCIE_1_SLV_AXI_CLK, + PCIE_1_MSTR_AXI_CLK, + PCIE_1_CFG_AHB_CLK, + PCIE_1_AUX_CLK, + AGGRE_NOC_PCIE_TBU_CLK, + AGGRE_NOC_PCIE_1_AXI_CLK, + DDRSS_PCIE_SF_CLK, + PCIE1_PHY_RCHNG_CLK, + AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, + PCIE_1_PIPE_CLK, + PCIE_CLKREF_EN, + GCC_PCIE_1_PIPE_MUXR, + PCIE_CLK_COUNT, +}; + +enum subsystem_reset { + AOP_RESET_SHFT = 0, + SHRM_RUN_STALL = 0, +}; + +enum pll_config_ctl_lo { + CTUNE_SHFT = 2, + K_I_SHFT = 4, + K_P_SHFT = 7, + PFA_MSB_SHFT = 10, + RES_BIT_SHFT = 14, + RON_DEGEN_MUL_SHFT = 18, + ALPHA_CAL_SHFT = 20, + DCO_ADDER_EN_SHFT = 22, + PLL_COUNTER_EN = 27, +}; + +enum pll_config_ctl_hi { + CUR_TRIM_SHFT = 0, + FREQ_DOUBLE_SHFT = 4, + ADJ_ENABLE_SHFT = 5, + ADJ_VALUE_SHFT = 6, + KLSB_SHFT = 13, + RON_MODE_SHFT = 17, + CHP_REF_SHFT = 19, + CHP_STARTUP = 21, + ADC_KMSB_VAL = 23, +}; + +enum pll_config_ctl_u1 { + FAST_LOCK_LOW_L_SHFT = 4, + DCO_BIAS_ADJ_SHFT = 26, +}; + +enum apss_gfmux { + GFMUX_SRC_SEL_BMSK = 0x3, + APCS_SRC_EARLY = 0x2, +}; + +static struct sc7280_gcc *const gcc = (void *)GCC_BASE; +static struct sc7280_apss_clock *const apss_silver = (void *)SILVER_PLL_BASE; +static struct sc7280_apss_clock *const apss_l3 = (void *)L3_PLL_BASE; +static struct sc7280_disp_cc *const mdss = (void *)DISP_CC_BASE; + +void clock_init(void); +void clock_configure_qspi(uint32_t hz); +void clock_enable_qup(int qup); +void clock_configure_sdcc(enum clk_sdcc, uint32_t hz); +void clock_configure_dfsr(int qup); +int clock_enable_gdsc(enum clk_gdsc gdsc_type); + +int mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz, + uint32_t source, uint32_t divider, + uint32_t m, uint32_t n, uint32_t d); +int mdss_clock_enable(enum clk_mdss clk_type); +int clock_enable_pcie(enum clk_pcie clk_type); +int clock_configure_mux(enum clk_pcie clk_type, u32 src_type); + +/* Subsystem Reset */ +static struct aoss *const aoss = (void *)AOSS_CC_BASE; +static struct shrm *const shrm = (void *)SHRM_SPROC_BASE; + +#define clock_reset_aop() \ + clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT) +#define clock_reset_shrm() \ + clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL) + +#endif // __SOC_QUALCOMM_SC7280_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 64 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit September 2021