coreboot-gerrit September 2021

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Change in coreboot[master]: util/sconfig: Refactor handling of SMBIOS data
by Angel Pons (Code Review) 03 Sep '21

03 Sep '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57369 ) Change subject: util/sconfig: Refactor handling of SMBIOS data ...................................................................... util/sconfig: Refactor handling of SMBIOS data Extract the code that handles devices' SMBIOS data into a helper function, and add another helper function to check if any SMBIOS information is present. Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/sconfig/main.c 1 file changed, 37 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57369/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index f7d1d10..a9634dd 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1108,6 +1108,40 @@ ptr->name); } +static int have_smbios_data(struct device *ptr) +{ + return (ptr->smbios_slot_type || + ptr->smbios_slot_data_width || + ptr->smbios_slot_designation || + ptr->smbios_slot_length); +} + +static void emit_smbios_data(FILE *fil, struct device *ptr) +{ + if (!have_smbios_data(ptr)) + return; + + fprintf(fil, "#if !DEVTREE_EARLY\n"); + fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); + + /* SMBIOS types start at 1, if zero it hasn't been set */ + if (ptr->smbios_slot_type) + fprintf(fil, "\t.smbios_slot_type = %s,\n", + ptr->smbios_slot_type); + if (ptr->smbios_slot_data_width) + fprintf(fil, "\t.smbios_slot_data_width = %s,\n", + ptr->smbios_slot_data_width); + if (ptr->smbios_slot_designation) + fprintf(fil, "\t.smbios_slot_designation = \"%s\",\n", + ptr->smbios_slot_designation); + if (ptr->smbios_slot_length) + fprintf(fil, "\t.smbios_slot_length = %s,\n", + ptr->smbios_slot_length); + + fprintf(fil, "#endif\n"); + fprintf(fil, "#endif\n"); +} + static void emit_resources(FILE *fil, struct device *ptr) { if (ptr->res == NULL) @@ -1266,29 +1300,9 @@ chip_ins->chip->name_underscore, chip_ins->id); if (next) fprintf(fil, "\t.next=&%s,\n", next->name); - if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || - ptr->smbios_slot_designation || ptr->smbios_slot_length) { - fprintf(fil, "#if !DEVTREE_EARLY\n"); - fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); - } - /* SMBIOS types start at 1, if zero it hasn't been set */ - if (ptr->smbios_slot_type) - fprintf(fil, "\t.smbios_slot_type = %s,\n", - ptr->smbios_slot_type); - if (ptr->smbios_slot_data_width) - fprintf(fil, "\t.smbios_slot_data_width = %s,\n", - ptr->smbios_slot_data_width); - if (ptr->smbios_slot_designation) - fprintf(fil, "\t.smbios_slot_designation = \"%s\",\n", - ptr->smbios_slot_designation); - if (ptr->smbios_slot_length) - fprintf(fil, "\t.smbios_slot_length = %s,\n", - ptr->smbios_slot_length); - if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || - ptr->smbios_slot_designation || ptr->smbios_slot_length) { - fprintf(fil, "#endif\n"); - fprintf(fil, "#endif\n"); - } + + emit_smbios_data(fil, ptr); + fprintf(fil, "};\n"); emit_resources(fil, ptr); -- To view, visit https://review.coreboot.org/c/coreboot/+/57369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e Gerrit-Change-Number: 57369 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants: fix override values for power limits
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Sumeet Pawnikar, Furquan Shaikh, Paul Menzel, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57290 ) Change subject: mb/google/brya/variants: fix override values for power limits ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57290/comment/00be33bc_0ea6b23b PS4, Line 9: There are two different types of 682 SKU available with TDP of 28W and 45W. : This patch fix override values for power limits for these 682 SKU. : This patch also sets power limit values dynamically based on machine ID and : CPU TDP of SKU. > reflow for 72 characters wide please Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Gerrit-Change-Number: 57290 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57102 ) Change subject: mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4 ...................................................................... mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4 Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated to I2C4. BUG=NA BRANCH=None TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned and does not conflict with I2C. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer 1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00 16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6 22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0 37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1 41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi 42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2 43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3 Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: Id0f3885dec5a6f635254c233709090321491c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 12048dc..68c561a 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -170,7 +170,10 @@ /* F17 : RST_N_TCH_PNL2 */ PAD_CFG_GPO(GPP_F17, 1, PLTRST), /* F18 : INT_N_TCH_PNL2 */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE) + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), + + /* E3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/57102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0f3885dec5a6f635254c233709090321491c739 Gerrit-Change-Number: 57102 Gerrit-PatchSet: 13 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*: move reset_i2c_peripherals call after early GPIO setup
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57291 ) Change subject: soc/amd/*: move reset_i2c_peripherals call after early GPIO setup ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Looking at the flow, do you think we should make an explicit call to initialize the GPIOs instead of […] hmm, that's a good point -- To view, visit https://review.coreboot.org/c/coreboot/+/57291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Gerrit-Change-Number: 57291 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially
by Subrata Banik (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Ronak Kanabar, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57343 ) Change subject: drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57343/comment/71dd62e2_ffd1a3f4 PS1, Line 17: But another MP service API `StartupAllCPUs` doesn't specifies any such : requirement. Running the `func` simultaneously on APs results into : coherency issue due to lack of acquire spin lock while accessing common : data structure in multiprocessor environment. > But right here, in the MpServices2 interface (https://github. […] yes, Tim, I also have same understanding, its upto the routine what we wish to run of APs and how that routine is being written to block access to its data structure. In this case, I felt the implementation owner doesn't pay attention on the merit of the routine and implication how it would execute on APs serially or simultaneously. I'm thinking on two options 1. as you said, if caller would like to run on all CPUs(BSP + APs) serially or simultaneously then it should use StartupAllAPs => I believe as StartupAllAPs is limited to run only on APs and not on BSP hence they have decided to introduce new API as StartupAllCPUs 2. I would expect EDK2 to provide again one more argument to let caller decides to run routine on CPUs either serially or simultaneously rather fixed design (which is simultaneously, set as FALSE). The suspected routine is being implemented with assumption that it shouldn't run concurrently but its end up doing the same unfortunately -- To view, visit https://review.coreboot.org/c/coreboot/+/57343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Gerrit-Change-Number: 57343 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:25:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: add conn_get_type_c_list()
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: add conn_get_type_c_list() ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/6e19dbed_1624fb8e PS3, Line 111: pmc = pcidev_path_on_root(PCH_DEVFN_PMC); : if (!pmc || !pmc->link_list->children) { : printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); : return NULL; : } : I kinda think the PMC device should be passed in to this function instead, so that `drivers` doesn't have to worry about any SoC specific things here. This function mostly exists because this file has direct knowledge of `drivers_intel_pmc_mux_conn_ops`, and I'd like to avoid sprinkling the `extern drivers_....ops` more and just switch to functions like this intead 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:23:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/leafhill,minnow3: remove ADD_FSP_BINARIES config override
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57346 ) Change subject: mb/intel/leafhill,minnow3: remove ADD_FSP_BINARIES config override ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I'm not sure about these - I think it's entirely reasonable to want to add an FSP from someplace oth […] having that overridable might be useful, but that should be done at the fsp driver Kconfig level and not at mainboard Kconfig level -- To view, visit https://review.coreboot.org/c/coreboot/+/57346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5 Gerrit-Change-Number: 57346 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:19:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57349 ) Change subject: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Should we split the ADD_FSP_BINARIES for AMD & Intel? Select it only for intel boards if FSP_USE_RE […] in the Intel case ADD_FSP_BINARIES is default y if FSP_USE_REPO and I added select ADD_FSP_BINARIES if USE_AMD_BLOBS for Picasso which is currently the only AMD platform with published FSP. might be a good idea to rename FSP_USE_REPO to FSP_USE_INTEL_REPO, but I'm not sure if that'll break local configs -- To view, visit https://review.coreboot.org/c/coreboot/+/57349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 Gerrit-Change-Number: 57349 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add tpch device information under dptf
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57097 ) Change subject: soc/intel/alderlake: Add tpch device information under dptf ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Gerrit-Change-Number: 57097 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56809 ) Change subject: sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c Gerrit-Change-Number: 56809 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:17:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2021