Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57102 )
Change subject: mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4 ......................................................................
mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4
Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated to I2C4.
BUG=NA BRANCH=None TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned and does not conflict with I2C. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer 1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00 16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6 22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0 37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1 41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi 42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2 43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3
Signed-off-by: Selma Bensaid selma.bensaid@intel.com Change-Id: Id0f3885dec5a6f635254c233709090321491c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102 Reviewed-by: Bora Guvendik bora.guvendik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 12048dc..68c561a 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -170,7 +170,10 @@ /* F17 : RST_N_TCH_PNL2 */ PAD_CFG_GPO(GPP_F17, 1, PLTRST), /* F18 : INT_N_TCH_PNL2 */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE) + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), + + /* E3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) };
void variant_configure_gpio_pads(void)