coreboot-gerrit September 2021

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Change in coreboot[master]: soc/intel/cannonlake: Clear RTC_BATTERY_DEAD
by Angel Pons (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56668 ) Change subject: soc/intel/cannonlake: Clear RTC_BATTERY_DEAD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54f519edb9f4295f83a581db9cb43f5ae5d0d483 Gerrit-Change-Number: 56668 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 17:05:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add argument for CSE fixed client addr
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Sridhar Siricilla, Aseda Aboagye, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57295 ) Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Patchset: PS10: Thanks Rizwan! Nice cleanup 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 10 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 17:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable thermal control functionality for tpch
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57098 to look at the new patch set (#6). Change subject: mb/google/brya: Enable thermal control functionality for tpch ...................................................................... mb/google/brya: Enable thermal control functionality for tpch Enable DPTF based thermal control functionality for tpch device on brya device. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57098/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/57098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Gerrit-Change-Number: 57098 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add tpch device information under dptf
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57097 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Add tpch device information under dptf ...................................................................... soc/intel/alderlake: Add tpch device information under dptf Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/dptf.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/57097/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Gerrit-Change-Number: 57097 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add new thermal control mechanism for pch device
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57096 to look at the new patch set (#7). Change subject: drivers/intel/dptf: Add new thermal control mechanism for pch device ...................................................................... drivers/intel/dptf: Add new thermal control mechanism for pch device Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h 3 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/57096/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Introduce new thermal control mechanism for pch d...
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 ) Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57096/comment/a756694b_4646ad2d PS5, Line 211: acpigen_emit_byte(RETURN_OP); : acpigen_write_package(0); : acpigen_write_package_end(); > Can you add a comment then that the reason for returning a value here is a W/A for the ESIF shell? ACK -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 17:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Clear RTC_BATTERY_DEAD
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56617 ) Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > pong 😆 -- To view, visit https://review.coreboot.org/c/coreboot/+/56617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc21c19ea8ce561e9655e189ec26aba7a07967e Gerrit-Change-Number: 56617 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 17:00:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Hsuan-ting Chen, Julius Werner, Andrey Petrov, Patrick Rudolph, Yu-Ping Wu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57048 ) Change subject: vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57048/comment/47425c16_db3fa0bc PS1, Line 9: We will introduce a new ctx field stores the current bootmode in > suggestion: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Gerrit-Change-Number: 57048 Gerrit-PatchSet: 6 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 16:59:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common/qspi: Add support for common QSPI driver
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55323 ) Change subject: soc/qualcomm/common/qspi: Add support for common QSPI driver ...................................................................... soc/qualcomm/common/qspi: Add support for common QSPI driver copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder. This common QSPI driver works in master mode and provides read/write operation for the slave devices like flash. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org> Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- R src/soc/qualcomm/common/include/soc/qspi_common.h R src/soc/qualcomm/common/qspi.c A src/soc/qualcomm/common/spi.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h D src/soc/qualcomm/sc7180/spi.c 7 files changed, 66 insertions(+), 69 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/common/include/soc/qspi_common.h similarity index 80% rename from src/soc/qualcomm/sc7180/include/soc/qspi.h rename to src/soc/qualcomm/common/include/soc/qspi_common.h index bad3071..a0f612c 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qspi.h +++ b/src/soc/qualcomm/common/include/soc/qspi_common.h @@ -3,10 +3,10 @@ #include <soc/addressmap.h> #include <spi-generic.h> -#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__ -#define __SOC_QUALCOMM_SC7180_QSPI_H__ +#ifndef __SOC_QUALCOMM_QSPI_H__ +#define __SOC_QUALCOMM_QSPI_H__ -struct sc7180_qspi_regs { +struct qcom_qspi_regs { u32 mstr_cfg; u32 ahb_mstr_cfg; u32 reserve_0; @@ -28,8 +28,8 @@ u32 rd_fifo[16]; }; -check_member(sc7180_qspi_regs, rd_fifo, 0x50); -static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE; +check_member(qcom_qspi_regs, rd_fifo, 0x50); +static struct qcom_qspi_regs * const qcom_qspi = (void *) QSPI_BASE; // MSTR_CONFIG register @@ -98,11 +98,11 @@ #define QSPI_MAX_PACKET_COUNT 0xFFC0 void quadspi_init(uint32_t hz); -int sc7180_claim_bus(const struct spi_slave *slave); -int sc7180_setup_bus(const struct spi_slave *slave); -void sc7180_release_bus(const struct spi_slave *slave); -int sc7180_xfer(const struct spi_slave *slave, const void *dout, +int qspi_claim_bus(const struct spi_slave *slave); +int qspi_setup_bus(const struct spi_slave *slave); +void qspi_release_bus(const struct spi_slave *slave); +int qspi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes); -int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, +int qspi_xfer_dual(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes); -#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */ +#endif /* __SOC_QUALCOMM_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/common/qspi.c similarity index 85% rename from src/soc/qualcomm/sc7180/qspi.c rename to src/soc/qualcomm/common/qspi.c index 825e298..b6d2b2d 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -5,7 +5,7 @@ #include <arch/cache.h> #include <device/mmio.h> #include <soc/addressmap.h> -#include <soc/qspi.h> +#include <soc/qspi_common.h> #include <soc/gpio.h> #include <soc/clock.h> #include <symbols.h> @@ -65,11 +65,11 @@ { uint32_t mstr_int_status; - write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&qcom_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); while (1) { - mstr_int_status = read32(&sc7180_qspi->mstr_int_sts); + mstr_int_status = read32(&qcom_qspi->mstr_int_sts); if (mstr_int_status & DMA_CHAIN_DONE) break; } @@ -138,20 +138,20 @@ static void cs_change(enum cs_state state) { - gpio_set(GPIO(68), state == CS_DEASSERT); + gpio_set(QSPI_CS, state == CS_DEASSERT); } static void configure_gpios(void) { - gpio_output(GPIO(68), 1); + gpio_output(QSPI_CS, 1); - gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, + gpio_configure(QSPI_DATA_0, GPIO_FUNC_QSPI_DATA_0, GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); - gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, + gpio_configure(QSPI_DATA_1, GPIO_FUNC_QSPI_DATA_1, GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); - gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, + gpio_configure(QSPI_CLK, GPIO_FUNC_QSPI_CLK, GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); } @@ -240,12 +240,12 @@ (DMA_ENABLE) | (FULL_CYCLE_MODE); - write32(&sc7180_qspi->mstr_cfg, mstr_config); - write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42); - write32(&sc7180_qspi->mstr_int_en, 0x0); - write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sc7180_qspi->rd_fifo_cfg, 0x0); - write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO); + write32(&qcom_qspi->mstr_cfg, mstr_config); + write32(&qcom_qspi->ahb_mstr_cfg, 0xA42); + write32(&qcom_qspi->mstr_int_en, 0x0); + write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&qcom_qspi->rd_fifo_cfg, 0x0); + write32(&qcom_qspi->rd_fifo_rst, RESET_FIFO); } void quadspi_init(uint32_t hz) @@ -256,13 +256,13 @@ reg_init(); } -int sc7180_claim_bus(const struct spi_slave *slave) +int qspi_claim_bus(const struct spi_slave *slave) { cs_change(CS_ASSERT); return 0; } -void sc7180_release_bus(const struct spi_slave *slave) +void qspi_release_bus(const struct spi_slave *slave) { cs_change(CS_DEASSERT); } @@ -283,13 +283,13 @@ return 0; } -int sc7180_xfer(const struct spi_slave *slave, const void *dout, +int qspi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes) { return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); } -int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, +int qspi_xfer_dual(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes) { return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); diff --git a/src/soc/qualcomm/common/spi.c b/src/soc/qualcomm/common/spi.c new file mode 100644 index 0000000..b4db3e5 --- /dev/null +++ b/src/soc/qualcomm/common/spi.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <soc/qspi_common.h> + +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = qspi_claim_bus, + .release_bus = qspi_release_bus, + .xfer = qspi_xfer, + .xfer_dual = qspi_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &qspi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 83f9eb5..048faf5 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -5,12 +5,12 @@ decompressor-y += mmu.c decompressor-y += ../common/timer.c all-y += ../common/timer.c -all-y += spi.c all-y += ../common/gpio.c +all-y += ../common/spi.c +all-$(CONFIG_SC7180_QSPI) += ../common/qspi.c all-y += qupv3_i2c.c all-y += qupv3_spi.c all-y += clock.c -all-$(CONFIG_SC7180_QSPI) += qspi.c all-y += ../common/clock.c all-y += qcom_qup_se.c all-y += qupv3_config.c diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index cfeb6f9..be79ba6 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -2,7 +2,7 @@ #include <bootblock_common.h> #include <soc/clock.h> -#include <soc/qspi.h> +#include <soc/qspi_common.h> #include <soc/qupv3_config.h> void bootblock_soc_init(void) diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 832ef42..e360e8a 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -46,4 +46,14 @@ #define QMP_PHY_PCS_REG_BASE 0x088e9c00 #define USB_HOST_DWC3_BASE 0x0a60c100 +/* SC7180 QSPI GPIO PINS */ +#define QSPI_CLK GPIO(63) +#define QSPI_DATA_0 GPIO(64) +#define QSPI_DATA_1 GPIO(65) +#define QSPI_CS GPIO(68) + +#define GPIO_FUNC_QSPI_DATA_0 GPIO64_FUNC_QSPI_DATA_0 +#define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1 +#define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c deleted file mode 100644 index 45abe90..0000000 --- a/src/soc/qualcomm/sc7180/spi.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <spi-generic.h> -#include <spi_flash.h> -#include <soc/qspi.h> -#include <soc/qupv3_spi.h> - -static const struct spi_ctrlr qspi_ctrlr = { - .claim_bus = sc7180_claim_bus, - .release_bus = sc7180_release_bus, - .xfer = sc7180_xfer, - .xfer_dual = sc7180_xfer_dual, - .max_xfer_size = QSPI_MAX_PACKET_COUNT, -}; - -const struct spi_ctrlr spi_qup_ctrlr = { - .claim_bus = qup_spi_claim_bus, - .release_bus = qup_spi_release_bus, - .xfer = qup_spi_xfer, - .max_xfer_size = 65535, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &qspi_ctrlr, - .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - }, - { - .ctrlr = &spi_qup_ctrlr, - .bus_start = 0, - .bus_end = 11, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/55323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Gerrit-Change-Number: 55323 Gerrit-PatchSet: 24 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/qualcomm/sc7280: DDR One-Time-Training Support
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54352 ) Change subject: soc/qualcomm/sc7280: DDR One-Time-Training Support ...................................................................... soc/qualcomm/sc7280: DDR One-Time-Training Support Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/chromeos.fmd M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd index a44a638..e85271c 100644 --- a/src/mainboard/google/herobrine/chromeos.fmd +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -17,7 +17,7 @@ RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 32K RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 1589ffb..64e5008 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -37,14 +37,14 @@ STACK(0x1484B000, 16K) VBOOT2_WORK(0x1484F000, 12K) DMA_COHERENT(0x14853000, 8K) - REGION(ddr_training, 0x14855000, 8K, 4K) REGION(qclib_serial_log, 0x14857000, 4K, 4K) CBFS_MCACHE(0x14858000,16K) REGION(ddr_information, 0x1485C000, 1K, 1K) FMAP_CACHE(0x1485C400, 2K) REGION(dcb, 0x1485E000, 32K, 4K) REGION(pmic, 0x14866000, 96K, 4K) - REGION(qclib, 0x1487E000, 840K, 4K) + REGION(ddr_training, 0x1487E000, 32K, 4K) + REGION(qclib, 0x14886000, 800K, 4K) BSRAM_END(0x14950000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/54352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Gerrit-Change-Number: 54352 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit September 2021