Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56783 )
Change subject: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips ......................................................................
soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
southbridge/amd/pi/hudson uses the common GPIO bank access code from soc/amd, but doesn't provide all functionality that would be needed to use the full functionality. Add a Kconfig option that switches off some functionality in the common SoC GPIO access code, so that more of the functionality proviced by the common SoC GPIO code can be used in the AMD binaryPI chipset and board code.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783 Reviewed-by: Martin Roth martinroth@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/gpio_banks/Kconfig M src/soc/amd/common/block/gpio_banks/gpio.c M src/southbridge/amd/pi/hudson/Kconfig 3 files changed, 17 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig index 1efb1db..0a1bffe 100644 --- a/src/soc/amd/common/block/gpio_banks/Kconfig +++ b/src/soc/amd/common/block/gpio_banks/Kconfig @@ -5,3 +5,16 @@ Select this option to use the newer style banks of GPIO signals. These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio base. + +if SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + +config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE + bool + help + Select this option when selecting the GPIO bank support from AMD + chipsets outside the soc/ subtree that only support a subset of the + features available on the chipsets inside the soc/ subtree. When this + option is selected, no SMI or SCI event can be configured by the GPIO + code. + +endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 8f84cb6..b3c1ac1 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -171,8 +171,9 @@ static const struct soc_amd_event *gev_tbl; static size_t gev_items; int gevent_num; - const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && - ENV_SEPARATE_VERSTAGE); + const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + ENV_SEPARATE_VERSTAGE) || + CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE));
set_gpio_mux(g->gpio, g->function);
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index fa60d17..c959e28 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -18,6 +18,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config EHCI_BAR