coreboot-gerrit March 2021

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Change in coreboot[master]: util/spd_tools/lp4x: Add 2 new parts to global memory definition
by Martin Roth (Code Review) 02 Mar '21

02 Mar '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51057 ) Change subject: util/spd_tools/lp4x: Add 2 new parts to global memory definition ...................................................................... util/spd_tools/lp4x: Add 2 new parts to global memory definition This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index ffb08c7..fcbe624 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -229,6 +229,32 @@ "ranksPerChannel": 1, "speedMbps": 4267 } + }, + { + "name": "NT6AP256T32AV-J1", + "attribs": { + "densityPerChannelGb": 4, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 1, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267, + "tckMaxPs": 1250, + "casLatencies": "14 20 24 28 32 36" + } + }, + { + "name": "MT53E1G32D4NQ-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/51057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Gerrit-Change-Number: 51057 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50294 to look at the new patch set (#17). Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... vendor: mediatek: Add mediatek mt8192 dram initialization codes This is the DRAM initialization code from the reference implementation released by Mediatek for MT8192. The DRAM calibration code can be took as an standalone library, used by different boot loaders for initializing DRAM and following a different coding style(coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- M MAINTAINERS A src/vendorcode/mediatek/Kconfig A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8192/dramc/emi.c A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8192/include/addressmap.h A src/vendorcode/mediatek/mt8192/include/custom_emi.h A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_common.h A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h A src/vendorcode/mediatek/mt8192/include/dramc_register.h A src/vendorcode/mediatek/mt8192/include/dramc_top.h A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8192/include/emi.h A src/vendorcode/mediatek/mt8192/include/emi_hw.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h A src/vendorcode/mediatek/mt8192/include/memory.h A src/vendorcode/mediatek/mt8192/include/print.h A src/vendorcode/mediatek/mt8192/include/reg.h A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8192/include/x_hal_io.h A src/vendorcode/mediatek/mt8192/lib/Makefile.inc A src/vendorcode/mediatek/mt8192/lib/print.c 56 files changed, 85,621 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 17 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51194 to look at the new patch set (#5). Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that the devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 81 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 5 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph. Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51194 ) Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... Patch Set 4: (4 comments) File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/51194/comment/5a7c31b4_1afde906 PS1, Line 250: Enables TCSS to initialize devices before Kernel. > Sets up USB2/3 port mapping in TCSS Mux and sets MUX state to disconnected. changed wording in next patch update File src/soc/intel/tigerlake/early_tcss.c: https://review.coreboot.org/c/coreboot/+/51194/comment/bce36e4b_8c79637b PS1, Line 267: initialize_mux_to_disc_mode > Probably just say `tcss_init_mux()`? It does two things: […] will rename in next patch update https://review.coreboot.org/c/coreboot/+/51194/comment/49530a45_7fb02d1f PS1, Line 274: inial > initial fixed in next patch update https://review.coreboot.org/c/coreboot/+/51194/comment/f6d0f48a_8a20d3ac PS1, Line 277: update_tcss_mux > I think this should be renamed to `tcss_configure_dp_mode()` so that the intent is clear. will rename in next patch update -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 4 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 03:01:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51194 to look at the new patch set (#4). Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that the devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 79 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 4 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update telemetry settings
by Frank Wu (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: John Su, Martin Roth, Chris Wang, Rob Barnes. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51165 ) Change subject: mb/google/zork/var/vilboz: Update telemetry settings ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi Google, Would you help to merge the CL? Then we can have official CPFE FW to verify the issue after cherry-picking it to zork firmware branch. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/51165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec Gerrit-Change-Number: 51165 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 02:16:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Hung-Te Lin (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... Patch Set 16: (3 comments) File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/38cdd0be_862cf9a9 PS16, Line 3: config DEBUG_DRAM : bool "Output verbose DRAM related debug messages" : default y : help : This option enables additional DRAM related debug messages. > > I wonder if we can revise it to something like [...] […] What Angel suggested sounds good. @Xixi please make the change, and we should fix 8173 and 8183 in the same way (use DEBUG_RAM_SETUP) in the follow up changes. File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c: PS13: > I assume that is more about SPDX specifically than about the license in general. […] Got it, and I think Xixi also said they can add SPDX. File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c: https://review.coreboot.org/c/coreboot/+/50294/comment/5da0b2e1_eae80abf PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Just from a practical perspective: while I do love the GPL and want everyone to use it in general, p […] I also prefer BSD3. @xixi please check with your internal teams and move to BSD3 if possible. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 16 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 02:15:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Introduce pctl_start
by Julius Werner (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Moritz Fischer. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51129 ) Change subject: soc/rockchip/rk3399/sdram: Introduce pctl_start ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51129/comment/e35b52bc_f962dff1 PS1, Line 9: Adapted from u-boot commit a0aebe8398 ("ram: rk3399: Add pctl start Can you please also explain what this actually does and why it is necessary? File src/soc/rockchip/rk3399/sdram.c: https://review.coreboot.org/c/coreboot/+/51129/comment/6d183aed_a4371449 PS1, Line 97: con I think this should be called get_ddrc_con0, not get_ddrc0_con (that's something U-Boot didn't update when they later fixed which of these is the channel-dependent one). https://review.coreboot.org/c/coreboot/+/51129/comment/1931e304_998322a5 PS1, Line 347: write32(&ddrc0_con, 0x01000000); This is one of the special Rockchip write-mask registers, so what you're actually doing here is clearing bit 8 (ddr_ie_polarity). Please write this as write32(&ddrc_con0, RK_CLRBITS(1 << 8)); (or define a DDR_CON_IE_POLARITY (1 << 8) somewhere and use that). https://review.coreboot.org/c/coreboot/+/51129/comment/e6993dab_b6d2855f PS1, Line 360: write32(&ddrc0_con, 0x01000100); This would then be write32(&ddr_con0, RK_SETBITS(1 << 8)); -- To view, visit https://review.coreboot.org/c/coreboot/+/51129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcea403218ba96ec48c889709b73df4e8882d825 Gerrit-Change-Number: 51129 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Moritz Fischer <moritzf(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 02:13:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/generic/alc1015: add ALC1015 AMP driver
by Kangheui Won (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Frank Wu, Martin Roth, Tim Wawrzynczak, EricR Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51051 ) Change subject: drivers/generic/alc1015: add ALC1015 AMP driver ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79 Gerrit-Change-Number: 51051 Gerrit-PatchSet: 6 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 02:08:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array
by Julius Werner (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Moritz Fischer. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51128 ) Change subject: soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array ...................................................................... Patch Set 1: (1 comment) File src/soc/rockchip/rk3399/sdram.c: https://review.coreboot.org/c/coreboot/+/51128/comment/eca92a20_5473cdf3 PS1, Line 95: u32 pwrup_srefresh_exit[MAX_DRAM_CHANNELS]; Let's try to avoid using globals to pass values between functions where possible. Looks like your goal is just to pass this from pctl_cfg() to pctl_start() which runs right afterwards. Can we instead not just call pctl_start() from within pctl_cfg() (at the end), so that this can just be a local passed along as a parameter? -- To view, visit https://review.coreboot.org/c/coreboot/+/51128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84fe0bc2dbc9874facfa35534b871ec049cb26bb Gerrit-Change-Number: 51128 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Moritz Fischer <moritzf(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 01:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2021