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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51178 )
Change subject: mb/google/brya: fix BT enumeration issue
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
@Tim, could we change the name? I checked deltan it use PCH_BT_RADIO_DIS. But ACPI said it reset_gpio? IMO, it is RF-kill purpose, right?
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Change subject: soc/intel/skylake: Do not unhide P2SB before disabling HECI
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/51205/comment/88a5c340_7e2c228c
PS3, Line 37: p2sb_unhide();
i don't really understand the motivation here.
Typically, FSP hides P2SB post FSP-S and we want to unhide to program HECI disable and again line 70, we like to hide it prior to boot to OS.
As per security guideline, P2SB need to hide from bus when we boot to OS.
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Change subject: mb/dell: Add OptiPlex 3010
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Yeah I already fixed that a while back
coreboot-4.13-2425-gd5c8a15d74 Tue Mar 2 23:14:06 UTC 2021 bootblock starting (log level: 7)...
FMAP: area COREBOOT found @ 270200 (5832192 bytes)
CBFS: mcache @0xfeff0e00 built for 13 files, used 0x274 of 0x2000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0x16b7c in mcache @0xfeff0e2c
BS: bootblock times (exec / console): total (unknown) / 3 ms
coreboot-4.13-2425-gd5c8a15d74 Tue Mar 2 23:14:06 UTC 2021 romstage starting (log level: 7)...
SMBus controller enabled
Setting up static northbridge registers... done
Graphics not supported by this CPU/chipset.
Back from systemagent_early_init()
ASSERTION ERROR: file 'src/superio/smsc/sch5545/sch5545_emi.c', line 58
sch5545_ec_hwm_early_init
is what I get when I use a 9010 rom on this device. Think that's a dead end.
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Change subject: drivers/generic/alc1015: add ALC1015 AMP driver
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
fix bug since remove the hid, no need to check..
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Kangheui Won, Paul Menzel, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/generic/alc1015: add ALC1015 AMP driver
......................................................................
drivers/generic/alc1015: add ALC1015 AMP driver
Add ALC1015 AMP support.
ALC1015Q-VB Datasheet Rev 0.1
BUG=b:177971830
TEST: ALC1015P driver can probe properly.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79
---
A src/drivers/generic/alc1015/Kconfig
A src/drivers/generic/alc1015/Makefile.inc
A src/drivers/generic/alc1015/alc1015.c
A src/drivers/generic/alc1015/chip.h
4 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/51051/7
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu,
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes
......................................................................
vendor: mediatek: Add mediatek mt8192 dram initialization codes
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be took as an standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style(coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
---
M MAINTAINERS
A src/vendorcode/mediatek/Kconfig
A src/vendorcode/mediatek/Makefile.inc
A src/vendorcode/mediatek/mt8192/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
A src/vendorcode/mediatek/mt8192/dramc/emi.c
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h
A src/vendorcode/mediatek/mt8192/include/addressmap.h
A src/vendorcode/mediatek/mt8192/include/custom_emi.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_common.h
A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h
A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h
A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h
A src/vendorcode/mediatek/mt8192/include/dramc_register.h
A src/vendorcode/mediatek/mt8192/include/dramc_top.h
A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h
A src/vendorcode/mediatek/mt8192/include/emi.h
A src/vendorcode/mediatek/mt8192/include/emi_hw.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h
A src/vendorcode/mediatek/mt8192/include/memory.h
A src/vendorcode/mediatek/mt8192/include/print.h
A src/vendorcode/mediatek/mt8192/include/reg.h
A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
A src/vendorcode/mediatek/mt8192/include/x_hal_io.h
A src/vendorcode/mediatek/mt8192/lib/Makefile.inc
A src/vendorcode/mediatek/mt8192/lib/print.c
56 files changed, 85,621 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/17
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph,
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Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3 devices
to downgrade to USB2 speed. To properly configure the Type C ports the muxes
should be set to disconnected state during boot so that the port mapping of
USB2/3 devices is properly setup prior to Kernel initializing devices.
BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple times
to verify that the devices were no longer downgrading to USB2 speed.
Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/early_tcss.c
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/early_tcss.h
5 files changed, 81 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/5
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