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Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 )
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(2 comments)
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/50294/comment/0e955ac9_0c792c8f
PS18, Line 620: k/
> If the section is "MT8192" then you should have this as […]
Done
https://review.coreboot.org/c/coreboot/+/50294/comment/bbbf42de_31f3ba89
PS18, Line 621: mt8192
> mt8192/ […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
vendor: mediatek: Add mediatek mt8192 dram initialization code
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
---
M MAINTAINERS
A src/vendorcode/mediatek/Makefile.inc
A src/vendorcode/mediatek/mt8192/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
A src/vendorcode/mediatek/mt8192/dramc/emi.c
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h
A src/vendorcode/mediatek/mt8192/include/addressmap.h
A src/vendorcode/mediatek/mt8192/include/custom_emi.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_common.h
A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h
A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h
A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h
A src/vendorcode/mediatek/mt8192/include/dramc_register.h
A src/vendorcode/mediatek/mt8192/include/dramc_top.h
A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h
A src/vendorcode/mediatek/mt8192/include/emi.h
A src/vendorcode/mediatek/mt8192/include/emi_hw.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h
A src/vendorcode/mediatek/mt8192/include/memory.h
A src/vendorcode/mediatek/mt8192/include/print.h
A src/vendorcode/mediatek/mt8192/include/reg.h
A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
A src/vendorcode/mediatek/mt8192/include/x_hal_io.h
53 files changed, 85,570 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/19
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
......................................................................
WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
The i2c actiming with the default reg setting cannot meet spec,
so we need to set some regs.
1. adjust the ratio of SCL high and low level, to adjust tLOW.
2. modify ext_conf reg to adjust tSU,STO.
BUG=b:179000159
TEST=Test on asurada (MT8192), boot pass,
timing pass.
Signed-off-by: jg_daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com>
Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8
---
M src/soc/mediatek/mt8192/i2c.c
1 file changed, 28 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51024/7
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Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 )
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(1 comment)
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/02e30839_c586a315
PS16, Line 3: config DEBUG_DRAM
: bool "Output verbose DRAM related debug messages"
: default y
: help
: This option enables additional DRAM related debug messages.
> Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good. […]
@hung-te: CB:51125 ps11 has changed dramc_dbg to mediatek common header file.
Besides of mt8192, mt8173 and mt8183 both use the common dramc_dbg macro now.
Also, MEMORY_TEST config is moved to soc/mediatek/common/Kconfig, which is shared by all MTK SOCs.
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Hello Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
......................................................................
WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
The i2c actiming with the default reg setting cannot meet spec,
so we need to set some regs.
1. adjust the ratio of SCL high and low level, to adjust tLOW.
2. modify ext_conf reg to adjust tSU,STO.
BUG=b:179000159
TEST=Test on asurada (MT8192), boot pass,
timing pass.
Signed-off-by: Daolong Zhu <jg_daolongzhu(a)mediatek.corp-partner.google.com>
Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8
---
M src/soc/mediatek/mt8192/i2c.c
1 file changed, 28 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51024/6
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51076 )
Change subject: soc/amd/cezanne: Disable legacy DMA IO ports
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51076/comment/fb30cbf7_af9bdde6
PS2, Line 10: ports.
> had a look and didn't find any mainboard that is compatible with the renoir/cezanne apus and still h […]
Thank you for the analysis. Would have been great to have that in the commit message.
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
......................................................................
src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
Mediatek maintains the DRAM initialization code, the coding style
is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192
will not be used.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
---
A src/soc/mediatek/common/Kconfig
R src/soc/mediatek/common/dpm.c
A src/soc/mediatek/common/dram_init.c
R src/soc/mediatek/common/dramc_param.c
R src/soc/mediatek/common/include/soc/dpm.h
A src/soc/mediatek/common/include/soc/dramc_common.h
R src/soc/mediatek/common/include/soc/dramc_param.h
A src/soc/mediatek/common/include/soc/emi.h
R src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8173/Kconfig
M src/soc/mediatek/mt8173/dramc_pi_basic_api.c
M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/Kconfig
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
D src/soc/mediatek/mt8192/dramc_ana_init_config.c
D src/soc/mediatek/mt8192/dramc_dig_config.c
D src/soc/mediatek/mt8192/dramc_dvfs.c
D src/soc/mediatek/mt8192/dramc_pi_basic_api.c
D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
D src/soc/mediatek/mt8192/dramc_pi_main.c
D src/soc/mediatek/mt8192/dramc_power.c
D src/soc/mediatek/mt8192/dramc_subsys_config.c
D src/soc/mediatek/mt8192/dramc_tracking.c
D src/soc/mediatek/mt8192/dramc_utility.c
D src/soc/mediatek/mt8192/emi.c
D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
D src/soc/mediatek/mt8192/include/soc/dramc_power.h
D src/soc/mediatek/mt8192/include/soc/dramc_register.h
D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
A src/soc/mediatek/mt8192/include/soc/dramc_soc.h
D src/soc/mediatek/mt8192/include/soc/emi.h
M src/vendorcode/Makefile.inc
37 files changed, 293 insertions(+), 19,682 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/11
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Change subject: security/intel/txt: Fix logging
......................................................................
Patch Set 1:
(1 comment)
File src/security/intel/txt/logging.c:
https://review.coreboot.org/c/coreboot/+/51100/comment/80edb370_3b9b113d
PS1, Line 96: intel_txt_log_acm_error
TXT_BIOSACM_ERRORCODE and TXT_ERROR register have different encoding, thus using the same functions to decode seem wrong.
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51176 )
Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51176/comment/fd1e4cad_8e79dd1d
PS1, Line 9: wrong
> It was assigned randomly and was therefore wrong. It was not wrongly assigned but on purpose. […]
Ack
Patchset:
PS2:
I have changed the wording so it should be OK now.
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50294/comment/f96c5813_42bd1c04
PS5, Line 10: convinient
> convenient
Ack
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/4b61a4eb_66e619d7
PS16, Line 3: config DEBUG_DRAM
: bool "Output verbose DRAM related debug messages"
: default y
: help
: This option enables additional DRAM related debug messages.
> Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good. […]
I think we don't hae a standard err/info at the moment.
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