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Change in coreboot[master]: mb/intel/d510mo/devicetree.cb: Indent with tabs
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51149 ) Change subject: mb/intel/d510mo/devicetree.cb: Indent with tabs ...................................................................... mb/intel/d510mo/devicetree.cb: Indent with tabs This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/d510mo/devicetree.cb 1 file changed, 94 insertions(+), 94 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 7486f7e..22e67e7 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -1,100 +1,100 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/pineview # Northbridge - register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG - device pci 2.0 on end # Integrated graphics controller - device pci 2.1 on end # Integrated graphics controller 2 - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x20000040" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x20000040" - device pci 1b.0 on end # Audio - device pci 1c.0 on # PCIe 1 - device pci 0.0 on end # NIC - end - device pci 1c.1 on end # PCIe 2 - device pci 1c.2 on end # PCIe 3 - device pci 1c.3 on end # PCIe 4 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.3 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio (not on nm10?) - #device pci 1e.3 off end # AC'97 Modem (not on nm10?) - device pci 1f.0 on # ISA bridge - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 off end # Floppy - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 0 - end - device pnp 4e.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - irq 0xf0 = 0x80 - end - device pnp 4e.6 off end - device pnp 4e.7 off end - device pnp 4e.8 off end - device pnp 4e.9 off end - device pnp 4e.a off end # ACPI - device pnp 4e.b on # HWM - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 1f.1 off end # PATA - device pci 1f.2 on end # SATA - device pci 1f.3 on # SMbus - chip drivers/i2c/ck505 # ICS9EPRS525 - register "mask" = "{ 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff }" - register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff, - 0xff, 0x00, 0x00, 0x01, - 0x03, 0x25, 0x83, 0x17, - 0x0d }" - device i2c 69 on end - end - end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end - end - end + device pci 1b.0 on end # Audio + device pci 1c.0 on # PCIe 1 + device pci 0.0 on end # NIC + end + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio (not on nm10?) + #device pci 1e.3 off end # AC'97 Modem (not on nm10?) + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + irq 0xf0 = 0x80 + end + device pnp 4e.6 off end + device pnp 4e.7 off end + device pnp 4e.8 off end + device pnp 4e.9 off end + device pnp 4e.a off end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1f.1 off end # PATA + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 # ICS9EPRS525 + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff }" + register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x01, + 0x03, 0x25, 0x83, 0x17, + 0x0d }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/51149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Gerrit-Change-Number: 51149 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40465 ) Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... mb/gigabyte: Add GA-D510UD Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/gigabyte/ga-d510ud/Kconfig A src/mainboard/gigabyte/ga-d510ud/Kconfig.name A src/mainboard/gigabyte/ga-d510ud/Makefile.inc A src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl A src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl A src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl A src/mainboard/gigabyte/ga-d510ud/board_info.txt A src/mainboard/gigabyte/ga-d510ud/cmos.default A src/mainboard/gigabyte/ga-d510ud/cmos.layout A src/mainboard/gigabyte/ga-d510ud/cstates.c A src/mainboard/gigabyte/ga-d510ud/data.vbt A src/mainboard/gigabyte/ga-d510ud/devicetree.cb A src/mainboard/gigabyte/ga-d510ud/dsdt.asl A src/mainboard/gigabyte/ga-d510ud/early_init.c A src/mainboard/gigabyte/ga-d510ud/gpio.c A src/mainboard/gigabyte/ga-d510ud/hda_verb.c 16 files changed, 469 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig b/src/mainboard/gigabyte/ga-d510ud/Kconfig new file mode 100644 index 0000000..71fe981 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_GIGABYTE_GA_D510UD + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_512 + select CPU_INTEL_SOCKET_FCBGA559 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select NORTHBRIDGE_INTEL_PINEVIEW + select REALTEK_8168_RESET + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8720F + +config MAINBOARD_DIR + string + default "gigabyte/ga-d510ud" + +config MAINBOARD_PART_NUMBER + string + default "GA-D510UD" + +endif # BOARD_GIGABYTE_GA_D510UD diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig.name b/src/mainboard/gigabyte/ga-d510ud/Kconfig.name new file mode 100644 index 0000000..68c6dc4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_D510UD + bool "GA-D510UD" diff --git a/src/mainboard/gigabyte/ga-d510ud/Makefile.inc b/src/mainboard/gigabyte/ga-d510ud/Makefile.inc new file mode 100644 index 0000000..e78c424e --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-y += cstates.c diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..d6e6bef --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is the IRQ routing for the 0:1e.0 PCI bridge of the NM10 */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 0x15}, + Package() { 0x0000ffff, 1, 0, 0x16}, + Package() { 0x0000ffff, 2, 0, 0x17}, + Package() { 0x0000ffff, 3, 0, 0x14}, + Package() { 0x0001ffff, 0, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl b/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl new file mode 100644 index 0000000..c67e5d8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_SP1 +#define IT8720F_SHOW_SP2 +#define IT8720F_SHOW_EC +#define IT8720F_SHOW_KBCK +#define IT8720F_SHOW_KBCM +#include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/gigabyte/ga-d510ud/board_info.txt b/src/mainboard/gigabyte/ga-d510ud/board_info.txt new file mode 100644 index 0000000..ad5afe1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +Board URL: https://www.gigabyte.com/Motherboard/GA-D510UD-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-d510ud/cmos.default b/src/mainboard/gigabyte/ga-d510ud/cmos.default new file mode 100644 index 0000000..41098be --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=8M diff --git a/src/mainboard/gigabyte/ga-d510ud/cmos.layout b/src/mainboard/gigabyte/ga-d510ud/cmos.layout new file mode 100644 index 0000000..1e08c1f --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/cmos.layout @@ -0,0 +1,67 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +416 512 s 0 boot_devices + +# coreboot config options: cpu + +# coreboot config options: northbridge +952 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ga-d510ud/cstates.c b/src/mainboard/gigabyte/ga-d510ud/cstates.c new file mode 100644 index 0000000..21b18b9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/gigabyte/ga-d510ud/data.vbt b/src/mainboard/gigabyte/ga-d510ud/data.vbt new file mode 100644 index 0000000..ae75a25 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/data.vbt Binary files differ diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb new file mode 100644 index 0000000..9fb5ff5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/pineview + register "use_crt" = "1" + + device cpu_cluster 0 on + chip cpu/intel/socket_FCBGA559 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x105b 0x0d55 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # iGPU + device pci 2.1 off end # iGPU 2 + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x441" + + register "gen1_dec" = "0x00040291" # Environment Controller + + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # PCIe 1: Realtek GbE NIC + device pci 1c.1 on end # PCIe 2: JMB363 SATA/IDE + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on end # UHCI + device pci 1d.1 on end # UHCI + device pci 1d.2 on end # UHCI + device pci 1d.3 on end # UHCI + device pci 1d.7 on end # EHCI + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8720f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # PP + io 0x60 = 0x378 + io 0x62 = 0 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + end + end +end diff --git a/src/mainboard/gigabyte/ga-d510ud/dsdt.asl b/src/mainboard/gigabyte/ga-d510ud/dsdt.asl new file mode 100644 index 0000000..0e2fa7b --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 +) +{ + #include <acpi/dsdt_top.asl> + + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/pineview/acpi/pineview.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-d510ud/early_init.c b/src/mainboard/gigabyte/ga-d510ud/early_init.c new file mode 100644 index 0000000..8fdf25d --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/early_init.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/pineview/pineview.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8720f/it8720f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8720F_EC) + +void bootblock_mainboard_early_init(void) +{ + /* Set default GPIOs on superio */ + pnp_enter_conf_state(GPIO_DEV); + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x25, 0x00); + pnp_write_config(GPIO_DEV, 0x26, 0x0c); + pnp_write_config(GPIO_DEV, 0x28, 0x41); + pnp_write_config(GPIO_DEV, 0x2c, 0x01); + pnp_write_config(GPIO_DEV, 0x62, 0x08); + pnp_write_config(GPIO_DEV, 0x72, 0x00); + pnp_write_config(GPIO_DEV, 0xb8, 0x00); + pnp_write_config(GPIO_DEV, 0xc0, 0x00); + pnp_write_config(GPIO_DEV, 0xc1, 0x0c); + pnp_write_config(GPIO_DEV, 0xc3, 0x41); + pnp_write_config(GPIO_DEV, 0xc8, 0x00); + pnp_write_config(GPIO_DEV, 0xcb, 0x00); + pnp_write_config(GPIO_DEV, 0xe9, 0x01); + pnp_write_config(GPIO_DEV, 0xfc, 0xa4); + + pnp_exit_conf_state(GPIO_DEV); + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + printk(BIOS_DEBUG, "ITE register 0xef: 0x%02x ", pnp_read_config(GPIO_DEV, 0xef)); + + /* Disable SIO reboot */ + pnp_write_config(GPIO_DEV, 0xef, 0x7e); + + printk(BIOS_DEBUG, "=> 0x%02x\n", pnp_read_config(GPIO_DEV, 0xef)); + + pnp_set_logical_device(EC_DEV); + pnp_write_config(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */ + pnp_write_config(EC_DEV, 0x30, 0x01); /* Enable */ + + pnp_exit_conf_state(GPIO_DEV); +} + +void get_mb_spd_addrmap(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[1] = 0x51; +} diff --git a/src/mainboard/gigabyte/ga-d510ud/gpio.c b/src/mainboard/gigabyte/ga-d510ud/gpio.c new file mode 100644 index 0000000..5c756b9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/gpio.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c new file mode 100644 index 0000000..f36d48c --- /dev/null +++ b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0662, + 0x105b0d55, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, 0x01014c10), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c31), + AZALIA_PIN_CFG(0, 0x1a, 0x0181343f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x99430120), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/cbfs.c: Fix return value of failure to measure
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51099 ) Change subject: lib/cbfs.c: Fix return value of failure to measure ...................................................................... lib/cbfs.c: Fix return value of failure to measure Returning an error on a failure to measure makes the system not bootable. Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/lib/cbfs.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, but someone else must approve Christian Walter: Looks good to me, approved diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 60dc15a..4bc6962 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -69,8 +69,9 @@ if (rdev_chain(rdev, &cbd->rdev, data_offset, be32toh(mdata->h.len))) return CB_ERR; - if (tspi_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) - return CB_ERR; + if (tspi_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) { + printk(BIOS_ERR, "CBFS ERROR: error when measuring '%s'\n", name); + } return CB_SUCCESS; } @@ -144,7 +145,7 @@ ret = cbfs_locate(fh, &rdev, name, type); if (!ret) if (tspi_measure_cbfs_hook(&rdev, name, *type)) - return -1; + LOG("error measuring %s in region %s\n", name, region_name); return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/51099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce Gerrit-Change-Number: 51099 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Cindy Ching, Martin Roth, Shaoming Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51125 ) Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: also, the message macros (especially those related to 73/83) should be moved to a new patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 12 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:52:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Cindy Ching, Martin Roth, Shaoming Chen, Paul Menzel. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51125 ) Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: this patch has too many things in one patch. Please split into: 1. Change Kconfig 2. Move files to common (1, 2 can be merged if that makes sense) 3. switch to vendor code -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 12 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 20: (1 comment) Patchset: PS19: > Please rebase to master head and pin to the DRAM ToT so we can review there (and let buildbot verify […] rebase done. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 20 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:48:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
by Yu-Ping Wu (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Jg Daolongzhu, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51024 ) Change subject: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO ...................................................................... Patch Set 9: (9 comments) File src/soc/mediatek/mt8192/i2c.c: PS7: Please remove execute permission. https://review.coreboot.org/c/coreboot/+/51024/comment/ba5324a5_ed0227d3 PS7, Line 10: FULL_DUTY Can we use "I2C_" as prefix? https://review.coreboot.org/c/coreboot/+/51024/comment/f8795ab1_3a16f2ae PS7, Line 12: ADJUST Maybe "ADJUSTED" https://review.coreboot.org/c/coreboot/+/51024/comment/087e3635_cf0d9aac PS7, Line 137: uint32_t tar_speed_high = 400; : uint32_t tar_speed_low = 400; No need to initialize these. https://review.coreboot.org/c/coreboot/+/51024/comment/93681077_ebb9862d PS7, Line 142: adjust Adjust https://review.coreboot.org/c/coreboot/+/51024/comment/8031aa98_edd6e01c PS7, Line 150: i2c_freq Align with sample_div. https://review.coreboot.org/c/coreboot/+/51024/comment/412cf4ec_8bdefcc8 PS7, Line 157: adjust Adjust https://review.coreboot.org/c/coreboot/+/51024/comment/6f4eadea_880eff74 PS7, Line 165: i2c_freq Align with sample_div. https://review.coreboot.org/c/coreboot/+/51024/comment/51c86940_084afdfa PS7, Line 174: adjust Adjust -- To view, visit https://review.coreboot.org/c/coreboot/+/51024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Gerrit-Change-Number: 51024 Gerrit-PatchSet: 9 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:47:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 19: (1 comment) File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/8225a222_4fea4274 PS16, Line 3: config DEBUG_DRAM : bool "Output verbose DRAM related debug messages" : default y : help : This option enables additional DRAM related debug messages. > @hung-te: CB:51125 ps11 has changed dramc_dbg to mediatek common header file. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 19 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xi Chen <xixi.chen(a)mediatek.com> Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
by Jg Daolongzhu (Code Review) 03 Mar '21

03 Mar '21

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
by Jg Daolongzhu (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Jg Daolongzhu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51024 ) Change subject: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO ...................................................................... Patch Set 9: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51024/comment/abd783f0_fa230e4a PS5, Line 2: jg_daolongzhu > Please use *Jg Daolongzhu*. Done https://review.coreboot.org/c/coreboot/+/51024/comment/383a8273_269b4f0f PS5, Line 7: tLOW,tSU,STO > Please add a space after the comma. Done https://review.coreboot.org/c/coreboot/+/51024/comment/2af901b6_9a5e8334 PS5, Line 8: > Please describe the problem first. Done https://review.coreboot.org/c/coreboot/+/51024/comment/ed0b55da_371357bf PS5, Line 9: 1.adjust > Please add a space after the dot. Done https://review.coreboot.org/c/coreboot/+/51024/comment/49083518_237524c0 PS5, Line 10: to adjust tLOW. > This fits on one line. Done https://review.coreboot.org/c/coreboot/+/51024/comment/2a23a48f_198f04e5 PS5, Line 14: asurada(MT8192) > Please add a space before the (. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Gerrit-Change-Number: 51024 Gerrit-PatchSet: 9 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:45:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit March 2021