coreboot-gerrit March 2021

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate lock bit write
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47036 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate lock bit write ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate lock bit write This lock bit can be set later, and should also be set for Lynxpoint-H. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47036/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b47b8a..10e498a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -364,9 +364,6 @@ if (RCBA32(FD) & PCH_DISABLE_ADSPD) RCBA32_OR(0x2b1c, (1 << 29)); - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - /* Set RCBA 0x33D4 after other setup */ RCBA32_OR(0x33d4, 0x2fff2fb1); @@ -772,6 +769,9 @@ { spi_finalize_ops(); + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) apm_control(APM_CNT_FINALIZE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Gerrit-Change-Number: 47036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA boards: Captilize ASL names
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51152 ) Change subject: AGESA boards: Captilize ASL names ...................................................................... AGESA boards: Captilize ASL names ASL+ Optimizing Compiler/Disassembler version 20200925 remarks: IASL build/dsdt.aml Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20200925 Copyright (c) 2000 - 2020 Intel Corporation dsdt.asl 222: Name(PSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_) dsdt.asl 228: Name(APSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA) Execute the command below to fix all occurences: git grep -l PSa | xargs sed -i 's/PSa/PSA/g' Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/inagua/acpi/routing.asl M src/mainboard/amd/south_station/acpi/routing.asl M src/mainboard/amd/union_station/acpi/routing.asl M src/mainboard/asrock/e350m1/acpi/routing.asl M src/mainboard/gizmosphere/gizmo/acpi/routing.asl M src/mainboard/lippert/frontrunner-af/acpi/routing.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl 7 files changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 5fa77f0..50cb070 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 5fa77f0..50cb070 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index f8b62fa..2820cbb 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 0e610d7..5d1e261 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -339,8 +339,8 @@ Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PICM){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PICM){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Gerrit-Change-Number: 51152 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: configs/config.google_volteer.build_test_purposes: Add file
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51155 ) Change subject: configs/config.google_volteer.build_test_purposes: Add file ...................................................................... configs/config.google_volteer.build_test_purposes: Add file This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> --- A configs/config.google_volteer.build_test_purposes 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Francois Toguo Fotso: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/configs/config.google_volteer.build_test_purposes b/configs/config.google_volteer.build_test_purposes new file mode 100644 index 0000000..8531b79 --- /dev/null +++ b/configs/config.google_volteer.build_test_purposes @@ -0,0 +1,32 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + Debug options +# + Crashlog +# + Flashconsole +CONFIG_VENDOR_GOOGLE=y +CONFIG_CONSOLE_POST=y +CONFIG_BOARD_GOOGLE_VOLTEER=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_INTEL_TME=y +CONFIG_SOC_INTEL_CRASHLOG=y +CONFIG_NO_GFX_INIT=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DISPLAY_UPD_DATA=y +CONFIG_CONSOLE_SPI_FLASH=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DISPLAY_MTRRS=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_VERIFY_HOBS=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/51155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Gerrit-Change-Number: 51155 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Re-use existing define in CrashLog implementation
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51096 ) Change subject: soc/intel/tigerlake: Re-use existing define in CrashLog implementation ...................................................................... soc/intel/tigerlake: Re-use existing define in CrashLog implementation TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/tigerlake/crashlog_lib.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/crashlog_lib.c b/src/soc/intel/tigerlake/crashlog_lib.c index c9b1e61..93baf04 100644 --- a/src/soc/intel/tigerlake/crashlog_lib.c +++ b/src/soc/intel/tigerlake/crashlog_lib.c @@ -220,9 +220,9 @@ printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr); if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { - pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR0, tmp_bar_addr); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr); } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { - pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR1, tmp_bar_addr); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr); } else { printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); -- To view, visit https://review.coreboot.org/c/coreboot/+/51096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Gerrit-Change-Number: 51096 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Retype `CnviBtAudioOffload` devicetree option
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51154 ) Change subject: soc/intel: Retype `CnviBtAudioOffload` devicetree option ...................................................................... soc/intel: Retype `CnviBtAudioOffload` devicetree option The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 6 files changed, 6 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 6a826c0..825005e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -289,7 +289,7 @@ register "tcc_offset" = "10" # TCC of 90 - register "CnviBtAudioOffload" = "FORCE_ENABLE" + register "CnviBtAudioOffload" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 13e77cf..fa9fce2 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -207,10 +207,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* * IOM Port Config diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 1d97b36..c3a7ac1 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -196,10 +196,7 @@ unsigned int sdcard_cd_gpio; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* Tcss */ uint8_t TcssXhciEn; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 64bc70b..b878fd6 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -184,11 +184,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - PLATFORM_POR, - FORCE_ENABLE, - FORCE_DISABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* * Override GPIO PM configuration: diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6e52efd..c25ccbf 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -199,10 +199,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* Tcss */ uint8_t TcssXhciEn; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index cccf804..76a2480 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -317,10 +317,7 @@ } debug_interface_flag; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* TCSS USB */ uint8_t TcssXhciEn; -- To view, visit https://review.coreboot.org/c/coreboot/+/51154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Gerrit-Change-Number: 51154 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_mini: Implement `die_notify`
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50013 ) Change subject: mb/purism/librem_mini: Implement `die_notify` ...................................................................... mb/purism/librem_mini: Implement `die_notify` Make the SATA LED blink when coreboot dies. GPIO functions aren't compiled in for postcar, so add a check to prevent linker failures. TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and also blinding LED). Re-install RAM (and re-seat RAM a few times), boot to OS, and observe SATA LED operating normally, as expected. Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/purism/librem_cnl/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/die.c 3 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved Benjamin Doron: Looks good to me, but someone else must approve diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc index 8e3b5a6..c8cfa22 100644 --- a/src/mainboard/purism/librem_cnl/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -7,3 +7,5 @@ ramstage-y += ramstage.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc new file mode 100644 index 0000000..20ff438 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += die.c +smm-y += die.c diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c new file mode 100644 index 0000000..8147abb --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/gpio.h> + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_E8, 1); + + while (1) { + gpio_set(GPP_E8, 0); + mdelay(100); + gpio_set(GPP_E8, 1); + mdelay(100); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Gerrit-Change-Number: 50013 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 20: Code-Review+1 (1 comment) Patchset: PS20: ok.... I think we're pretty close? -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 20 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 09:01:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/*: Don't select PCIEXP_HOTPLUG
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51151 ) Change subject: mb/*/*: Don't select PCIEXP_HOTPLUG ...................................................................... mb/*/*: Don't select PCIEXP_HOTPLUG PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/tglrvp/Kconfig 3 files changed, 9 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index ddfd704..79f50aa 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -30,7 +30,6 @@ select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 - select PCIEXP_HOTPLUG select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE select HAVE_SPD_IN_CBFS @@ -112,6 +111,9 @@ int default 8 +config PCIEXP_HOTPLUG + default y + # Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) # Revision 0.7.6 Section 7.2.5.1.5 config PCIEXP_HOTPLUG_BUSES diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 91a18d9..295b56f 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -16,7 +16,6 @@ select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 - select PCIEXP_HOTPLUG config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON @@ -85,6 +84,9 @@ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT endchoice +config PCIEXP_HOTPLUG + default y + config PCIEXP_HOTPLUG_BUSES int default 42 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 233706d..bbdaf79 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,7 +18,6 @@ select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI - select PCIEXP_HOTPLUG select HAVE_SPD_IN_CBFS select SOC_INTEL_CSE_LITE_SKU select MAINBOARD_HAS_TPM2 @@ -61,6 +60,9 @@ int default 8 +config PCIEXP_HOTPLUG + default y + config PCIEXP_HOTPLUG_BUSES int default 42 -- To view, visit https://review.coreboot.org/c/coreboot/+/51151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Gerrit-Change-Number: 51151 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Backport SMRR locking support
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50936 ) Change subject: soc/intel: Backport SMRR locking support ...................................................................... soc/intel: Backport SMRR locking support Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/elkhartlake/smmrelocate.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 5 files changed, 85 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 0cc42e2..4df90fd 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> @@ -137,8 +138,24 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } diff --git a/src/soc/intel/elkhartlake/smmrelocate.c b/src/soc/intel/elkhartlake/smmrelocate.c index 0cc42e2..4df90fd 100644 --- a/src/soc/intel/elkhartlake/smmrelocate.c +++ b/src/soc/intel/elkhartlake/smmrelocate.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> @@ -137,8 +138,24 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 0cc42e2..4df90fd 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> @@ -137,8 +138,24 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 0cc42e2..4df90fd 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> @@ -137,8 +138,24 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 0cc42e2..4df90fd 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mp.h> @@ -137,8 +138,24 @@ /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Gerrit-Change-Number: 50936 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51150 ) Change subject: mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device ...................................................................... mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device Pineview does not support PEG. Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 4c5c2fa..766d68f 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -13,7 +13,6 @@ device domain 0 on # PCI domain subsystemid 0x105b 0x0d55 inherit device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG device pci 2.0 on end # Integrated graphics controller device pci 2.1 off end # Integrated graphics controller 2 diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 22e67e7..4b5449f 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -12,7 +12,6 @@ end device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG device pci 2.0 on end # Integrated graphics controller device pci 2.1 on end # Integrated graphics controller 2 chip southbridge/intel/i82801gx # Southbridge -- To view, visit https://review.coreboot.org/c/coreboot/+/51150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Gerrit-Change-Number: 51150 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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