coreboot-gerrit March 2021

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Change in coreboot[master]: soc/intel/alderlake: Log internal device wake events
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47399 ) Change subject: soc/intel/alderlake: Log internal device wake events ...................................................................... soc/intel/alderlake: Log internal device wake events Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/elog.c 3 files changed, 77 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..68c33c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,8 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..f1d7b65 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 88760b9..c3509df 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> @@ -56,6 +57,77 @@ } } +static void pch_log_add_elog_event(const struct pme_map *ipme_map) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((ipme_map->devfn == PCH_DEVFN_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(ipme_map->wake_source, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + bool dev_found = false; + + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + { SA_DEVFN_TCSS_DMA0, ELOG_WAKE_SOURCE_PME_TCSS_DMA0 }, + { SA_DEVFN_TCSS_DMA1, ELOG_WAKE_SOURCE_PME_TCSS_DMA1 }, + }; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + pch_log_add_elog_event(&ipme_map[i]); + dev_found = true; + } + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + /* Check Thunderbolt ports */ + if (!dev_found) { + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + } + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -74,9 +146,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Gerrit-Change-Number: 47399 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add some helper macros for accessing TCSS DMA de...
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47413 ) Change subject: soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices ...................................................................... soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/pci_devs.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47413/1 diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index d86e81d..fd9823e 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -50,6 +50,8 @@ #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, (x + 2)) #define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) #define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) #define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/47413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Gerrit-Change-Number: 47413 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add PCIe root port wake sources to elog
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47398 ) Change subject: soc/intel/alderlake: Add PCIe root port wake sources to elog ...................................................................... soc/intel/alderlake: Add PCIe root port wake sources to elog Log PCIe root port wake events in the elog. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 --- M src/soc/intel/alderlake/elog.c 1 file changed, 39 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47398/1 diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84f0a7e..88760b9 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -2,11 +2,18 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> +#include <types.h> + +struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; +}; static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +27,35 @@ } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +66,9 @@ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 Gerrit-Change-Number: 47398 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate lock bit write
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47036 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate lock bit write ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate lock bit write This lock bit can be set later, and should also be set for Lynxpoint-H. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47036/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b47b8a..10e498a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -364,9 +364,6 @@ if (RCBA32(FD) & PCH_DISABLE_ADSPD) RCBA32_OR(0x2b1c, (1 << 29)); - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - /* Set RCBA 0x33D4 after other setup */ RCBA32_OR(0x33d4, 0x2fff2fb1); @@ -772,6 +769,9 @@ { spi_finalize_ops(); + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) apm_control(APM_CNT_FINALIZE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Gerrit-Change-Number: 47036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: AGESA boards: Captilize ASL names
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51152 ) Change subject: AGESA boards: Captilize ASL names ...................................................................... AGESA boards: Captilize ASL names ASL+ Optimizing Compiler/Disassembler version 20200925 remarks: IASL build/dsdt.aml Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20200925 Copyright (c) 2000 - 2020 Intel Corporation dsdt.asl 222: Name(PSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_) dsdt.asl 228: Name(APSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA) Execute the command below to fix all occurences: git grep -l PSa | xargs sed -i 's/PSa/PSA/g' Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/inagua/acpi/routing.asl M src/mainboard/amd/south_station/acpi/routing.asl M src/mainboard/amd/union_station/acpi/routing.asl M src/mainboard/asrock/e350m1/acpi/routing.asl M src/mainboard/gizmosphere/gizmo/acpi/routing.asl M src/mainboard/lippert/frontrunner-af/acpi/routing.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl 7 files changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index 2b5823f..8f8ea45 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 5fa77f0..50cb070 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 5fa77f0..50cb070 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index f8b62fa..2820cbb 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -289,14 +289,14 @@ Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PSa, Package(){ + Name(PSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Package(){0x0000FFFF, 3, INTC, 0 }, }) - Name(APSa, Package(){ + Name(APSA, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, Package(){0x0000FFFF, 1, 0, 19 }, diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 0e610d7..5d1e261 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -339,8 +339,8 @@ Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PICM){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PICM){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Gerrit-Change-Number: 51152 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: configs/config.google_volteer.build_test_purposes: Add file
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51155 ) Change subject: configs/config.google_volteer.build_test_purposes: Add file ...................................................................... configs/config.google_volteer.build_test_purposes: Add file This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> --- A configs/config.google_volteer.build_test_purposes 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Francois Toguo Fotso: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/configs/config.google_volteer.build_test_purposes b/configs/config.google_volteer.build_test_purposes new file mode 100644 index 0000000..8531b79 --- /dev/null +++ b/configs/config.google_volteer.build_test_purposes @@ -0,0 +1,32 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + Debug options +# + Crashlog +# + Flashconsole +CONFIG_VENDOR_GOOGLE=y +CONFIG_CONSOLE_POST=y +CONFIG_BOARD_GOOGLE_VOLTEER=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_INTEL_TME=y +CONFIG_SOC_INTEL_CRASHLOG=y +CONFIG_NO_GFX_INIT=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DISPLAY_UPD_DATA=y +CONFIG_CONSOLE_SPI_FLASH=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DISPLAY_MTRRS=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_VERIFY_HOBS=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/51155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Gerrit-Change-Number: 51155 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Re-use existing define in CrashLog implementation
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51096 ) Change subject: soc/intel/tigerlake: Re-use existing define in CrashLog implementation ...................................................................... soc/intel/tigerlake: Re-use existing define in CrashLog implementation TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/tigerlake/crashlog_lib.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/crashlog_lib.c b/src/soc/intel/tigerlake/crashlog_lib.c index c9b1e61..93baf04 100644 --- a/src/soc/intel/tigerlake/crashlog_lib.c +++ b/src/soc/intel/tigerlake/crashlog_lib.c @@ -220,9 +220,9 @@ printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr); if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { - pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR0, tmp_bar_addr); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr); } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { - pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR1, tmp_bar_addr); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr); } else { printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); -- To view, visit https://review.coreboot.org/c/coreboot/+/51096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Gerrit-Change-Number: 51096 Gerrit-PatchSet: 5 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Retype `CnviBtAudioOffload` devicetree option
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51154 ) Change subject: soc/intel: Retype `CnviBtAudioOffload` devicetree option ...................................................................... soc/intel: Retype `CnviBtAudioOffload` devicetree option The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 6 files changed, 6 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 6a826c0..825005e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -289,7 +289,7 @@ register "tcc_offset" = "10" # TCC of 90 - register "CnviBtAudioOffload" = "FORCE_ENABLE" + register "CnviBtAudioOffload" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 13e77cf..fa9fce2 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -207,10 +207,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* * IOM Port Config diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 1d97b36..c3a7ac1 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -196,10 +196,7 @@ unsigned int sdcard_cd_gpio; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* Tcss */ uint8_t TcssXhciEn; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 64bc70b..b878fd6 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -184,11 +184,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - PLATFORM_POR, - FORCE_ENABLE, - FORCE_DISABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* * Override GPIO PM configuration: diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6e52efd..c25ccbf 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -199,10 +199,7 @@ uint8_t pch_isclk; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* Tcss */ uint8_t TcssXhciEn; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index cccf804..76a2480 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -317,10 +317,7 @@ } debug_interface_flag; /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ - enum { - FORCE_DISABLE, - FORCE_ENABLE, - } CnviBtAudioOffload; + bool CnviBtAudioOffload; /* TCSS USB */ uint8_t TcssXhciEn; -- To view, visit https://review.coreboot.org/c/coreboot/+/51154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Gerrit-Change-Number: 51154 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_mini: Implement `die_notify`
by Patrick Georgi (Code Review) 03 Mar '21

03 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50013 ) Change subject: mb/purism/librem_mini: Implement `die_notify` ...................................................................... mb/purism/librem_mini: Implement `die_notify` Make the SATA LED blink when coreboot dies. GPIO functions aren't compiled in for postcar, so add a check to prevent linker failures. TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and also blinding LED). Re-install RAM (and re-seat RAM a few times), boot to OS, and observe SATA LED operating normally, as expected. Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/purism/librem_cnl/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/die.c 3 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved Benjamin Doron: Looks good to me, but someone else must approve diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc index 8e3b5a6..c8cfa22 100644 --- a/src/mainboard/purism/librem_cnl/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -7,3 +7,5 @@ ramstage-y += ramstage.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc new file mode 100644 index 0000000..20ff438 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += die.c +smm-y += die.c diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c new file mode 100644 index 0000000..8147abb --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/die.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include <soc/gpio.h> + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_E8, 1); + + while (1) { + gpio_set(GPP_E8, 0); + mdelay(100); + gpio_set(GPP_E8, 1); + mdelay(100); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Gerrit-Change-Number: 50013 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 20: Code-Review+1 (1 comment) Patchset: PS20: ok.... I think we're pretty close? -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 20 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 09:01:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2021