coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO
by Jg Daolongzhu (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Jg Daolongzhu, Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51024 to look at the new patch set (#6). Change subject: WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO ...................................................................... WIP: soc/mediatek/mt8192: adjust i2c tLOW, tSU,STO The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust tLOW. 2. modify ext_conf reg to adjust tSU,STO. BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 --- M src/soc/mediatek/mt8192/i2c.c 1 file changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51024/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/51024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Gerrit-Change-Number: 51024 Gerrit-PatchSet: 6 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Disable legacy DMA IO ports
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51076 ) Change subject: soc/amd/cezanne: Disable legacy DMA IO ports ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51076/comment/fb30cbf7_af9bdde6 PS2, Line 10: ports. > had a look and didn't find any mainboard that is compatible with the renoir/cezanne apus and still h […] Thank you for the analysis. Would have been great to have that in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/51076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694 Gerrit-Change-Number: 51076 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:16:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Martin Roth, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51125 to look at the new patch set (#11). Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) Mediatek maintains the DRAM initialization code, the coding style is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192 will not be used. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf --- A src/soc/mediatek/common/Kconfig R src/soc/mediatek/common/dpm.c A src/soc/mediatek/common/dram_init.c R src/soc/mediatek/common/dramc_param.c R src/soc/mediatek/common/include/soc/dpm.h A src/soc/mediatek/common/include/soc/dramc_common.h R src/soc/mediatek/common/include/soc/dramc_param.h A src/soc/mediatek/common/include/soc/emi.h R src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/dramc_ana_init_config.c D src/soc/mediatek/mt8192/dramc_dig_config.c D src/soc/mediatek/mt8192/dramc_dvfs.c D src/soc/mediatek/mt8192/dramc_pi_basic_api.c D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c D src/soc/mediatek/mt8192/dramc_pi_main.c D src/soc/mediatek/mt8192/dramc_power.c D src/soc/mediatek/mt8192/dramc_subsys_config.c D src/soc/mediatek/mt8192/dramc_tracking.c D src/soc/mediatek/mt8192/dramc_utility.c D src/soc/mediatek/mt8192/emi.c D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h D src/soc/mediatek/mt8192/include/soc/dramc_power.h D src/soc/mediatek/mt8192/include/soc/dramc_register.h D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h A src/soc/mediatek/mt8192/include/soc/dramc_soc.h D src/soc/mediatek/mt8192/include/soc/emi.h M src/vendorcode/Makefile.inc 37 files changed, 293 insertions(+), 19,682 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 11 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Fix logging
by Patrick Rudolph (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Christian Walter, Arthur Heymans, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51100 ) Change subject: security/intel/txt: Fix logging ...................................................................... Patch Set 1: (1 comment) File src/security/intel/txt/logging.c: https://review.coreboot.org/c/coreboot/+/51100/comment/80edb370_3b9b113d PS1, Line 96: intel_txt_log_acm_error TXT_BIOSACM_ERRORCODE and TXT_ERROR register have different encoding, thus using the same functions to decode seem wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/51100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9c7140c7d51605e2708cbbc4a79d3ac37965656 Gerrit-Change-Number: 51100 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:13:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c/rx6110sa: Add official ACPI ID
by Werner Zeh (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Andy Shevchenko, Paul Menzel. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51176 ) Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51176/comment/fd1e4cad_8e79dd1d PS1, Line 9: wrong > It was assigned randomly and was therefore wrong. It was not wrongly assigned but on purpose. […] Ack Patchset: PS2: I have changed the wording so it should be OK now. -- To view, visit https://review.coreboot.org/c/coreboot/+/51176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45838162f014a760520692c6dcaae329ad98547d Gerrit-Change-Number: 51176 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 18: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50294/comment/f96c5813_42bd1c04 PS5, Line 10: convinient > convenient Ack File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/4b61a4eb_66e619d7 PS16, Line 3: config DEBUG_DRAM : bool "Output verbose DRAM related debug messages" : default y : help : This option enables additional DRAM related debug messages. > Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good. […] I think we don't hae a standard err/info at the moment. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 18 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:01:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xi Chen <xixi.chen(a)mediatek.com> Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Hung-Te Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 18: (7 comments) Patchset: PS18: Much better now, can you rebase this to the head so we can let buildbot verify and merge? File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/50294/comment/9ee7c9fb_e125faea PS15, Line 617: MT8192 > Currently, only mt8192. Ack https://review.coreboot.org/c/coreboot/+/50294/comment/077ba5fd_cf929726 PS15, Line 618: Xi Chen <xixi.chen(a)mediatek.com> > Currently, mainly on DRAM, in MT8192 section now. Ack File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/50294/comment/866469e6_d651f21e PS18, Line 620: k/ If the section is "MT8192" then you should have this as mediatek/mt8192/ https://review.coreboot.org/c/coreboot/+/50294/comment/aaed6c93_742c5e69 PS18, Line 621: mt8192 mt8192/ (you need the trailing slash /) File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/db0740c6_56791ca7 PS16, Line 1: SOC_MEDIATEK_MT8192 > move the file to soc/mediatek/common. Ack File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c: https://review.coreboot.org/c/coreboot/+/50294/comment/d1b141dc_de5fe197 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > use GPL-2.0. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 18 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 08:00:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xi Chen <xixi.chen(a)mediatek.com> Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low time
by Stanley Wu (Code Review) 03 Mar '21

03 Mar '21

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51198 ) Change subject: mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low time ...................................................................... mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low time Configure I2C bus 5 high and low time for p-sensor device. BUG=b:181727056 TEST=Measured the I2C bus frequency reduce to 387 KHz. Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/51198/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 6c0fdd6..d7ed0f2 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -51,6 +51,12 @@ }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/51198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c Gerrit-Change-Number: 51198 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Martin Roth, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51125 to look at the new patch set (#10). Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) Mediatek maintains the DRAM initialization code, the coding style is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192 will not be used. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf --- A src/soc/mediatek/common/Kconfig R src/soc/mediatek/common/dpm.c A src/soc/mediatek/common/dram_init.c R src/soc/mediatek/common/dramc_param.c R src/soc/mediatek/common/include/soc/dpm.h A src/soc/mediatek/common/include/soc/dramc_common.h R src/soc/mediatek/common/include/soc/dramc_param.h A src/soc/mediatek/common/include/soc/emi.h R src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/dramc_ana_init_config.c D src/soc/mediatek/mt8192/dramc_dig_config.c D src/soc/mediatek/mt8192/dramc_dvfs.c D src/soc/mediatek/mt8192/dramc_pi_basic_api.c D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c D src/soc/mediatek/mt8192/dramc_pi_main.c D src/soc/mediatek/mt8192/dramc_power.c D src/soc/mediatek/mt8192/dramc_subsys_config.c D src/soc/mediatek/mt8192/dramc_tracking.c D src/soc/mediatek/mt8192/dramc_utility.c D src/soc/mediatek/mt8192/emi.c D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h D src/soc/mediatek/mt8192/include/soc/dramc_power.h D src/soc/mediatek/mt8192/include/soc/dramc_register.h D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h A src/soc/mediatek/mt8192/include/soc/dramc_soc.h D src/soc/mediatek/mt8192/include/soc/emi.h M src/vendorcode/Makefile.inc 31 files changed, 215 insertions(+), 19,573 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 10 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization code
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Julius Werner, Angel Pons, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code ...................................................................... Patch Set 18: (13 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50294/comment/78400e5b_4be651fc PS16, Line 7: codes > code Done https://review.coreboot.org/c/coreboot/+/50294/comment/1e33d53a_6ac8c0a0 PS16, Line 12: an > a Done https://review.coreboot.org/c/coreboot/+/50294/comment/17ce104f_deee0fb8 PS16, Line 12: took > "taken" or "considered" Done https://review.coreboot.org/c/coreboot/+/50294/comment/f1d8fb21_9134963b PS16, Line 14: ( > One space before "(" Done File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/50294/comment/ca4b84e7_5277d3e1 PS15, Line 617: MT8192 > Will you work on DRAM for more platforms in future? […] Currently, only mt8192. https://review.coreboot.org/c/coreboot/+/50294/comment/9f951cc4_540d1a44 PS15, Line 618: Xi Chen <xixi.chen(a)mediatek.com> > If you'll work on non-dram topics as well, feel free to move your self to "MEDIATEK SOCS" Currently, mainly on DRAM, in MT8192 section now. https://review.coreboot.org/c/coreboot/+/50294/comment/a0fc3b44_d91b4a48 PS15, Line 620: / > if this is for 8192 then the path should be mediatek/mt8192/ Done https://review.coreboot.org/c/coreboot/+/50294/comment/b3ae454b_9eed87e2 PS15, Line 621: 2 > mt8192/ Done File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/659d7440_254aaadb PS16, Line 1: SOC_MEDIATEK_MT8192 > can we move this to mt8192/Kconfig? move the file to soc/mediatek/common. https://review.coreboot.org/c/coreboot/+/50294/comment/6b23dbe9_ae6237ed PS16, Line 3: config DEBUG_DRAM : bool "Output verbose DRAM related debug messages" : default y : help : This option enables additional DRAM related debug messages. > What Angel suggested sounds good. […] Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good. Add dramc_dbg in mediatek common file: soc/mediatek/common/.../dramc_common.h CB:51125 #define dramc_dbg(_x_...) do { \ if (CONFIG(DEBUG_DRAM)) \ printk(BIOS_INFO, _x_); \ } while (0) Another reason we use dramc_xxx macro is that we want a simple log level macro: eg: #define err(_x_...) printk(BIOS_ERR, _x_) #define info(_x_...) printk(BIOS_INFO, _x_) Do these macros exist in common log header file? https://review.coreboot.org/c/coreboot/+/50294/comment/d59c5780_0c93fca8 PS16, Line 9: config MEDIATEK_DRAM_DVFS : bool : default n : help : This option enables DRAM calibration with multiple frequencies (low, : medium and high frequency groups, with total 7 frequencies) for DVFS : feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, : 3200, 4266. : : config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT : bool : default y : select MEDIATEK_DRAM_DVFS : help : This options limit DRAM frequency calibration count from total 7 to 3, : other frequency will directly use the low frequency shu result. : : config MEMORY_TEST : bool : default y : help : This option enables memory basic compare test to verify the DRAM read : or write is as expected. > these options are not really used in the dramc implementation here. […] Move them to soc/mediatek/common. File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c: https://review.coreboot.org/c/coreboot/+/50294/comment/024ea23a_6336d079 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > I also prefer BSD3. @xixi please check with your internal teams and move to BSD3 if possible. use GPL-2.0. File src/vendorcode/mediatek/mt8192/include/print.h: https://review.coreboot.org/c/coreboot/+/50294/comment/64ed3d47_43934ba0 PS16, Line 7: #define printf print > What about just add […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 18 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 07:50:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021