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Change subject: security/intel/txt: Fix logging
......................................................................
Patch Set 1:
(1 comment)
File src/security/intel/txt/logging.c:
https://review.coreboot.org/c/coreboot/+/51100/comment/80edb370_3b9b113d
PS1, Line 96: intel_txt_log_acm_error
TXT_BIOSACM_ERRORCODE and TXT_ERROR register have different encoding, thus using the same functions to decode seem wrong.
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Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51176/comment/fd1e4cad_8e79dd1d
PS1, Line 9: wrong
> It was assigned randomly and was therefore wrong. It was not wrongly assigned but on purpose. […]
Ack
Patchset:
PS2:
I have changed the wording so it should be OK now.
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50294/comment/f96c5813_42bd1c04
PS5, Line 10: convinient
> convenient
Ack
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/4b61a4eb_66e619d7
PS16, Line 3: config DEBUG_DRAM
: bool "Output verbose DRAM related debug messages"
: default y
: help
: This option enables additional DRAM related debug messages.
> Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good. […]
I think we don't hae a standard err/info at the moment.
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(7 comments)
Patchset:
PS18:
Much better now, can you rebase this to the head so we can let buildbot verify and merge?
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/50294/comment/9ee7c9fb_e125faea
PS15, Line 617: MT8192
> Currently, only mt8192.
Ack
https://review.coreboot.org/c/coreboot/+/50294/comment/077ba5fd_cf929726
PS15, Line 618: Xi Chen <xixi.chen(a)mediatek.com>
> Currently, mainly on DRAM, in MT8192 section now.
Ack
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/50294/comment/866469e6_d651f21e
PS18, Line 620: k/
If the section is "MT8192" then you should have this as
mediatek/mt8192/
https://review.coreboot.org/c/coreboot/+/50294/comment/aaed6c93_742c5e69
PS18, Line 621: mt8192
mt8192/
(you need the trailing slash /)
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/db0740c6_56791ca7
PS16, Line 1: SOC_MEDIATEK_MT8192
> move the file to soc/mediatek/common.
Ack
File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c:
https://review.coreboot.org/c/coreboot/+/50294/comment/d1b141dc_de5fe197
PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> use GPL-2.0.
Ack
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51125
to look at the new patch set (#10).
Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
......................................................................
src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
Mediatek maintains the DRAM initialization code, the coding style
is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192
will not be used.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
---
A src/soc/mediatek/common/Kconfig
R src/soc/mediatek/common/dpm.c
A src/soc/mediatek/common/dram_init.c
R src/soc/mediatek/common/dramc_param.c
R src/soc/mediatek/common/include/soc/dpm.h
A src/soc/mediatek/common/include/soc/dramc_common.h
R src/soc/mediatek/common/include/soc/dramc_param.h
A src/soc/mediatek/common/include/soc/emi.h
R src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
D src/soc/mediatek/mt8192/dramc_ana_init_config.c
D src/soc/mediatek/mt8192/dramc_dig_config.c
D src/soc/mediatek/mt8192/dramc_dvfs.c
D src/soc/mediatek/mt8192/dramc_pi_basic_api.c
D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
D src/soc/mediatek/mt8192/dramc_pi_main.c
D src/soc/mediatek/mt8192/dramc_power.c
D src/soc/mediatek/mt8192/dramc_subsys_config.c
D src/soc/mediatek/mt8192/dramc_tracking.c
D src/soc/mediatek/mt8192/dramc_utility.c
D src/soc/mediatek/mt8192/emi.c
D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
D src/soc/mediatek/mt8192/include/soc/dramc_power.h
D src/soc/mediatek/mt8192/include/soc/dramc_register.h
D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
A src/soc/mediatek/mt8192/include/soc/dramc_soc.h
D src/soc/mediatek/mt8192/include/soc/emi.h
M src/vendorcode/Makefile.inc
31 files changed, 215 insertions(+), 19,573 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/10
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Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 )
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 18:
(13 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50294/comment/78400e5b_4be651fc
PS16, Line 7: codes
> code
Done
https://review.coreboot.org/c/coreboot/+/50294/comment/1e33d53a_6ac8c0a0
PS16, Line 12: an
> a
Done
https://review.coreboot.org/c/coreboot/+/50294/comment/17ce104f_deee0fb8
PS16, Line 12: took
> "taken" or "considered"
Done
https://review.coreboot.org/c/coreboot/+/50294/comment/f1d8fb21_9134963b
PS16, Line 14: (
> One space before "("
Done
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/50294/comment/ca4b84e7_5277d3e1
PS15, Line 617: MT8192
> Will you work on DRAM for more platforms in future? […]
Currently, only mt8192.
https://review.coreboot.org/c/coreboot/+/50294/comment/9f951cc4_540d1a44
PS15, Line 618: Xi Chen <xixi.chen(a)mediatek.com>
> If you'll work on non-dram topics as well, feel free to move your self to "MEDIATEK SOCS"
Currently, mainly on DRAM, in MT8192 section now.
https://review.coreboot.org/c/coreboot/+/50294/comment/a0fc3b44_d91b4a48
PS15, Line 620: /
> if this is for 8192 then the path should be mediatek/mt8192/
Done
https://review.coreboot.org/c/coreboot/+/50294/comment/b3ae454b_9eed87e2
PS15, Line 621: 2
> mt8192/
Done
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/659d7440_254aaadb
PS16, Line 1: SOC_MEDIATEK_MT8192
> can we move this to mt8192/Kconfig?
move the file to soc/mediatek/common.
https://review.coreboot.org/c/coreboot/+/50294/comment/6b23dbe9_ae6237ed
PS16, Line 3: config DEBUG_DRAM
: bool "Output verbose DRAM related debug messages"
: default y
: help
: This option enables additional DRAM related debug messages.
> What Angel suggested sounds good. […]
Thanks for all your advice. Reuse DEBUG_RAM_SETUP is very good.
Add dramc_dbg in mediatek common file: soc/mediatek/common/.../dramc_common.h CB:51125
#define dramc_dbg(_x_...) do { \
if (CONFIG(DEBUG_DRAM)) \
printk(BIOS_INFO, _x_); \
} while (0)
Another reason we use dramc_xxx macro is that we want a simple log level macro:
eg:
#define err(_x_...) printk(BIOS_ERR, _x_)
#define info(_x_...) printk(BIOS_INFO, _x_)
Do these macros exist in common log header file?
https://review.coreboot.org/c/coreboot/+/50294/comment/d59c5780_0c93fca8
PS16, Line 9: config MEDIATEK_DRAM_DVFS
: bool
: default n
: help
: This option enables DRAM calibration with multiple frequencies (low,
: medium and high frequency groups, with total 7 frequencies) for DVFS
: feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
: 3200, 4266.
:
: config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT
: bool
: default y
: select MEDIATEK_DRAM_DVFS
: help
: This options limit DRAM frequency calibration count from total 7 to 3,
: other frequency will directly use the low frequency shu result.
:
: config MEMORY_TEST
: bool
: default y
: help
: This option enables memory basic compare test to verify the DRAM read
: or write is as expected.
> these options are not really used in the dramc implementation here. […]
Move them to soc/mediatek/common.
File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c:
https://review.coreboot.org/c/coreboot/+/50294/comment/024ea23a_6336d079
PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> I also prefer BSD3. @xixi please check with your internal teams and move to BSD3 if possible.
use GPL-2.0.
File src/vendorcode/mediatek/mt8192/include/print.h:
https://review.coreboot.org/c/coreboot/+/50294/comment/64ed3d47_43934ba0
PS16, Line 7: #define printf print
> What about just add […]
Done
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Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
......................................................................
Patch Set 9:
(1 comment)
File src/soc/mediatek/common/include/soc/dramc_common.h:
https://review.coreboot.org/c/coreboot/+/51125/comment/a3dcbe76_8418b5f6
PS9, Line 14: } while(0)
space required before the open parenthesis '('
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50294
to look at the new patch set (#18).
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
vendor: mediatek: Add mediatek mt8192 dram initialization code
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
---
M MAINTAINERS
A src/vendorcode/mediatek/Makefile.inc
A src/vendorcode/mediatek/mt8192/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
A src/vendorcode/mediatek/mt8192/dramc/emi.c
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h
A src/vendorcode/mediatek/mt8192/include/addressmap.h
A src/vendorcode/mediatek/mt8192/include/custom_emi.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_common.h
A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h
A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h
A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h
A src/vendorcode/mediatek/mt8192/include/dramc_register.h
A src/vendorcode/mediatek/mt8192/include/dramc_top.h
A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h
A src/vendorcode/mediatek/mt8192/include/emi.h
A src/vendorcode/mediatek/mt8192/include/emi_hw.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h
A src/vendorcode/mediatek/mt8192/include/memory.h
A src/vendorcode/mediatek/mt8192/include/print.h
A src/vendorcode/mediatek/mt8192/include/reg.h
A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
A src/vendorcode/mediatek/mt8192/include/x_hal_io.h
53 files changed, 85,570 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/18
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
Gerrit-Change-Number: 50294
Gerrit-PatchSet: 18
Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-MessageType: newpatchset
Attention is currently required from: Hung-Te Lin, Martin Roth, Paul Menzel.
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51125
to look at the new patch set (#9).
Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
......................................................................
src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
Mediatek maintains the DRAM initialization code, the coding style
is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192
will not be used.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
---
A src/soc/mediatek/common/Kconfig
R src/soc/mediatek/common/dpm.c
A src/soc/mediatek/common/dram_init.c
R src/soc/mediatek/common/dramc_param.c
R src/soc/mediatek/common/include/soc/dpm.h
A src/soc/mediatek/common/include/soc/dramc_common.h
R src/soc/mediatek/common/include/soc/dramc_param.h
A src/soc/mediatek/common/include/soc/emi.h
R src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
D src/soc/mediatek/mt8192/dramc_ana_init_config.c
D src/soc/mediatek/mt8192/dramc_dig_config.c
D src/soc/mediatek/mt8192/dramc_dvfs.c
D src/soc/mediatek/mt8192/dramc_pi_basic_api.c
D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
D src/soc/mediatek/mt8192/dramc_pi_main.c
D src/soc/mediatek/mt8192/dramc_power.c
D src/soc/mediatek/mt8192/dramc_subsys_config.c
D src/soc/mediatek/mt8192/dramc_tracking.c
D src/soc/mediatek/mt8192/dramc_utility.c
D src/soc/mediatek/mt8192/emi.c
D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
D src/soc/mediatek/mt8192/include/soc/dramc_power.h
D src/soc/mediatek/mt8192/include/soc/dramc_register.h
D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
A src/soc/mediatek/mt8192/include/soc/dramc_soc.h
D src/soc/mediatek/mt8192/include/soc/emi.h
M src/vendorcode/Makefile.inc
31 files changed, 215 insertions(+), 19,573 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/9
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
Gerrit-Change-Number: 51125
Gerrit-PatchSet: 9
Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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