coreboot-gerrit March 2021

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: mt6315: update correct slave id
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, hsin-hsiung wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51056 ) Change subject: WIP: soc/mediatek/mt8192: mt6315: update correct slave id ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51056/comment/6a55d205_c97b1797 PS1, Line 8: What problem does this fix? https://review.coreboot.org/c/coreboot/+/51056/comment/5803eddb_d03524e1 PS1, Line 11: 2. update the correct sequence flow of the key protection. 1. Please start sentences with a capital letter. 2. If you enumerate changes, it’s a good indicator to make a separate commit for each change. -- To view, visit https://review.coreboot.org/c/coreboot/+/51056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 Gerrit-Change-Number: 51056 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicolas Boichat <drinkcat(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
by Kevin Chang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Paul Menzel. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51200 ) Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51200/comment/42867c15_353bc832 PS3, Line 9: because some MB is using wrong Samsung date code memory. > I do not understand this part. […] Hi Pual Update in patchset 4. -- To view, visit https://review.coreboot.org/c/coreboot/+/51200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Gerrit-Change-Number: 51200 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:27:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
by build bot (Jenkins) (Code Review) 03 Mar '21

03 Mar '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51200 ) Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/51200/comment/61454a93_e7e0f9e6 PS4, Line 10: void __weak memcfg_variant_init(FSPM_UPD *mupd); Using weak declarations can have unintended link defects -- To view, visit https://review.coreboot.org/c/coreboot/+/51200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Gerrit-Change-Number: 51200 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:26:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
by Kevin Chang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Kevin Chang. Hello build bot (Jenkins), Patrick Rudolph, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51200 to look at the new patch set (#4). Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB ...................................................................... mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB Disable SA GV in EVT MB, because factory used Samsung memory with wrong date code. So we need to use board version to judement MB phase to disable SA GV. Disable SA GV when board version equal. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/lindar/memory.c M src/soc/intel/tigerlake/include/soc/romstage.h 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/51200/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Gerrit-Change-Number: 51200 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mediatek/common: Add DRAM common files
by build bot (Jenkins) (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51203 ) Change subject: src/mediatek/common: Add DRAM common files ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/51203/comment/da19c5a1_26cc46d4 PS1, Line 28: } else { else is not generally useful after a break or return -- To view, visit https://review.coreboot.org/c/coreboot/+/51203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e Gerrit-Change-Number: 51203 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:16:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/mediatek/mt8173 & mt8183: use common dramc_xxx log macro
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin. Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51224 ) Change subject: src/soc/mediatek/mt8173 & mt8183: use common dramc_xxx log macro ...................................................................... src/soc/mediatek/mt8173 & mt8183: use common dramc_xxx log macro Use mediatek common dramc_xxx log macro instead of SOCs defined macro. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d --- M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 6 files changed, 77 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51224/1 diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 0c37998..7a2b1a5 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -25,17 +25,11 @@ config DEBUG_SOC_DRIVER bool "The top level switch for soc driver debug messages" default n - select DEBUG_DRAM + select DEBUG_RAM_SETUP select DEBUG_I2C select DEBUG_PMIC select DEBUG_PMIC_WRAP -config DEBUG_DRAM - bool "Output verbose DRAM related debug messages" - default n - help - This option enables additional DRAM related debug messages. - config DEBUG_I2C bool "Output verbose I2C related debug messages" default n diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 17a2207..8da4c7b 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -184,7 +184,7 @@ u16 one_count = (u16)((value >> 16) & 0xffff); u16 zero_count = (u16)(value & 0xffff); - dramc_dbg_msg("PLL %d, phase %d, one_count %d, zero_count %d\n", + dramc_dbg("PLL %d, phase %d, one_count %d, zero_count %d\n", (idx + 2), mempll->phase, one_count, zero_count); switch (mempll->phase) { @@ -232,8 +232,8 @@ {0, 0, 0}, }; - dramc_dbg_msg("[PLL_Phase_Calib] ===== PLL Phase Calibration: "); - dramc_dbg_msg("CHANNEL %d (0: CHA, 1: CHB) =====\n", channel); + dramc_dbg("[PLL_Phase_Calib] ===== PLL Phase Calibration: "); + dramc_dbg("CHANNEL %d (0: CHA, 1: CHB) =====\n", channel); /* 1. set jitter meter count number to 1024 for mempll 2 3 4 */ for (i = 0; i < 3; i++) @@ -283,11 +283,11 @@ } } - dramc_dbg_msg("pll done: "); + dramc_dbg("pll done: "); - dramc_dbg_msg("%d, %d, %d\n", + dramc_dbg("%d, %d, %d\n", mempll[0].done, mempll[1].done, mempll[2].done); - dramc_dbg_msg("pll dl: %d, %d, %d\n", + dramc_dbg("pll dl: %d, %d, %d\n", mempll[0].delay, mempll[1].delay, mempll[2].delay); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 3258270..1a182c5 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -19,8 +19,8 @@ const struct mt8173_calib_params *params = &sdram_params->calib_params; - dramc_dbg_msg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp); - dramc_dbg_msg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn); + dramc_dbg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp); + dramc_dbg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn); mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */ @@ -110,18 +110,18 @@ 0xf << PADCTL1_CLK_SHIFT, ca_max_center << PADCTL1_CLK_SHIFT); - dramc_dbg_msg("=========================================\n"); - dramc_dbg_msg(" [Channel %d] CA training\n", channel); - dramc_dbg_msg("=========================================\n"); + dramc_dbg("=========================================\n"); + dramc_dbg(" [Channel %d] CA training\n", channel); + dramc_dbg("=========================================\n"); for (i = 0; i < CATRAINING_NUM; i++) - dramc_dbg_msg("[CA] CA %d\tShift %d\n", i, ca_shift[i]); + dramc_dbg("[CA] CA %d\tShift %d\n", i, ca_shift[i]); - dramc_dbg_msg("[CA] Reg CMDDLY4 = %xh\n", + dramc_dbg("[CA] Reg CMDDLY4 = %xh\n", read32(&ch[channel].ddrphy_regs->cmddly[4])); - dramc_dbg_msg("[CA] Reg DQSCAL1 = %xh\n", + dramc_dbg("[CA] Reg DQSCAL1 = %xh\n", read32(&ch[channel].ao_regs->dqscal1)); - dramc_dbg_msg("[CA] Reg PADCTL1 = %xh\n", + dramc_dbg("[CA] Reg PADCTL1 = %xh\n", read32(&ch[channel].ddrphy_regs->padctl1)); } @@ -154,17 +154,17 @@ write32(&ch[channel].ddrphy_regs->dqodly[byte_i], value); } - dramc_dbg_msg("========================================\n"); - dramc_dbg_msg("[Channel %d] dramc_write_leveling_swcal\n", channel); - dramc_dbg_msg("========================================\n"); + dramc_dbg("========================================\n"); + dramc_dbg("[Channel %d] dramc_write_leveling_swcal\n", channel); + dramc_dbg("========================================\n"); - dramc_dbg_msg("[WL] DQS: %#x", + dramc_dbg("[WL] DQS: %#x", read32(&ch[channel].ddrphy_regs->padctl3)); - dramc_dbg_msg("[WL] DQM: %#x\n", + dramc_dbg("[WL] DQM: %#x\n", read32(&ch[channel].ddrphy_regs->padctl2)); for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++) - dramc_dbg_msg("[WL] DQ byte%d: %#x\n", byte_i, + dramc_dbg("[WL] DQ byte%d: %#x\n", byte_i, read32(&ch[channel].ddrphy_regs->dqodly[byte_i])); } @@ -358,11 +358,11 @@ gw_coarse_val = sdram_params->calib_params.gating_win[channel][rank][0]; gw_fine_val = sdram_params->calib_params.gating_win[channel][rank][1]; - dramc_dbg_msg("****************************************************\n"); - dramc_dbg_msg("Channel %d Rank %d DQS GW Calibration\n", channel, rank); - dramc_dbg_msg("Default (coarse, fine) tune value %d, %d.\n", + dramc_dbg("****************************************************\n"); + dramc_dbg("Channel %d Rank %d DQS GW Calibration\n", channel, rank); + dramc_dbg("Default (coarse, fine) tune value %d, %d.\n", gw_coarse_val, gw_fine_val); - dramc_dbg_msg("****************************************************\n"); + dramc_dbg("****************************************************\n"); /* set default coarse and fine value */ set_gw_coarse_factor(channel, gw_coarse_val); @@ -596,7 +596,7 @@ } } - dramc_dbg_msg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", + dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", bit, setup, hold, setup + hold, p->best_dqdly, p->best_dqsdly); @@ -618,8 +618,8 @@ max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty); - dramc_dbg_msg("[Channel %d CLK DUTY CALIB] ", channel); - dramc_dbg_msg("Final DUTY_SEL=%d, DUTY=%d, rx window size=%d\n", + dramc_dbg("[Channel %d CLK DUTY CALIB] ", channel); + dramc_dbg("Final DUTY_SEL=%d, DUTY=%d, rx window size=%d\n", max_duty_sel, max_duty, max_win_size); } @@ -673,18 +673,18 @@ clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* output dle setting of rank 0 and 1 */ - dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n" + dramc_dbg("[DLE] Rank 0 DLE calibrated setting = %xh.\n" "[DLE] Rank 1 DLE calibrated setting = %xh.\n", r0_dle_setting, r1_dle_setting); if (r1_dle_setting < r0_dle_setting) { /* compare dle setting of two ranks */ - dramc_dbg_msg("[DLE] rank 0 > rank 1. set to rank 0.\n"); + dramc_dbg("[DLE] rank 0 > rank 1. set to rank 0.\n"); /* case 1: set rank 0 dle setting */ set_dle_factor(channel, r0_dle_setting); } else { /* compare dle setting of two ranks */ - dramc_dbg_msg("[DLE] rank 0 < rank 1. use rank 1.\n"); + dramc_dbg("[DLE] rank 0 < rank 1. use rank 1.\n"); /* case 2: set rank 1 dle setting */ set_dle_factor(channel, r1_dle_setting); } @@ -696,10 +696,10 @@ u8 i, best_step; u32 err[DLE_TEST_NUM]; - dramc_dbg_msg("=========================================\n"); - dramc_dbg_msg("[Channel %d] [Rank %d] DATLAT calibration\n", + dramc_dbg("=========================================\n"); + dramc_dbg("[Channel %d] [Rank %d] DATLAT calibration\n", channel, rank); - dramc_dbg_msg("=========================================\n"); + dramc_dbg("=========================================\n"); clrbits32(&ch[channel].ao_regs->mckdly, 0x11 << MCKDLY_DQIENQKEND_SHIFT | @@ -736,7 +736,7 @@ */ set_dle_factor(channel, best_step); - dramc_dbg_msg("[DLE] adjusted value = %#x\n", best_step); + dramc_dbg("[DLE] adjusted value = %#x\n", best_step); return best_step; } @@ -754,7 +754,7 @@ index = i / DQS_BIT_NUMBER; if (i % DQS_BIT_NUMBER == 0) - dramc_dbg_msg("DQS%d: %d\n", index, + dramc_dbg("DQS%d: %d\n", index, wrlevel_dqs_dly[channel][index]); if (max_dqsdly_byte[index] <= wrlevel_dqs_dly[channel][index]) { @@ -872,9 +872,9 @@ write32(&ch[channel].ao_regs->r0deldly, value); write32(&ch[channel].ao_regs->r1deldly, value); - dramc_dbg_msg("[RX] DQS Reg R0DELDLY=%xh\n", + dramc_dbg("[RX] DQS Reg R0DELDLY=%xh\n", read32(&ch[channel].ao_regs->r0deldly)); - dramc_dbg_msg("[RX] DQS Reg R1DELDLY=%xh\n", + dramc_dbg("[RX] DQS Reg R1DELDLY=%xh\n", read32(&ch[channel].ao_regs->r1deldly)); for (i = 0; i < DATA_WIDTH_32BIT; i += 4) { @@ -885,7 +885,7 @@ (((u32)dqdqs_perbit_dly[i + 3].best_dqdly) << 24); write32(&ch[channel].ao_regs->dqidly[i / 4], value); - dramc_dbg_msg("[RX] DQ DQIDLY%d = %xh\n", (i + 4) / 4, value); + dramc_dbg("[RX] DQ DQIDLY%d = %xh\n", (i + 4) / 4, value); } } @@ -901,7 +901,7 @@ } write32(&ch[channel].ddrphy_regs->padctl3, value); - dramc_dbg_msg("[TX] DQS PADCTL3 Reg = %#x\n", value); + dramc_dbg("[TX] DQS PADCTL3 Reg = %#x\n", value); /* DQ delay */ for (bit = 0; bit < DATA_WIDTH_32BIT; bit++) { @@ -916,7 +916,7 @@ /* each register is with 8 DQ */ if ((bit + 1) % DQS_BIT_NUMBER == 0) { write32(&ch[channel].ddrphy_regs->dqodly[dqs_index], value); - dramc_dbg_msg("[TX] DQ DQ0DLY%d = %xh\n", + dramc_dbg("[TX] DQ DQ0DLY%d = %xh\n", dqs_index + 1, value); } } @@ -929,7 +929,7 @@ value += (((u32)ave_dqdly_byte[bit]) << (4 * bit)); } write32(&ch[channel].ddrphy_regs->padctl2, value); - dramc_dbg_msg("[TX] DQM PADCTL2 Reg = %#x\n", value); + dramc_dbg("[TX] DQM PADCTL2 Reg = %#x\n", value); } void perbit_window_cal(u32 channel, u8 type) @@ -940,7 +940,7 @@ struct dqs_perbit_dly dqdqs_perbit_dly[DQ_DATA_WIDTH]; - dramc_dbg_msg("\n[Channel %d] %s DQ/DQS per bit :\n", + dramc_dbg("\n[Channel %d] %s DQ/DQS per bit :\n", channel, (type == TX_WIN)? "TX": "RX"); if (type == TX_WIN) @@ -967,13 +967,13 @@ /* 1. set DQS delay to 0 first */ set_dly_factor(channel, STAGE_HOLD, type, FIRST_DQS_DELAY); - dramc_dbg_msg("----------------------------------" + dramc_dbg("----------------------------------" "--------------------\n"); - dramc_dbg_msg("Start DQ delay to find pass range," + dramc_dbg("Start DQ delay to find pass range," "DQS delay fixed to %#x...\n", FIRST_DQS_DELAY); - dramc_dbg_msg("----------------------------------" + dramc_dbg("----------------------------------" "-------------------\n"); - dramc_dbg_msg("x-axis is bit #; y-axis is DQ delay (%d~%d)\n", + dramc_dbg("x-axis is bit #; y-axis is DQ delay (%d~%d)\n", FIRST_DQ_DELAY, MAX_DQDLY_TAPS - 1); /* delay DQ from 0 to 15 to get the setup time */ @@ -988,12 +988,12 @@ dramk_check_dq_win(&(dqdqs_perbit_dly[bit]), dly, MAX_DQDLY_TAPS - 1, fail_bit); if (fail_bit == 0) { - dramc_dbg_msg("o"); + dramc_dbg("o"); } else { - dramc_dbg_msg("x"); + dramc_dbg("x"); } } - dramc_dbg_msg("\n"); + dramc_dbg("\n"); } /* 2. set DQ delay to 0 */ @@ -1002,13 +1002,13 @@ /* DQS delay taps: tx and rx are 16 and 64 taps */ max_dqs_taps = (type == TX_WIN)? MAX_TX_DQSDLY_TAPS: MAX_RX_DQSDLY_TAPS; - dramc_dbg_msg("-----------------------------------" + dramc_dbg("-----------------------------------" "-------------------\n"); - dramc_dbg_msg("Start DQS delay to find pass range," + dramc_dbg("Start DQS delay to find pass range," "DQ delay fixed to %#x...\n", FIRST_DQ_DELAY); - dramc_dbg_msg("------------------------------------" + dramc_dbg("------------------------------------" "------------------\n"); - dramc_dbg_msg("x-axis is bit #; y-axis is DQS delay (%d~%d)\n", + dramc_dbg("x-axis is bit #; y-axis is DQS delay (%d~%d)\n", FIRST_DQS_DELAY + 1, max_dqs_taps - 1); /* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */ @@ -1024,22 +1024,22 @@ dramk_check_dqs_win(&(dqdqs_perbit_dly[bit]), dly, max_dqs_taps - 1, fail_bit); if (fail_bit == 0) { - dramc_dbg_msg("o"); + dramc_dbg("o"); } else { - dramc_dbg_msg("x"); + dramc_dbg("x"); } } - dramc_dbg_msg("\n"); + dramc_dbg("\n"); } /* 3 calculate dq and dqs time */ - dramc_dbg_msg("-------------------------------" + dramc_dbg("-------------------------------" "-----------------------\n"); - dramc_dbg_msg("Start calculate dq time and dqs " + dramc_dbg("Start calculate dq time and dqs " "time:\n"); - dramc_dbg_msg("Find max DQS delay per byte / " + dramc_dbg("Find max DQS delay per byte / " "Adjust DQ delay to align DQS...\n"); - dramc_dbg_msg("--------------------------------" + dramc_dbg("--------------------------------" "----------------------\n"); /* As per byte, check max DQS delay in 8-bit. @@ -1059,7 +1059,7 @@ &max_dqsdly_byte[index]); if ((i + 1) % DQS_BIT_NUMBER == 0) - dramc_dbg_msg("----separate line----\n"); + dramc_dbg("----separate line----\n"); } for (i = 0; i < DATA_WIDTH_32BIT; i++) { @@ -1088,34 +1088,34 @@ if (fail == 1) /* error handling */ die("fail on %s()\n", __func__); - dramc_dbg_msg("==================================================\n"); - dramc_dbg_msg(" dramc_perbit_window_swcal:\n"); - dramc_dbg_msg(" channel=%d(0:cha, 1:chb)\n", channel); - dramc_dbg_msg(" bus width=%d\n", DATA_WIDTH_32BIT); - dramc_dbg_msg("==================================================\n"); - dramc_dbg_msg("DQS Delay :\n DQS0 = %d DQS1 = %d DQS2 = %d DQS3 = %d\n", + dramc_dbg("==================================================\n"); + dramc_dbg(" dramc_perbit_window_swcal:\n"); + dramc_dbg(" channel=%d(0:cha, 1:chb)\n", channel); + dramc_dbg(" bus width=%d\n", DATA_WIDTH_32BIT); + dramc_dbg("==================================================\n"); + dramc_dbg("DQS Delay :\n DQS0 = %d DQS1 = %d DQS2 = %d DQS3 = %d\n", max_dqsdly_byte[0], max_dqsdly_byte[1], max_dqsdly_byte[2], max_dqsdly_byte[3]); if (type == TX_WIN) - dramc_dbg_msg("DQM Delay :\n" + dramc_dbg("DQM Delay :\n" "DQM0 = %d DQM1 = %d DQM2 = %d DQM3 = %d\n", ave_dqdly_byte[0], ave_dqdly_byte[1], ave_dqdly_byte[2], ave_dqdly_byte[3]); - dramc_dbg_msg("DQ Delay :\n"); + dramc_dbg("DQ Delay :\n"); for (i = 0; i < DATA_WIDTH_32BIT; i++) { - dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly); + dramc_dbg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly); if (((i + 1) % 4) == 0) - dramc_dbg_msg("\n"); + dramc_dbg("\n"); } - dramc_dbg_msg("____________________________________" + dramc_dbg("____________________________________" "____________________________________\n"); if (type == TX_WIN) { /* Add CLK to DQS/DQ skew after write leveling */ - dramc_dbg_msg("Add CLK to DQS/DQ skew based on write leveling.\n"); + dramc_dbg("Add CLK to DQS/DQ skew based on write leveling.\n"); /* this subroutine add clk delay to DQS/DQ after WL */ tx_delay_for_wrleveling(channel, dqdqs_perbit_dly, max_dqsdly_byte, ave_dqdly_byte); diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 7ced662..08d15b4 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -3,6 +3,7 @@ #ifndef _DRAMC_PI_API_H #define _DRAMC_PI_API_H +#include <soc/dramc_common.h> #include <soc/emi.h> #include <console/console.h> @@ -165,10 +166,4 @@ void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); -#if CONFIG(DEBUG_DRAM) -#define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_) -#else -#define dramc_dbg_msg(_x_...) -#endif - #endif /* _PI_API_H */ diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index aace5c4..f7e0aa3 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -21,12 +21,6 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE -config DEBUG_DRAM - bool "Output verbose DRAM related debug messages" - default n - help - This option enables additional DRAM related debug messages. - config MT8183_DRAM_EMCP bool default n diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index b1a0c74..5ee6300 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -4,17 +4,10 @@ #define _DRAMC_PI_API_MT8183_H #include <types.h> +#include <soc/dramc_common.h> #include <soc/emi.h> #include <console/console.h> -#define dramc_err(_x_...) printk(BIOS_ERR, _x_) -#define dramc_show(_x_...) printk(BIOS_INFO, _x_) -#if CONFIG(DEBUG_DRAM) -#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) -#else -#define dramc_dbg(_x_...) -#endif - #define DATLAT_TAP_NUMBER 32 #define HW_REG_SHUFFLE_MAX 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d Gerrit-Change-Number: 51224 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: src/mediatek/common: Add DRAM common files
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin. Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51203 ) Change subject: src/mediatek/common: Add DRAM common files ...................................................................... src/mediatek/common: Add DRAM common files To reduce duplicated dram sources on seperate SOCs, add dpm, dram_init, dramc_params, memory(fast-k or full-k) implementations, also add dramc log level macro header files. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e --- A src/soc/mediatek/common/Kconfig A src/soc/mediatek/common/dpm.c A src/soc/mediatek/common/dram_init.c A src/soc/mediatek/common/dramc_param.c A src/soc/mediatek/common/include/soc/dpm.h A src/soc/mediatek/common/include/soc/dramc_common.h A src/soc/mediatek/common/include/soc/dramc_param.h A src/soc/mediatek/common/include/soc/emi.h A src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig 11 files changed, 650 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/51203/1 diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig new file mode 100644 index 0000000..7f45ce6 --- /dev/null +++ b/src/soc/mediatek/common/Kconfig @@ -0,0 +1,23 @@ +config MEDIATEK_DRAM_DVFS + bool + default n + help + This option enables DRAM calibration with multiple frequencies (low, + medium and high frequency groups, with total 7 frequencies) for DVFS + feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, + 3200, 4266. + +config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT + bool + default y + select MEDIATEK_DRAM_DVFS + help + This options limit DRAM frequency calibration count from total 7 to 3, + other frequency will directly use the low frequency shu result. + +config MEMORY_TEST + bool + default y + help + This option enables memory basic compare test to verify the DRAM read + or write is as expected. diff --git a/src/soc/mediatek/common/dpm.c b/src/soc/mediatek/common/dpm.c new file mode 100644 index 0000000..991441e --- /dev/null +++ b/src/soc/mediatek/common/dpm.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/dpm.h> +#include <soc/mcu_common.h> +#include <soc/symbols.h> + +static void reset_dpm(struct mtk_mcu *mcu) +{ + /* write bootargs */ + write32(&mtk_dpm->twam_window_len, 0x0); + write32(&mtk_dpm->twam_mon_type, 0x0); + + /* free RST */ + setbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET); +} + +static struct mtk_mcu dpm_mcu[] = { + { + .firmware_name = CONFIG_DPM_DM_FIRMWARE, + .run_address = (void *)DPM_DM_SRAM_BASE, + }, + { + .firmware_name = CONFIG_DPM_PM_FIRMWARE, + .run_address = (void *)DPM_PM_SRAM_BASE, + .reset = reset_dpm, + }, +}; + +int dpm_init(void) +{ + int i; + struct mtk_mcu *dpm; + + /* config DPM SRAM layout */ + clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1); + + for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) { + dpm = &dpm_mcu[i]; + dpm->load_buffer = _dram_dma; + dpm->buffer_size = REGION_SIZE(dram_dma); + if (mtk_init_mcu(dpm)) + return -1; + } + + return 0; +} diff --git a/src/soc/mediatek/common/dram_init.c b/src/soc/mediatek/common/dram_init.c new file mode 100644 index 0000000..3f13287 --- /dev/null +++ b/src/soc/mediatek/common/dram_init.c @@ -0,0 +1,34 @@ +#include <console/console.h> +#include <delay.h> +#include <print.h> +#include <stdint.h> +#include <soc/dramc_param.h> +#include <soc/emi.h> + +struct dramc_param *dramc_params; + +extern void (*do_putc)(unsigned char c); + +bool is_dvfs_enabled(void) +{ + print("dram_init: config_dvfs: %d\n", dramc_params->dramc_datas.ddr_info.config_dvfs); + return !!(dramc_params->dramc_datas.ddr_info.config_dvfs); +} + +u32 get_ddr_geometry(void) +{ + print("dram_init: ddr_geometry: %d\n", dramc_params->dramc_datas.ddr_info.ddr_geometry); + return dramc_params->dramc_datas.ddr_info.ddr_geometry; +} + +u32 get_ddr_type(void) +{ + print("dram_init: ddr_type: %d\n", dramc_params->dramc_datas.ddr_info.ddr_type); + return dramc_params->dramc_datas.ddr_info.ddr_type; +} + +void init_dram_by_params(const struct dramc_param *dparam) +{ + dramc_params = (struct dramc_param *)dparam; + mt_set_emi(dramc_params); +} diff --git a/src/soc/mediatek/common/dramc_param.c b/src/soc/mediatek/common/dramc_param.c new file mode 100644 index 0000000..8548dbc --- /dev/null +++ b/src/soc/mediatek/common/dramc_param.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <string.h> +#include <soc/dramc_param.h> + +#define print(_x_...) printk(BIOS_INFO, _x_) + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +void dump_param_header(const void *blob) +{ + const struct dramc_param *dparam = blob; + const struct dramc_param_header *header = &dparam->header; + + print("header.status = %#x\n", header->status); + print("header.version = %#x (expected: %#x)\n", + header->version, DRAMC_PARAM_HEADER_VERSION); + print("header.size = %#x (expected: %#lx)\n", + header->size, sizeof(*dparam)); + print("header.flags = %#x\n", header->flags); + print("header.checksum = %#x\n", header->checksum); +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = &param->header; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = &param->header; + + memset(hdr, 0, sizeof(*hdr)); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->size = sizeof(*param); + return 0; +} diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h new file mode 100644 index 0000000..7262e09 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dpm.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_DPM_H__ +#define __SOC_MEDIATEK_DPM_H__ + +#include <soc/addressmap.h> +#include <stdint.h> +#include <types.h> + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0); + +#define DPM_SW_RSTN_RESET BIT(0) +#define DPM_MEM_RATIO_OFFSET 28 +#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) +#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) + +static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; + +int dpm_init(void); + +#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dramc_common.h b/src/soc/mediatek/common/include/soc/dramc_common.h new file mode 100644 index 0000000..67540b4 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dramc_common.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_DRAMC_COMMON_H__ +#define __SOC_MEDIATEK_DRAMC_COMMON_H__ + +#include <console/console.h> + +#define dramc_err(_x_...) printk(BIOS_ERR, _x_) +#define dramc_info(_x_...) printk(BIOS_INFO, _x_) +#define dramc_show(_x_...) dramc_info +#define dramc_dbg(_x_...) \ + do { \ + if (CONFIG(DEBUG_RAM_SETUP)) \ + printk(BIOS_INFO, _x_); \ + } while (0) + +#endif diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/common/include/soc/dramc_param.h new file mode 100644 index 0000000..d3eda8d --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dramc_param.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_DRAMC_PARAM_H__ + +/* any change in this file should sync to blob dramc_param.h */ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_soc.h> + +enum { + DRAMC_PARAM_HEADER_VERSION = 5, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_FAST_CALIBRATION, +}; + +enum DRAMC_PARAM_DVFS_FLAG { + DRAMC_DISABLE_DVFS, + DRAMC_ENABLE_DVFS, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +enum DRAMC_PARAM_DDR_TYPE { + DDR_TYPE_DISCRETE, + DDR_TYPE_EMCP, +}; + +/* Don't change the order, which is matched with blob */ +enum DRAMC_PARAM_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + DDR_TYPE_2CH_1RK_4GB_4_0, + DDR_TYPE_2CH_2RK_6GB_2_4, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + +enum DRAM_PARAM_VOLTAGE_TYPE { + DRAM_VOLTAGE_NVCORE_NVDRAM, + DRAM_VOLTAGE_HVCORE_HVDRAM, + DRAM_VOLTAGE_LVCORE_LVDRAM, +}; + +struct dramc_param_header { + u32 checksum; /* checksum of dramc_datas, update in the coreboot */ + u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ + u16 size; /* size of whole dramc_param, update in the coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ + u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ +}; + +struct sdram_params { + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* Gating */ + u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* TX perbit */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* TX OE */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_base_info { + u32 config_dvfs; /* DRAMC_PARAM_DVFS_FLAG */ + u32 ddr_type; /* DRAMC_PARAM_DDR_TYPE */ + u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ + u32 voltage_type; /* DRAM_PARAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + dram_cbt_mode cbt_mode[RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +struct dramc_param_ops { + struct dramc_param *param; + bool (*read_from_flash)(struct dramc_param *dparam); + bool (*write_to_flash)(const struct dramc_param *dparam); +}; + +struct sdram_info { + u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ + u32 ddr_type; /* DRAMC_PARAM_DDR_TYPE */ +}; + +const struct sdram_info *get_sdram_config(void); +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob); +#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h new file mode 100644 index 0000000..8cc5e73 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_EMI_H +#define SOC_MEDIATEK_EMI_H + +#include <soc/dramc_param.h> + +size_t sdram_size(void); +void mt_set_emi(struct dramc_param *dparam); +void mt_mem_init(struct dramc_param_ops *dparam_ops); +int complex_mem_test(u8 *start, unsigned int len); + +bool is_dvfs_enabled(void); +u32 get_ddr_geometry(void); +u32 get_ddr_type(void); +void init_dram_by_params(const struct dramc_param *dparam); + +#endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c new file mode 100644 index 0000000..34d3d10 --- /dev/null +++ b/src/soc/mediatek/common/memory.c @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <bootmode.h> +#include <cbfs.h> +#include <console/console.h> +#include <ip_checksum.h> +#include <soc/emi.h> +#include <symbols.h> +#include <timer.h> + +const char *get_dram_geometry_str(u32 ddr_geometry); +const char *get_dram_type_str(u32 ddr_type); + +static int mt_mem_test(const struct dramc_data *dparam) +{ + if (CONFIG(MEMORY_TEST)) { + u8 *addr = _dram; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { + int result = complex_mem_test(addr, 0x2000); + + if (result != 0) { + printk(BIOS_ERR, + "[MEM] complex R/W mem test failed: %d\n", result); + return -1; + } else { + printk(BIOS_DEBUG, "[MEM] complex R/W mem test passed\n"); + } + + addr += ddr_info->rank_size[rank]; + } + } + + return 0; +} + +static u32 compute_checksum(const struct dramc_param *dparam) +{ + return (u32)compute_ip_checksum(&dparam->dramc_datas, + sizeof(dparam->dramc_datas)); +} + +const char *get_dram_geometry_str(u32 ddr_geometry) +{ + const char *s; + + switch (ddr_geometry) { + case DDR_TYPE_2CH_2RK_4GB_2_2: + s = "2CH_2RK_4GB_2_2"; + break; + case DDR_TYPE_2CH_2RK_6GB_3_3: + s = "2CH_2RK_6GB_3_3"; + break; + case DDR_TYPE_2CH_2RK_8GB_4_4: + s = "2CH_2RK_8GB_4_4"; + break; + case DDR_TYPE_2CH_2RK_8GB_4_4_BYTE: + s = "2CH_2RK_8GB_4_4_BYTE"; + break; + case DDR_TYPE_2CH_1RK_4GB_4_0: + s = "2CH_1RK_4GB_4_0"; + break; + case DDR_TYPE_2CH_2RK_6GB_2_4: + s = "2CH_2RK_6GB_2_4"; + break; + default: + s = ""; + break; + } + + return s; +} + +const char *get_dram_type_str(u32 ddr_type) +{ + const char *s; + + switch (ddr_type) { + case DDR_TYPE_DISCRETE: + s = "DSC"; + break; + case DDR_TYPE_EMCP: + s = "EMCP"; + break; + default: + s = ""; + break; + } + + return s; +} + +static int dram_run_fast_calibration(const struct dramc_param *dparam) +{ + if (!is_valid_dramc_param(dparam)) { + printk(BIOS_WARNING, "DRAM-K: Invalid DRAM calibration data from flash\n"); + dump_param_header((void *)dparam); + return -1; + } + + const u32 checksum = compute_checksum(dparam); + if (dparam->header.checksum != checksum) { + printk(BIOS_ERR, + "DRAM-K: Invalid DRAM calibration checksum from flash " + "(expected: %#x, saved: %#x)\n", + checksum, dparam->header.checksum); + return DRAMC_ERR_INVALID_CHECKSUM; + } + + const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; + if (dparam->dramc_datas.ddr_info.config_dvfs != config) { + printk(BIOS_WARNING, + "DRAM-K: Incompatible config for calibration data from flash " + "(expected: %#x, saved: %#x)\n", + config, dparam->dramc_datas.ddr_info.config_dvfs); + return -1; + } + + printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); + init_dram_by_params(dparam); + if (mt_mem_test(&dparam->dramc_datas) == 0) + return 0; + + return DRAMC_ERR_FAST_CALIBRATION; +} + +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) { + printk(BIOS_ERR, "DRAM-K: Locate program failed\n"); + return -1; + } + + if (cbfs_prog_stage_load(&dram)) { + printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n"); + return -2; + } + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "DRAM-K: Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + +static void mem_init_set_default_config(struct dramc_param *dparam, + const struct sdram_info *dram_info) +{ + u32 type, geometry; + memset(dparam, 0, sizeof(*dparam)); + + type = dram_info->ddr_type; + geometry = dram_info->ddr_geometry; + + dparam->dramc_datas.ddr_info.ddr_type = type; + + if (CONFIG(MEDIATEK_DRAM_DVFS)) + dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS; + + dparam->dramc_datas.ddr_info.ddr_geometry = geometry; + + printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n", + get_dram_type_str(type), + dparam->dramc_datas.ddr_info.config_dvfs, + get_dram_geometry_str(geometry)); +} + +static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, + const struct sdram_info *dram_info) +{ + struct dramc_param *dparam = dparam_ops->param; + struct stopwatch sw; + int ret; + + /* Load calibration params from flash and run fast calibration */ + mem_init_set_default_config(dparam, dram_info); + if (dparam_ops->read_from_flash(dparam)) { + printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); + stopwatch_init(&sw); + + ret = dram_run_fast_calibration(dparam); + if (ret != 0) { + printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " + "in %ld msecs, error: %d\n", + stopwatch_duration_msecs(&sw), ret); + + /* Erase flash data after fast calibration failed */ + memset(dparam, 0xa5, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } else { + printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + return; + } + } else { + printk(BIOS_WARNING, "DRAM-K: Failed to read calibration data from flash\n"); + } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); + mem_init_set_default_config(dparam, dram_info); + + stopwatch_init(&sw); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "DRAM-K: Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } else { + printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + } +} + +void mt_mem_init(struct dramc_param_ops *dparam_ops) +{ + const struct sdram_info *sdram_param = get_sdram_config(); + + mt_mem_init_run(dparam_ops, sdram_param); +} diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 15b833f..0c37998 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -22,10 +22,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE -config MEMORY_TEST - bool - default n - config DEBUG_SOC_DRIVER bool "The top level switch for soc driver debug messages" default n diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index ce99c76..aace5c4 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -41,10 +41,6 @@ This options enables DRAM calibration with multiple frequencies (low, medium and high) for DVFS feature. -config MEMORY_TEST - bool - default y - config SSPM_FIRMWARE string default "sspm.bin" -- To view, visit https://review.coreboot.org/c/coreboot/+/51203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e Gerrit-Change-Number: 51203 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/asurada: Add generic DRAM groups
by Xi Chen (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/51202 to review the following change. Change subject: mb/google/asurada: Add generic DRAM groups ...................................................................... mb/google/asurada: Add generic DRAM groups To reduce qualification effort, we want to pre-populate DRAM by their size, package type and geometry so when a new DRAM is introduced we don't need to spin off a new firmware release. Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f --- M src/mainboard/google/asurada/boardid.c M src/mainboard/google/asurada/sdram_configs.c M src/mainboard/google/asurada/sdram_params/Makefile.inc A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-1RANK-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-1RANK-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-8GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c M src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c 14 files changed, 209 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/51202/1 diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c index cb91812..06c21ec 100644 --- a/src/mainboard/google/asurada/boardid.c +++ b/src/mainboard/google/asurada/boardid.c @@ -10,7 +10,8 @@ #define ADC_LEVELS 15 enum { - RAM_ID_CHANNEL = 3, + RAM_ID_HIGH_CHANNEL = 4, + RAM_ID_LOW_CHANNEL = 3, }; static const unsigned int ram_voltages[ADC_LEVELS] = { @@ -33,7 +34,8 @@ }; static const unsigned int *adc_voltages[] = { - [RAM_ID_CHANNEL] = ram_voltages, + [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [RAM_ID_LOW_CHANNEL] = ram_voltages, }; static uint32_t get_adc_index(unsigned int channel) @@ -63,8 +65,11 @@ { static uint32_t cached_ram_code = BOARD_ID_INIT; - if (cached_ram_code == BOARD_ID_INIT) - cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } return cached_ram_code; } diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c index e1eb527..9a0133f 100644 --- a/src/mainboard/google/asurada/sdram_configs.c +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -5,9 +5,121 @@ #include <console/console.h> #include <soc/dramc_param.h> +/* Reference: go/asurada-id */ static const char *const sdram_configs[] = { - [0] = "sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB", - [1] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB", + /* Exceptional legacy module */ + [0x00] = "sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB", + [0x01] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB", + [0x02] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [0x03] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + + /* Group 0x0: eMCP 4GB single rank. */ + [0x04] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x05] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x06] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x07] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x08] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x09] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x0a] = "sdram-lpddr4x-EMCP-1RANK-4GB", + [0x0b] = "sdram-lpddr4x-EMCP-1RANK-4GB", + + /* Group 0x1: eMCP 4GB dual rank. */ + [0x10] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x11] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x12] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x13] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x14] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x15] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x16] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x17] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x18] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x19] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x1a] = "sdram-lpddr4x-EMCP-2RANK-4GB", + [0x1b] = "sdram-lpddr4x-EMCP-2RANK-4GB", + + /* Group 0x2: eMCP 8GB dual rank. */ + [0x20] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x21] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x22] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x23] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x24] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x25] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x26] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x27] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x28] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x29] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x2a] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x2b] = "sdram-lpddr4x-EMCP-2RANK-8GB", + + /* Group 0x3: eMCP 8GB dual rank. */ + [0x30] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x31] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x32] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x33] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x34] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x35] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x36] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x37] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x38] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x39] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x3a] = "sdram-lpddr4x-EMCP-2RANK-8GB", + [0x3b] = "sdram-lpddr4x-EMCP-2RANK-8GB", + + /* Group 0x4: discrete 4GB single rank. */ + [0x40] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x41] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x42] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x43] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x44] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x45] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x46] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x47] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x48] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x49] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x4a] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + [0x4b] = "sdram-lpddr4x-DISCRETE-1RANK-4GB", + + /* Group 0x5: discrete 4GB dual rank. */ + [0x50] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x51] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x52] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x53] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x54] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x55] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x56] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x57] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x58] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x59] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x5a] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + [0x5b] = "sdram-lpddr4x-DISCRETE-2RANK-4GB", + + /* Group 0x6: discrete 8GB dual rank. */ + [0x60] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x61] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x62] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x63] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x64] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x65] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x66] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x67] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x68] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x69] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x6a] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + [0x6b] = "sdram-lpddr4x-DISCRETE-2RANK-8GB", + + /* Group 0x7: discrete 8GB dual rank byte mode. */ + [0x70] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x71] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x72] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x73] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x74] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x75] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x76] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x77] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x78] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x79] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x7a] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", + [0x7b] = "sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE", }; static struct sdram_info params; diff --git a/src/mainboard/google/asurada/sdram_params/Makefile.inc b/src/mainboard/google/asurada/sdram_params/Makefile.inc index acc8b58..20df2ba 100644 --- a/src/mainboard/google/asurada/sdram_params/Makefile.inc +++ b/src/mainboard/google/asurada/sdram_params/Makefile.inc @@ -1,6 +1,18 @@ sdram-params := + +# Generic parameters +sdram-params += sdram-lpddr4x-EMCP-1RANK-4GB +sdram-params += sdram-lpddr4x-EMCP-2RANK-4GB +sdram-params += sdram-lpddr4x-EMCP-2RANK-8GB +sdram-params += sdram-lpddr4x-DISCRETE-1RANK-4GB +sdram-params += sdram-lpddr4x-DISCRETE-2RANK-4GB +sdram-params += sdram-lpddr4x-DISCRETE-2RANK-8GB +sdram-params += sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE + sdram-params += sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB sdram-params += sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB +sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-1RANK-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-1RANK-4GB.c new file mode 100644 index 0000000..aef8512 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-1RANK-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-4GB.c new file mode 100644 index 0000000..5735df5 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE.c new file mode 100644 index 0000000..51e8a6f --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB.c new file mode 100644 index 0000000..3d12588 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-DISCRETE-2RANK-8GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-1RANK-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-1RANK-4GB.c new file mode 100644 index 0000000..15217f0 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-1RANK-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, + .ddr_type = DDR_TYPE_EMCP, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-4GB.c new file mode 100644 index 0000000..bed9418 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_EMCP, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-8GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-8GB.c new file mode 100644 index 0000000..17c954c --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-EMCP-2RANK-8GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .ddr_type = DDR_TYPE_EMCP, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c new file mode 100644 index 0000000..bed9418 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_EMCP, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c new file mode 100644 index 0000000..bed9418 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_EMCP, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c index 8ae9b69..15217f0 100644 --- a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c @@ -4,4 +4,5 @@ struct sdram_info params = { .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, + .ddr_type = DDR_TYPE_EMCP, }; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c index 36fc0a2..bfd2720 100644 --- a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c @@ -4,4 +4,5 @@ struct sdram_info params = { .ddr_geometry = DDR_TYPE_2CH_2RK_6GB_3_3, + .ddr_type = DDR_TYPE_EMCP, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/51202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f Gerrit-Change-Number: 51202 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/blipper: Enable touchpad support
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Martin Roth, zanxi chen, Tao Xia, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51188 ) Change subject: mb/google/dedede/var/blipper: Enable touchpad support ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51188/comment/2341c231_4c4bfeb5 PS2, Line 13: TEST=built blipper firmware and verified touchpad function Maybe paste the Linux kernel detection message or part of the of `libinput list-devices`. -- To view, visit https://review.coreboot.org/c/coreboot/+/51188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617 Gerrit-Change-Number: 51188 Gerrit-PatchSet: 2 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:10:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/blipper: Generate SPD ID for supported memory parts
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Martin Roth, zanxi chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51201 ) Change subject: mb/google/dedede/var/blipper: Generate SPD ID for supported memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3 Gerrit-Change-Number: 51201 Gerrit-PatchSet: 1 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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