coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

1 participants
7266 discussions

Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak. Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50754 to look at the new patch set (#4). Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... soc/intel/common: Prevent SMI storm when setting SPI WPD bit From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMM handler, which results in a deadlock. Avoid deadlocks by clearing the SPI status bits in the SMM handler. This patch does not handle eSPI because I cannot test it, and knowing whether a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS write protection. However, write protection is still not being enforced. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/50754/comment/c84a0283_3d3c5dcb PS1, Line 398: fast_spi_enable_wp > I can't find that document. Is it public? […] Ack File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/50754/comment/da1308c1_bbbe9507 PS1, Line 363: if (fast_spi_wpd_status()) { > if possible you shouldn't touch wpd in this commit at all. only reset the SMI status bits to prevent SMI storm. Done https://review.coreboot.org/c/coreboot/+/50754/comment/f4c41a4f_56060dbf PS1, Line 368: uint16_t bios_cntl = pci_read_config16(PCH_DEV_LPC, 0xdc); > Regarding LPC, even if CB:40830 doesn't enable protection, I guess it doesn't hurt to handle BIOSWR_ […] eSPI is not handled in this patch. I don't have a board with eSPI to test things on and the SOC_ESPI Kconfig option is specific to APL. https://review.coreboot.org/c/coreboot/+/50754/comment/f2b78e68_9371c5a5 PS1, Line 368: PCH_DEV_LPC > SPI_SYNC_SS clearing (discussed above) must also be done on eSPI (but not LPC). […] eSPI is not handled in this patch. (see above comment for reasoning) -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 12:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak. Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50754 to look at the new patch set (#3). Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... soc/intel/common: Prevent SMI storm when setting SPI WPD bit From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMM handler, which results in a deadlock. Avoid deadlocks by clearing the SPI status bits in the SMM handler. Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS write protection. However, write protection is still not being enforced. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/fast_spi: Clean up header
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50752 to look at the new patch set (#5). Change subject: soc/intel/common/block/fast_spi: Clean up header ...................................................................... soc/intel/common/block/fast_spi: Clean up header Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex values and rename BIOS_CONTROL macros, as the register is not in SPIBAR. Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 3 files changed, 58 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/50752/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/50752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Gerrit-Change-Number: 50752 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by chris wang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang, EricR Lai. chris wang has uploaded a new patch set (#6) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zork/variants/vilboz/romstage.c 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49683/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by chris wang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang, EricR Lai. chris wang has uploaded a new patch set (#5) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zork/variants/vilboz/romstage.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49683/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by chris wang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang, EricR Lai. chris wang has uploaded a new patch set (#4) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zork/variants/vilboz/romstage.c M src/mainboard/google/zork/variants/vilboz/variant.c 4 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49683/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by build bot (Jenkins) (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang, EricR Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/zork/variants/vilboz/romstage.c: https://review.coreboot.org/c/coreboot/+/49683/comment/c600c588_752b4847 PS3, Line 22: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 12:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by chris wang (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang, EricR Lai. chris wang has uploaded a new patch set (#3) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zork/variants/vilboz/romstage.c M src/mainboard/google/zork/variants/vilboz/variant.c 4 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49683/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/zork: add UPDM updating function before runing FSP-M
by chris wang (Code Review) 03 Mar '21

03 Mar '21

chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51181 ) Change subject: mb/google/zork: add UPDM updating function before runing FSP-M ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/51181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4954a438a51b29b086015624127e651fd06f971b Gerrit-Change-Number: 51181 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 12:01:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2021