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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
soc/intel/common: Prevent SMI storm when setting SPI WPD bit
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMM handler, which results in a deadlock.
Avoid deadlocks by clearing the SPI status bits in the SMM handler.
Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS
write protection. However, write protection is still not being enforced.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 20 insertions(+), 2 deletions(-)
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Change subject: soc/intel/common/block/fast_spi: Clean up header
......................................................................
soc/intel/common/block/fast_spi: Clean up header
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex
values and rename BIOS_CONTROL macros, as the register is not in SPIBAR.
Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
3 files changed, 58 insertions(+), 59 deletions(-)
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
---
M src/mainboard/google/zork/variants/baseboard/helpers.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/zork/variants/vilboz/romstage.c
3 files changed, 31 insertions(+), 0 deletions(-)
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
---
M src/mainboard/google/zork/variants/baseboard/helpers.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/zork/variants/vilboz/romstage.c
3 files changed, 32 insertions(+), 0 deletions(-)
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
---
M src/mainboard/google/zork/variants/baseboard/helpers.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/zork/variants/vilboz/romstage.c
M src/mainboard/google/zork/variants/vilboz/variant.c
4 files changed, 33 insertions(+), 0 deletions(-)
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/zork/variants/vilboz/romstage.c:
https://review.coreboot.org/c/coreboot/+/49683/comment/c600c588_752b4847
PS3, Line 22: }
adding a line without newline at end of file
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chris wang has uploaded a new patch set (#3) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/49683 )
Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
---
M src/mainboard/google/zork/variants/baseboard/helpers.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/zork/variants/vilboz/romstage.c
M src/mainboard/google/zork/variants/vilboz/variant.c
4 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/49683/3
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/apollolake: Add `GPE0_STS_BIT` macro
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/apollolake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/50916/comment/3e3fa791_4913f5f5
PS1, Line 111: GPE0_STS_BIT
> Not the best at it, but I can give it a try :P: […]
I've done something else so that common code doesn't need to know that this bit is actually reserved. Thoughts?
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
......................................................................
soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.
Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.
Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
2 files changed, 6 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/50750/6
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