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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls
......................................................................
soc/intel/xeon_sp: Lockdown SPI BIOS controls
Lockdown SPI based on Intel BWG recommendation.
Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
A src/soc/intel/xeon_sp/include/soc/spi.h
M src/soc/intel/xeon_sp/lockdown.c
2 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51227/3
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51167 )
Change subject: util: Add new memory part to LP4x list
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51167/comment/0410412d_187f018a
PS6, Line 7: Add new memory part for brya boards
> nit: Add new memory part to LP4x list […]
Done
https://review.coreboot.org/c/coreboot/+/51167/comment/9b771845_89ae412f
PS6, Line 10: are derived from data sheets.
> Also, regenerate the SPD files for ADL SoC using the newly added parts.
Done
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Change subject: util: Add new memory part to LP4x list
......................................................................
util: Add new memory part to LP4x list
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.Also, regenerate the SPD files for ADL
SoC using the newly added parts.
BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
A src/soc/intel/alderlake/spd/lp4x-spd-6.hex
A src/soc/intel/alderlake/spd/lp4x-spd-7.hex
M src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
4 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/51167/7
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Hello Jonathan Zhang, Jay Talbott, Johnny Lin, Stefan Reinauer, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51227
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls
......................................................................
soc/intel/xeon_sp: Lockdown SPI BIOS controls
Lockdown SPI based on Intel BWG recommendation.
Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481
Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com>
---
A src/soc/intel/xeon_sp/include/soc/spi.h
M src/soc/intel/xeon_sp/lockdown.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51227/2
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Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51200 )
Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
......................................................................
Patch Set 4:
(3 comments)
File src/mainboard/google/volteer/romstage.c:
https://review.coreboot.org/c/coreboot/+/51200/comment/68853dfe_59993891
PS4, Line 25: memcfg_variant_init
I think you can put a default __weak memcfg_variant_init() in this file. For example:
void __weak memcfg_variant_init(FSPM_UPD *mupd)
{
}
after that, you can remove the __weak the *.h can *.c from the other files
File src/mainboard/google/volteer/variants/lindar/memory.c:
https://review.coreboot.org/c/coreboot/+/51200/comment/b3c705f7_710f1806
PS4, Line 67: __weak
remove this.
File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/51200/comment/92351c7d_291132a9
PS4, Line 10: void __weak memcfg_variant_init(FSPM_UPD *mupd);
I think you can put this to mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49683/comment/48271323_e2790346
PS6, Line 13: BRANCH=zork
How is this tested? Maybe paste the new log messages?
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Change subject: device/azalia_device: Fix STATESTS register and add defines
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c
......................................................................
Abandoned
Change isn't needed at this time
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Change subject: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
I am abandoning this for now. There isn't a specific need to move these settings.
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Change subject: soc/intel/xeon_sp: Add PCH lockdown
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/pch/Kconfig:
https://review.coreboot.org/c/coreboot/+/49849/comment/ba225b1c_d2549cf0
PS4, Line 21: if !XEON_SP_COMMON_BASE
> SERVER/CLIENT distinction would be a good starting point. […]
We could at least add a SERVER group for this patch. It would make this a little cleaner. Since this has been mostly used by mobile, it would be good to get some input and help from the *lake developers.
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