coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

1 participants
7266 discussions

Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Aamir Bohra. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > @Tim, could we change the name? I checked deltan it use PCH_BT_RADIO_DIS. […] IIRC it is for RF-kill or to reset the module. You mean change the signal name on the schematic? -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:22:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/gaze15: Add System76 Gazelle 15
by Tim Crawford (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Martin Roth, Jeremy Soller, Paul Menzel, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47822 ) Change subject: mb/system76/gaze15: Add System76 Gazelle 15 ...................................................................... Patch Set 9: (1 comment) File src/mainboard/system76/gaze15/gpio.c: https://review.coreboot.org/c/coreboot/+/47822/comment/680efd8c_c86aa24e PS8, Line 98: // > I simply booted the board without any GPIO config and then checked against vendor firmware values an […] This is taking me a while to do, since I don't know what changes are significant between the vendor firmware, leaving them unset, and what we set. Almost every GPIO is configured differently in vendor firmware. If I'm parsing it right, vendor firmware configures IOSTERM, but IOSTANDBY isn't enabled on CML. -- To view, visit https://review.coreboot.org/c/coreboot/+/47822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Gerrit-Change-Number: 47822 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeonsp: Set LPC EISS enable
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51228 ) Change subject: soc/intel/xeonsp: Set LPC EISS enable ...................................................................... soc/intel/xeonsp: Set LPC EISS enable Additional BIOS region lock recommended by Intel PCH documentation. This lock causes an SMI before the BIOS region is written. Change-Id: I3d768763618473a4c4d7a69fb3448691c5d07522 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51228/1 diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index cfbf94b..965c5c4 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -36,6 +36,7 @@ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); + lpc_set_eiss(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d768763618473a4c4d7a69fb3448691c5d07522 Gerrit-Change-Number: 51228 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Lockdown SPI BIOS controls
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Jay Talbott, Johnny Lin, Stefan Reinauer, Patrick Rudolph. Hello build bot (Jenkins), Jonathan Zhang, Jay Talbott, Johnny Lin, Stefan Reinauer, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51227 to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls ...................................................................... soc/intel/xeon_sp: Lockdown SPI BIOS controls Lockdown SPI based on Intel BWG recommendation. Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- A src/soc/intel/xeon_sp/include/soc/spi.h M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51227/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Gerrit-Change-Number: 51227 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util: Add new memory part to LP4x list
by EricR Lai (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Amanda Hwang, Ivy Jian, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51167 ) Change subject: util: Add new memory part to LP4x list ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51167/comment/0410412d_187f018a PS6, Line 7: Add new memory part for brya boards > nit: Add new memory part to LP4x list […] Done https://review.coreboot.org/c/coreboot/+/51167/comment/9b771845_89ae412f PS6, Line 10: are derived from data sheets. > Also, regenerate the SPD files for ADL SoC using the newly added parts. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Gerrit-Change-Number: 51167 Gerrit-PatchSet: 7 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:45:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util: Add new memory part to LP4x list
by EricR Lai (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Amanda Hwang, Ivy Jian, Patrick Rudolph. EricR Lai has uploaded a new patch set (#7) to the change originally created by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/51167 ) Change subject: util: Add new memory part to LP4x list ...................................................................... util: Add new memory part to LP4x list Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- A src/soc/intel/alderlake/spd/lp4x-spd-6.hex A src/soc/intel/alderlake/spd/lp4x-spd-7.hex M src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 4 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/51167/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/51167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Gerrit-Change-Number: 51167 Gerrit-PatchSet: 7 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Lockdown SPI BIOS controls
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Jonathan Zhang, Jay Talbott, Johnny Lin, Stefan Reinauer, Patrick Rudolph. Hello Jonathan Zhang, Jay Talbott, Johnny Lin, Stefan Reinauer, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51227 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls ...................................................................... soc/intel/xeon_sp: Lockdown SPI BIOS controls Lockdown SPI based on Intel BWG recommendation. Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- A src/soc/intel/xeon_sp/include/soc/spi.h M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51227/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Gerrit-Change-Number: 51227 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
by Zhuohao Lee (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Furquan Shaikh, Kevin Chang, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51200 ) Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB ...................................................................... Patch Set 4: (3 comments) File src/mainboard/google/volteer/romstage.c: https://review.coreboot.org/c/coreboot/+/51200/comment/68853dfe_59993891 PS4, Line 25: memcfg_variant_init I think you can put a default __weak memcfg_variant_init() in this file. For example: void __weak memcfg_variant_init(FSPM_UPD *mupd) { } after that, you can remove the __weak the *.h can *.c from the other files File src/mainboard/google/volteer/variants/lindar/memory.c: https://review.coreboot.org/c/coreboot/+/51200/comment/b3c705f7_710f1806 PS4, Line 67: __weak remove this. File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/51200/comment/92351c7d_291132a9 PS4, Line 10: void __weak memcfg_variant_init(FSPM_UPD *mupd); I think you can put this to mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h -- To view, visit https://review.coreboot.org/c/coreboot/+/51200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Gerrit-Change-Number: 51200 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:35:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: John Su, Chris Wang, chris wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49683 ) Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49683/comment/48271323_e2790346 PS6, Line 13: BRANCH=zork How is this tested? Maybe paste the new log messages? -- To view, visit https://review.coreboot.org/c/coreboot/+/49683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Gerrit-Change-Number: 49683 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:28:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: device/azalia_device: Fix STATESTS register and add defines
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50790 ) Change subject: device/azalia_device: Fix STATESTS register and add defines ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Gerrit-Change-Number: 50790 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:27:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2021