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Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51180/comment/02371747_baaa0367
PS2, Line 7: multidomain
I am curious what the use cases for the multi-domain support are? Last when I looked into this, there are tons of assumptions in coreboot that there is only a single domain. e.g. resource allocator. Lots of those assumptions will have to be revisited and fixed for enabling multi-domain support.
Also, this has been a question long on my mind. How do you define a domain? Is defining multiple domains the answer for the problem you are looking at? Or does it need multiple buses under a single domain. This is critical to ensure proper hierarchy and resource allocation.
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Change subject: soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bit
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Hi Subrata
I wonder is this design applies to client side FSP . If that is the case, we should make this logic generic to FSP 2.0; otherwise, we will have it in soc.intel/xeon_sp.
Note that this code change is backward compatible with older CPX-SP FSPs, but recent CPS-SP FSPs without this code change suffers boot performance issue.
Thanks,
Jonathan
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Change subject: soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bit
......................................................................
soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bit
If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
data is present.
Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b
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---
M src/soc/intel/xeon_sp/cpx/chip.h
M src/soc/intel/xeon_sp/cpx/romstage.c
2 files changed, 18 insertions(+), 0 deletions(-)
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Change subject: soc/intel/xeon_sp: Set the MRC "cold boot required" status bit
......................................................................
soc/intel/xeon_sp: Set the MRC "cold boot required" status bit
If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
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---
M src/soc/intel/xeon_sp/cpx/chip.h
M src/soc/intel/xeon_sp/cpx/romstage.c
2 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/51230/3
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Change subject: nb/intel/haswell: Program Mini-HD EM4 and EM5 registers
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
With refactor commit it built and ran on T440P.
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Change subject: soc/intel/xeon_sp: Set the MRC "cold boot required" status bit
......................................................................
soc/intel/xeon_sp: Set the MRC "cold boot required" status bit
If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
data is present.
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---
M 3rdparty/blobs
M 3rdparty/chromeec
M 3rdparty/fsp
M src/soc/intel/xeon_sp/cpx/chip.h
M src/soc/intel/xeon_sp/cpx/romstage.c
5 files changed, 21 insertions(+), 3 deletions(-)
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
---
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/romstage.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/romstage.c
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
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Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
---
M src/mainboard/google/zork/variants/baseboard/helpers.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/zork/variants/vilboz/Makefile.inc
A src/mainboard/google/zork/variants/vilboz/romstage.c
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Change subject: mb/google/guybrush: Enable Chrome EC
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/ec.c:
https://review.coreboot.org/c/coreboot/+/51043/comment/b5a57bdd_a3745994
PS2, Line 18: google_chromeec_events_init(&info, acpi_is_wakeup_s3());
> i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/default/GOOGLE_GUYBRUSH/generated/ramstage. […]
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