coreboot-gerrit March 2021

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Change in coreboot[master]: soc/intel/common/block/fast_spi: Clean up header
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50752 ) Change subject: soc/intel/common/block/fast_spi: Clean up header ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Gerrit-Change-Number: 50752 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 16:00:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Lockdown SPI BIOS controls
by Jay Talbott (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Johnny Lin, Stefan Reinauer, Patrick Rudolph. Jay Talbott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51227 ) Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Gerrit-Change-Number: 51227 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:57:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set SMI lock
by Jay Talbott (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Johnny Lin, Stefan Reinauer, Patrick Rudolph. Jay Talbott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51226 ) Change subject: soc/intel/xeon_sp: Set SMI lock ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418 Gerrit-Change-Number: 51226 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:55:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add support for 2 new DRAM parts
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51170 ) Change subject: mb/google/brya: Add support for 2 new DRAM parts ...................................................................... mb/google/brya: Add support for 2 new DRAM parts 1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/variants/brya0/memory/Makefile.inc M src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc index b8229c4..79605c2 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc @@ -3,3 +3,5 @@ SPD_SOURCES = SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt index 45b69ae..d926626 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt @@ -1,3 +1,5 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:F 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +MT53E2G32D4NQ-046 WT:A 2 (0010) diff --git a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt index 5f83732..178c17d 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt @@ -1,2 +1,4 @@ MT53E512M32D2NP-046 WT:F H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +MT53E2G32D4NQ-046 WT:A -- To view, visit https://review.coreboot.org/c/coreboot/+/51170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Gerrit-Change-Number: 51170 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util: Add new memory part to LP4x list
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51167 ) Change subject: util: Add new memory part to LP4x list ...................................................................... util: Add new memory part to LP4x list Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/soc/intel/alderlake/spd/lp4x-spd-6.hex A src/soc/intel/alderlake/spd/lp4x-spd-7.hex M src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 4 files changed, 79 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-6.hex b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex new file mode 100644 index 0000000..9c49a00 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex @@ -0,0 +1,32 @@ +23 11 11 0E 14 19 94 08 00 00 00 00 02 01 00 00 +00 00 04 0A 80 54 05 00 87 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-7.hex b/src/soc/intel/alderlake/spd/lp4x-spd-7.hex new file mode 100644 index 0000000..cadc358 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-7.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 29 B4 08 00 00 00 00 0A 01 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt index f09a27f..347118d 100644 --- a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt @@ -17,3 +17,6 @@ H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex +NT6AP256T32AV-J1,lp4x-spd-6.hex +MT53E1G32D4NQ-046 WT:E,lp4x-spd-3.hex +MT53E2G32D4NQ-046 WT:A,lp4x-spd-7.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index fcbe624..2cc1fa4 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -255,6 +255,18 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "MT53E2G32D4NQ-046 WT:A", + "attribs": { + "densityPerChannelGb": 16, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/51167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Gerrit-Change-Number: 51167 Gerrit-PatchSet: 8 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by EricR Lai (Code Review) 03 Mar '21

03 Mar '21

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > IIRC it is for RF-kill or to reset the module. […] Yes. This may not so confused and miss configure it. -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:26:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... mb/google/brya: fix BT enumeration issue Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index b70f156..aa5dc8f 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -274,7 +274,7 @@ register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F4)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port10 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Aamir Bohra. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > @Tim, could we change the name? I checked deltan it use PCH_BT_RADIO_DIS. […] IIRC it is for RF-kill or to reset the module. You mean change the signal name on the schematic? -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:22:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/gaze15: Add System76 Gazelle 15
by Tim Crawford (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Martin Roth, Jeremy Soller, Paul Menzel, Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47822 ) Change subject: mb/system76/gaze15: Add System76 Gazelle 15 ...................................................................... Patch Set 9: (1 comment) File src/mainboard/system76/gaze15/gpio.c: https://review.coreboot.org/c/coreboot/+/47822/comment/680efd8c_c86aa24e PS8, Line 98: // > I simply booted the board without any GPIO config and then checked against vendor firmware values an […] This is taking me a while to do, since I don't know what changes are significant between the vendor firmware, leaving them unset, and what we set. Almost every GPIO is configured differently in vendor firmware. If I'm parsing it right, vendor firmware configures IOSTERM, but IOSTANDBY isn't enabled on CML. -- To view, visit https://review.coreboot.org/c/coreboot/+/47822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Gerrit-Change-Number: 47822 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 15:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeonsp: Set LPC EISS enable
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51228 ) Change subject: soc/intel/xeonsp: Set LPC EISS enable ...................................................................... soc/intel/xeonsp: Set LPC EISS enable Additional BIOS region lock recommended by Intel PCH documentation. This lock causes an SMI before the BIOS region is written. Change-Id: I3d768763618473a4c4d7a69fb3448691c5d07522 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51228/1 diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index cfbf94b..965c5c4 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -36,6 +36,7 @@ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); + lpc_set_eiss(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d768763618473a4c4d7a69fb3448691c5d07522 Gerrit-Change-Number: 51228 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2021