Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51228 )
Change subject: soc/intel/xeonsp: Set LPC EISS enable ......................................................................
soc/intel/xeonsp: Set LPC EISS enable
Additional BIOS region lock recommended by Intel PCH documentation. This lock causes an SMI before the BIOS region is written.
Change-Id: I3d768763618473a4c4d7a69fb3448691c5d07522 Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51228/1
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index cfbf94b..965c5c4 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -36,6 +36,7 @@ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); + lpc_set_eiss(); } }