coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Marc Jones has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49913 ) Change subject: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c ...................................................................... Abandoned Change isn't needed at this time -- To view, visit https://review.coreboot.org/c/coreboot/+/49913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3319cbbfc44e6232033e9d7f299f45d9f22b07 Gerrit-Change-Number: 49913 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Martin Roth, Jonathan Zhang, Rocky Phagura, Arthur Heymans, Patrick Rudolph. Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49913 ) Change subject: soc/intel/xeon_sp/cpx: Move soc_final to finalize.c ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I am abandoning this for now. There isn't a specific need to move these settings. -- To view, visit https://review.coreboot.org/c/coreboot/+/49913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3319cbbfc44e6232033e9d7f299f45d9f22b07 Gerrit-Change-Number: 49913 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:23:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add PCH lockdown
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Jonathan Zhang, Johnny Lin, Stefan Reinauer, Rocky Phagura, Angel Pons, Patrick Rudolph. Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49849 ) Change subject: soc/intel/xeon_sp: Add PCH lockdown ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/pch/Kconfig: https://review.coreboot.org/c/coreboot/+/49849/comment/ba225b1c_d2549cf0 PS4, Line 21: if !XEON_SP_COMMON_BASE > SERVER/CLIENT distinction would be a good starting point. […] We could at least add a SERVER group for this patch. It would make this a little cleaner. Since this has been mostly used by mobile, it would be good to get some input and help from the *lake developers. -- To view, visit https://review.coreboot.org/c/coreboot/+/49849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Gerrit-Change-Number: 49849 Gerrit-PatchSet: 4 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 14:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Lockdown SPI BIOS controls
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51227 ) Change subject: soc/intel/xeon_sp: Lockdown SPI BIOS controls ...................................................................... soc/intel/xeon_sp: Lockdown SPI BIOS controls Lockdown SPI based on Intel BWG recommendation. Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51227/1 diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 0e21680..7e8cbd6 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -1,11 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> +#include <device/pci_ops.h> #include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> +#include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/spi.h> + +static void spi_set_bios_interface_lock_down(void) +{ + uint8_t bc_cntl; + + bc_cntl = pci_read_config8(PCH_DEV_SPI, BIOS_SPI_BC); + bc_cntl |= SPI_BC_LE | SPI_BC_EISS; + pci_write_config8(PCH_DEV_SPI, BIOS_SPI_BC, bc_cntl); + + /* Read back after performing lock down */ + pci_read_config8(PCH_DEV_SPI, BIOS_SPI_BC); +} + +static void spi_lockdown_config(int chipset_lockdown) +{ + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + spi_set_bios_interface_lock_down(); + } +} static void lpc_lockdown_config(int chipset_lockdown) { @@ -51,6 +74,9 @@ /* LPC lock down configuration */ lpc_lockdown_config(chipset_lockdown); + /* LPC lock down configuration */ + spi_lockdown_config(chipset_lockdown); + /* PMC lock down configuration */ pmc_lockdown_config(chipset_lockdown); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6999b7ad17615b8390f6c7b3d0a874e58bccc481 Gerrit-Change-Number: 51227 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Set SMI lock
by Marc Jones (Code Review) 03 Mar '21

03 Mar '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51226 ) Change subject: soc/intel/xeon_sp: Set SMI lock ...................................................................... soc/intel/xeon_sp: Set SMI lock Prevent writes to Global SMI enable as recommended by the BWG. Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/51226/1 diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 2fa53c9..0e21680 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -16,7 +16,19 @@ } } -static void pmc_lockdown_config(void) +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void pmc_lockdown_config(int chipset_lockdown) { uint8_t *pmcbase; u32 pmsyncreg; @@ -29,6 +41,9 @@ /* Make sure payload/OS can't trigger global reset */ pmc_global_reset_disable_and_lock(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); } void soc_lockdown_config(int chipset_lockdown) @@ -37,5 +52,5 @@ lpc_lockdown_config(chipset_lockdown); /* PMC lock down configuration */ - pmc_lockdown_config(); + pmc_lockdown_config(chipset_lockdown); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418 Gerrit-Change-Number: 51226 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/hda: Use azalia device code
by Patrick Rudolph (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50795 to look at the new patch set (#4). Change subject: soc/intel/common/block/hda: Use azalia device code ...................................................................... soc/intel/common/block/hda: Use azalia device code The code is already compiled in on all platforms. Use it as it provides the same functionality. Tested on Prodrive hermes: Still detects and initializes both codecs. Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/Kconfig.common M src/soc/intel/common/block/hda/hda.c 2 files changed, 7 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/50795/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31 Gerrit-Change-Number: 50795 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/azalia: Add support for writing GCAP
by Patrick Rudolph (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50794 to look at the new patch set (#4). Change subject: device/azalia: Add support for writing GCAP ...................................................................... device/azalia: Add support for writing GCAP Starting with Intel 6 Series PCH the GCAP is RW/ONCE. Add a helper function to write it after resetting the codec. Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/azalia_device.c M src/include/device/azalia_device.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50794/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Gerrit-Change-Number: 50794 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/azalia_device: Fix STATESTS register and add defines
by Patrick Rudolph (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50790 to look at the new patch set (#3). Change subject: device/azalia_device: Fix STATESTS register and add defines ...................................................................... device/azalia_device: Fix STATESTS register and add defines The STATESTS register is 16bits and supports up to 15 codecs. Add a new Kconfig for the maximum codec count and use it instead of the arbitrary choosen 32bit register size and maximum of 3 codecs. Fixes codec detection timeout seen on Intel PCH 200-Series. See "HDA Spec Rev. 1.0" for reference. Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig M src/device/azalia_device.c M src/include/device/azalia_device.h 3 files changed, 24 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/50790/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Gerrit-Change-Number: 50790 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Add log_level that can be overridden for SMM log level
by Johnny Lin (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Marc Jones, Patrick Rudolph, Jonathan Zhang, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Add log_level that can be overridden for SMM log level ...................................................................... Patch Set 5: (1 comment) File src/cpu/x86/smm/smm_module_loaderv2.c: https://review.coreboot.org/c/coreboot/+/49460/comment/197e26da_f3cbf946 PS4, Line 613: if (CONFIG(CONSOLE_OVERRIDE_LOGLEVEL)) { > How about always passing the ramstage loglevel, with an override possible if CONSOLE_OVERRIDE_LOGLEV […] Do you mean always assign it from get_smm_loglevel()? handler_mod_params->log_level = get_smm_loglevel(); and remove all the #if (CONFIG(CONSOLE_OVERRIDE_LOGLEVEL)) guards in this change? But I still need to keep the __weak function to provide default implementation to avoid build error. I think to be able to set SMM loglevel at runtime still requires to select CONSOLE_OVERRIDE_LOGLEVEL. -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 13:24:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50754/comment/479a65f0_54ab37af PS5, Line 23: Tested Needs re-test File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/50754/comment/249681ad_dd1f1793 PS3, Line 388: fast_spi_clear_smi > That doesn't answer the question. […] Ah, that's what you meant... I'll need to test. Maybe this is why I get two SMIs in a row. -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 13:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021