coreboot-gerrit March 2021

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Change in coreboot[master]: soc/intel/apollolake: Add `GPE0_STS_BIT` macro
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50916 ) Change subject: soc/intel/apollolake: Add `GPE0_STS_BIT` macro ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/apollolake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/50916/comment/3e3fa791_4913f5f5 PS1, Line 111: GPE0_STS_BIT > Not the best at it, but I can give it a try :P: […] I've done something else so that common code doesn't need to know that this bit is actually reserved. Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/50916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Gerrit-Change-Number: 50916 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 03 Mar 2021 11:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50750 to look at the new patch set (#6). Change subject: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode ...................................................................... soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/50750/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/50750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Gerrit-Change-Number: 50750 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake: Add `GPE0_STS_BIT` macro
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Andrey Petrov, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50916 to look at the new patch set (#3). Change subject: soc/intel/apollolake: Add `GPE0_STS_BIT` macro ...................................................................... soc/intel/apollolake: Add `GPE0_STS_BIT` macro The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/50916/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Gerrit-Change-Number: 50916 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/azalia_device: Fix STATESTS register and add defines
by Patrick Rudolph (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50790 ) Change subject: device/azalia_device: Fix STATESTS register and add defines ...................................................................... Patch Set 2: (1 comment) File src/include/device/azalia_device.h: https://review.coreboot.org/c/coreboot/+/50790/comment/7f0c5f3d_1f01bac0 PS2, Line 16: HDA_MAX_CODECS > Is this limit chipset-specific? If so, I'd turn it into a Kconfig option and derive the HDA_CODEC_MA […] It is, will turn it into a Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/50790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Gerrit-Change-Number: 50790 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 11:11:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST]mb/google/zork/variants/vilboz: Adjust phy driving to fix WWAN ...
by John Su (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: chris wang. Hello chris wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51225 to look at the new patch set (#2). Change subject: [TEST]mb/google/zork/variants/vilboz: Adjust phy driving to fix WWAN noise ...................................................................... [TEST]mb/google/zork/variants/vilboz: Adjust phy driving to fix WWAN noise Adjust phy driving to fix WWAN noise. BUG=b:171269338 BRANCH=zork TEST=Check COMMON_MAR_DEEMPH_NOM register and no noise Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I672a001a312e9142c213d463670e1ac825d17299 --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51225/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I672a001a312e9142c213d463670e1ac825d17299 Gerrit-Change-Number: 51225 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [TEST]mb/google/zork/variants/vilboz: Override phy driving to fix the...
by John Su (Code Review) 03 Mar '21

03 Mar '21

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51225 ) Change subject: [TEST]mb/google/zork/variants/vilboz: Override phy driving to fix the eDP noise ...................................................................... [TEST]mb/google/zork/variants/vilboz: Override phy driving to fix the eDP noise Override phy driving to fix th eDP noise for WWAN. BUG=b:171269338 BRANCH=zork TEST=Check COMMON_MAR_DEEMPH_NOM register and no noise Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I672a001a312e9142c213d463670e1ac825d17299 --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51225/1 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 3816aac..daf84e5 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -40,8 +40,18 @@ soc_cfg = config_of_soc(); /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ - if (variant_has_wwan()) + if (variant_has_wwan()) { soc_cfg->acp_i2s_use_external_48mhz_osc = 1; + + /* b:171269338 Improve WWAN noise floor to + adjust the phy driving setting */ + soc_cfg->edp_phy_override = ENABLE_EDP_TUNINGSET; + soc_cfg->edp_physel = 0x1; + soc_cfg->edp_tuningset.dp_vs_pemph_level = 0x1; + soc_cfg->edp_tuningset.margin_deemph = 0x004b; + soc_cfg->edp_tuningset.deemph_6db4 = 0x0; + soc_cfg->edp_tuningset.boostadj = 0x80; + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/51225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I672a001a312e9142c213d463670e1ac825d17299 Gerrit-Change-Number: 51225 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/azalia_device: Fix STATESTS register and add defines
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50790 ) Change subject: device/azalia_device: Fix STATESTS register and add defines ...................................................................... Patch Set 2: (1 comment) File src/include/device/azalia_device.h: https://review.coreboot.org/c/coreboot/+/50790/comment/dde2856b_bc0c08f0 PS2, Line 16: HDA_MAX_CODECS Is this limit chipset-specific? If so, I'd turn it into a Kconfig option and derive the HDA_CODEC_MASK macro from that Kconfig option. -- To view, visit https://review.coreboot.org/c/coreboot/+/50790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Gerrit-Change-Number: 50790 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:51:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/azalia: Add support for writing GCAP
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50794 ) Change subject: device/azalia: Add support for writing GCAP ...................................................................... Patch Set 3: (1 comment) File src/device/azalia_device.c: https://review.coreboot.org/c/coreboot/+/50794/comment/bea1e152_d22cf5d8 PS3, Line 274: find_resource probe_resource -- To view, visit https://review.coreboot.org/c/coreboot/+/50794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Gerrit-Change-Number: 50794 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:49:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/azalia: Switch to stopwatch
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Mike Banon, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50789 ) Change subject: device/azalia: Switch to stopwatch ...................................................................... Patch Set 2: (2 comments) File src/device/azalia_device.c: https://review.coreboot.org/c/coreboot/+/50789/comment/6a7a0adc_51f701e6 PS2, Line 178: udelay(1); > The CFL FSP doesn't have this delay. Since this code is primarily used by AMD boards, it would be nice to have someone test that HDA still works there. https://review.coreboot.org/c/coreboot/+/50789/comment/5a9f1dc3_b2df32c1 PS2, Line 174: stopwatch_init_usecs_expire(&sw, 50); > CFL FSP uses 10msec for iGPU here and 1msec for regular HDA codecs. Do we ever hit the timeout? We could make the timeout delays configurable, too. Maybe also log an error if a function times out? -- To view, visit https://review.coreboot.org/c/coreboot/+/50789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a Gerrit-Change-Number: 50789 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:47:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/i2c/rx6110sa: Add official ACPI ID
by Paul Menzel (Code Review) 03 Mar '21

03 Mar '21

Attention is currently required from: Andy Shevchenko, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51176 ) Change subject: src/drivers/i2c/rx6110sa: Add official ACPI ID ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51176/comment/49455554_f005b334 PS1, Line 9: wrong > Ack No idea. ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/51176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45838162f014a760520692c6dcaae329ad98547d Gerrit-Change-Number: 51176 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Reviewer: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Shevchenko <andy.shevchenko(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 10:36:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021