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Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
soc/intel/common: Prevent SMI storm when setting SPI WPD bit
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMM handler, which results in a deadlock.
Avoid deadlocks by clearing the SPI status bits in the SMM handler. This
patch does not handle eSPI because I cannot test it, and knowing whether
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).
Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS
write protection. However, write protection is still not being enforced.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/5
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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/6da30c3d_214a647c
PS3, Line 388: fast_spi_clear_smi
> do you need to clear SMI_STS. […]
By the time `smihandler_southbridge_tco` is invoked, SMI_STS.TCO_STS has already been cleared
https://review.coreboot.org/c/coreboot/+/50754/comment/a9143b97_8c6d5c75
PS3, Line 451: smi_sts = pmc_clear_smi_status();
SMI_STS.TCO_STS gets cleared here.
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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/feb62527_b0963ecf
PS3, Line 393: SPI_BIOS_CONTROL
> check if bit8 is set. If it's not this function will accidently enable SMI on write protect disable.
How would this happen?
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49683 )
Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6:
I would suggest call the file like variant.c not romstage.c :p
File src/mainboard/google/zork/variants/vilboz/romstage.c:
https://review.coreboot.org/c/coreboot/+/49683/comment/22b3692e_88b6a772
PS6, Line 3: #include <baseboard/variants.h>
please remove unused header.
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/zork/romstage.c:
https://review.coreboot.org/c/coreboot/+/51181/comment/d1c9da63_0e47a1fe
PS2, Line 3: #include <baseboard/variants.h>
please remove the unused header.
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Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/zork/variants/vilboz/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/51181/comment/eb956020_d4f51f4b
PS2, Line 5: romstage-y += romstage.c
this should be in another CL.
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Change subject: mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
You need add this into makefile
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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/124a73ec_4dc7efaf
PS3, Line 393: SPI_BIOS_CONTROL
check if bit8 is set. If it's not this function will accidently enable SMI on write protect disable.
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/1e84ce88_59995396
PS3, Line 388: fast_spi_clear_smi
do you need to clear SMI_STS.TCO_STS after this call?
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Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50754
to look at the new patch set (#4).
Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
soc/intel/common: Prevent SMI storm when setting SPI WPD bit
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMM handler, which results in a deadlock.
Avoid deadlocks by clearing the SPI status bits in the SMM handler. This
patch does not handle eSPI because I cannot test it, and knowing whether
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).
Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS
write protection. However, write protection is still not being enforced.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/4
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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
Patch Set 3:
(4 comments)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/c84a0283_3d3c5dcb
PS1, Line 398: fast_spi_enable_wp
> I can't find that document. Is it public? […]
Ack
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/da1308c1_bbbe9507
PS1, Line 363: if (fast_spi_wpd_status()) {
> if possible you shouldn't touch wpd in this commit at all. only reset the SMI status bits to prevent SMI storm.
Done
https://review.coreboot.org/c/coreboot/+/50754/comment/f4c41a4f_56060dbf
PS1, Line 368: uint16_t bios_cntl = pci_read_config16(PCH_DEV_LPC, 0xdc);
> Regarding LPC, even if CB:40830 doesn't enable protection, I guess it doesn't hurt to handle BIOSWR_ […]
eSPI is not handled in this patch. I don't have a board with eSPI to test things on and the SOC_ESPI Kconfig option is specific to APL.
https://review.coreboot.org/c/coreboot/+/50754/comment/f2b78e68_9371c5a5
PS1, Line 368: PCH_DEV_LPC
> SPI_SYNC_SS clearing (discussed above) must also be done on eSPI (but not LPC). […]
eSPI is not handled in this patch. (see above comment for reasoning)
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