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Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50210 )
Change subject: drivers/i2c: sx9310: Replace register map with descriptive names
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50210/comment/75b233a1_a2a6a9f4
PS4, Line 7: drivers/i2c: sx9310: Use open source variables
> Maybe: […]
Done
File src/drivers/i2c/sx9310/registers.h:
https://review.coreboot.org/c/coreboot/+/50210/comment/835b41a4_e0fe9154
PS4, Line 7: reg_prox_ctrl0
> Another board needs to be fixed along with this: nocturne (https://qa.coreboot. […]
Done
File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/50210/comment/3bd7f8d0_851dc461
PS4, Line 158: -
> _ instead of - […]
Done
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50210
to look at the new patch set (#5).
Change subject: drivers/i2c: sx9310: Replace register map with descriptive names
......................................................................
drivers/i2c: sx9310: Replace register map with descriptive names
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/…
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org>
---
M src/drivers/i2c/sx9310/chip.h
D src/drivers/i2c/sx9310/registers.h
M src/drivers/i2c/sx9310/sx9310.c
M src/mainboard/google/hatch/variants/hatch/overridetree.cb
M src/mainboard/google/hatch/variants/mushu/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/volteer/variants/halvor/overridetree.cb
M src/mainboard/google/volteer/variants/malefor/overridetree.cb
M src/mainboard/google/volteer/variants/trondo/overridetree.cb
M src/mainboard/google/volteer/variants/volteer/overridetree.cb
M src/mainboard/google/volteer/variants/volteer2/overridetree.cb
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
12 files changed, 159 insertions(+), 247 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/50210/5
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51197 )
Change subject: [WIP] vc/amd/cezanne: add platform_Descriptors.c
......................................................................
Patch Set 2:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/2e3f34fe_3248fd2c
PS2, Line 128: * Cezanne DXIO logical lane to physical PCIe lane mapping:
to make review a bit easier: this is in "Figure 51: SERDES Configuration" from the nbio/pcie chapter of the ppr
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Change subject: [WIP] vc/amd/cezanne: add platform_Descriptors.c
......................................................................
Patch Set 2:
(2 comments)
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/16b8c76d_d18c2cc7
PS2, Line 108: EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init
i'm not 100% sure about this and the next 3
https://review.coreboot.org/c/coreboot/+/51197/comment/b8d594c7_faa11a3a
PS2, Line 159: Currently unused by FSP
will those be used or not? i think at first we'll use them, but will end up removing the functionality from fsp, since coreboot can do that itself
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Change subject: mb/google/volteer: Configure tcss port information for early tcss init
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/51195/comment/058f9f4a_40a9264c
PS1, Line 182: mux_info
> I think you can still set the MAX_TYPE_C_PORTS to 4 and return num_ports based on what get_connector […]
Done
https://review.coreboot.org/c/coreboot/+/51195/comment/a1af89ae_efc46ecb
PS1, Line 186: get_connector_config
> Yeah that makes more sense then fetching all the devices should save some time only fetching them on […]
Done
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Felix Held has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/51197 )
Change subject: [WIP] vc/amd/cezanne: add platform_Descriptors.c
......................................................................
[WIP] vc/amd/cezanne: add platform_Descriptors.c
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474
---
A src/vendorcode/amd/fsp/cezanne/platform_descriptors.h
1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/51197/2
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Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51194/comment/0129be51_49cd7d6e
PS1, Line 12: the ports are not initialized till the ports are set to the appropriate mode.
> In addition to setting the muxes to disconnected state, early_tcss driver is also setting up the por […]
Done
File src/soc/intel/tigerlake/early_tcss.c:
https://review.coreboot.org/c/coreboot/+/51194/comment/29e58ec8_30e656ae
PS1, Line 322: mainboard_tcss_get_port_info
> it is acpi specific and I hate to abstract it out and create additional weirdness it also seems to b […]
Done
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Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51194
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3 devices
to downgrade to USB2 speed. To properly configure the Type C ports the muxes
should be set to disconnected state during boot so that the port mapping of
USB2/3 devices is properly setup prior to Kernel initializing devices.
BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple times
to verify that the devices were no longer downgrading to USB2 speed.
Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/early_tcss.c
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/early_tcss.h
4 files changed, 78 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/3
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Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3 devices
to downgrade to USB2 speed. To properly configure the Type C ports the muxes
should be set to disconnected state during boot so that devices connected on
the ports are not initialized till the ports are set to the appropriate mode.
BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple times
to verify that the devices were no longer downgrading to USB2 speed.
Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/early_tcss.c
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/early_tcss.h
4 files changed, 78 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/2
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