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Change in coreboot[master]: [WIP] vc/amd/cezanne: add platform_Descriptors.c
by Felix Held (Code Review) 02 Mar '21

02 Mar '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51197 ) Change subject: [WIP] vc/amd/cezanne: add platform_Descriptors.c ...................................................................... [WIP] vc/amd/cezanne: add platform_Descriptors.c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 --- A src/vendorcode/amd/fsp/cezanne/platform_descriptors.h 1 file changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/51197/1 diff --git a/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h new file mode 100644 index 0000000..69125c6 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H +#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* Upstream Auto Speed Change Allowed */ +typedef enum { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISBLED, + SPDC_ENABLED, + SPDC_INVALID +} dxio_upstream_auto_speed_change; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4_GFX, + CLK_REQ5, + CLK_REQ6, + /* 0x08 is invalid */ + CLK_GPP_REQ0 = 0x09, + CLK_GPP_REQ1, + CLK_GPP_REQ2, + CLK_GPP_REQ3, + CLK_GPP_REQ4, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1 = 0, + AUX2, + AUX3, + AUX4, + AUX5, + AUX6, + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1 = 0, + HDP2, + HDP3, + HDP4, + HDP5, + HDP6, + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP = 0, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* Cezanne DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* + * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, + * configure bifurcation and other settings. Beware that the lane numbers in + * here are the logical and not the physical lane numbers! + * + * Cezanne DXIO logical lane to physical PCIe lane mapping: + * + * logical | FT6 | AM4 + * --------|------------|---------------------- + * [00:03] | GPP[00:03] | GPP[00:03] + * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] + * [08:11] | GPP[08:11] | GFX[15:12] + * [12:15] | n/a | GFX[11:08] + * [16:23] | GFX[00:07] | GFX[07:0] + * + * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 + * platform additionally supports mapping lanes 8 and 9 to a SATA controller. + * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet + * controllers. + */ +typedef struct __packed { + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // Currently unused by FSP + uint8_t port_present :1; // Should be TRUE if train link + uint8_t reserved_3 :7; + uint8_t device_number :5; // Desired root port device number + uint8_t function_number :3; // Desired root port function number + uint8_t link_speed_capability :2; // See dxio_link_speed_cap + uint8_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint8_t eq_preset :4; // Gen3 equalization preset + uint8_t link_aspm :2; // See dxio_aspm_type + uint8_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint8_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint8_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint8_t slot_power_limit_scale :2; // Currently unused by FSP + uint8_t reserved_4 :6; + uint8_t link_compliance_mode :1; // Currently unused by FSP + uint8_t link_safe_mode :1; // Currently unused by FSP + uint8_t sb_link :1; // Currently unused by FSP + uint8_t clk_pm_support :1; // Currently unused by FSP + uint8_t channel_type :3; // See dxio_sata_channel_type + uint8_t turn_off_unused_lanes :1; // Power down lanes if device not present + uint8_t reserved[4]; +} fsp_dxio_descriptor; + +#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Gerrit-Change-Number: 51197 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51194 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that the devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 4 files changed, 78 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 3 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Configure tcss port information for early tcss init
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Brandon Breitenstein. Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51195 to look at the new patch set (#2). Change subject: mb/google/volteer: Configure tcss port information for early tcss init ...................................................................... mb/google/volteer: Configure tcss port information for early tcss init Implement the mainboard_tcss_get_port_info weak function so that the TCSS muxes can be properly configured to ensure mapping is correct in mux. This ensures that any devices that are connected during boot are not improperly configured by the Kernel. BUG=b:180426950 BRANCH=firmare-volteer-13672.B TEST= Verified that the SOC code that initialized TCSS muxes to disconnect mode is executing properly for all TCSS ports and verified that USB3 devices are no longer downgrading to USB2 speed if connected during boot. Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51195/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Gerrit-Change-Number: 51195 Gerrit-PatchSet: 2 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51194 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that devices connected on the ports are not initialized till the ports are set to the appropriate mode. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that the devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 4 files changed, 78 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 2 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add support for 2 new DRAM parts
by Amanda Hwang (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Ivy Jian. Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51170 ) Change subject: mb/google/brya: Add support for 2 new DRAM parts ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51170/comment/f7e327b6_2f8b0e3c PS1, Line 7: mb/google/brya: Add DRAM support for Micron MT53E1G32D2NP-046 and MT53E2G32D4NQ-046 > suggestion: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Gerrit-Change-Number: 51170 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 01:02:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add support for 2 new DRAM parts
by Amanda Hwang (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Amanda Hwang, Ivy Jian. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Ivy Jian, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51170 to look at the new patch set (#2). Change subject: mb/google/brya: Add support for 2 new DRAM parts ...................................................................... mb/google/brya: Add support for 2 new DRAM parts 1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/memory/Makefile.inc M src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/51170/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Gerrit-Change-Number: 51170 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update telemetry settings
by Kangheui Won (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Frank Wu, John Su, Martin Roth, Chris Wang, Rob Barnes. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51165 ) Change subject: mb/google/zork/var/vilboz: Update telemetry settings ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec Gerrit-Change-Number: 51165 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 00:48:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz
by Kangheui Won (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Frank Wu, Furquan Shaikh, Martin Roth, EricR Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51171 ) Change subject: mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2 Gerrit-Change-Number: 51171 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 00:47:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/storo: Add camera support
by Andy Yeh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, zanxi chen, Paul Menzel, Weimin Wu, Andy Yeh, Karthik Ramasubramanian. Andy Yeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50995 ) Change subject: mb/google/dedede/var/storo: Add camera support ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Even if camera EEPROM is going to be provisioned later, I would like SSFC in CBI to be provisioned n […] In that case, these CLs (could be referred) need be landed. https://review.coreboot.org/c/coreboot/+/45172 https://review.coreboot.org/c/coreboot/+/50261 (Private now - can you access?) https://review.coreboot.org/c/coreboot/+/45445 CBI could set as in the end of 32bit FW_CONFIG. 1. WFC - 3 bit (0: none-MIPI; 1: Kingcome 8MP; 2: TBD 2. UFC - 2 bit (0: none-MIPI) --> 0 since UFC is USB. However, we should take Maglia as higher priority (not clarified yet). And leverage the same approach to Storo by copying exactly as its schedule is later. Karthik, Henry, What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/50995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc Gerrit-Change-Number: 50995 Gerrit-PatchSet: 2 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Mar 2021 00:29:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Henry Sun <henrysun(a)google.com> Comment-In-Reply-To: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Andy Yeh <andy.yeh(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Configure tcss port information for early tcss init
by Furquan Shaikh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Chiranjeevi Rapolu, Tim Wawrzynczak, John Zhao, Duncan Laurie, Brandon Breitenstein. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51195 ) Change subject: mb/google/volteer: Configure tcss port information for early tcss init ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/51195/comment/5725b378_a9b2217e PS1, Line 182: mux_info > My only thing with this is how would we define MAX_TYPE_C_PORTS? for TGL that is 4 but we are only u […] I think you can still set the MAX_TYPE_C_PORTS to 4 and return num_ports based on what get_connector_config returns. It is not too bad if you restrict MAX_TYPE_C_PORTS in volteer to 2 since all volteer boards will just use upto a maximum of 2 type-C ports. It wouldn't impact any other TGL-based board. -- To view, visit https://review.coreboot.org/c/coreboot/+/51195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Gerrit-Change-Number: 51195 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 23:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2021