coreboot-gerrit March 2021

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Change in coreboot[master]: mb/google/volteer: Configure tcss port information for early tcss init
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51195 ) Change subject: mb/google/volteer: Configure tcss port information for early tcss init ...................................................................... mb/google/volteer: Configure tcss port information for early tcss init Implement the mainboard_tcss_get_port_info weak function so that the TCSS muxes can be properly configured to disconnect mode during boot. This ensures that any devices that are connected during boot are not improperly configured by the Kernel. BUG=b:180426950 BRANCH=firmare-volteer-13672.B TEST= Verified that the SOC code that initialized TCSS muxes to disconnect mode is executing properly for all TCSS ports and verified that USB3 devices are no longer downgrading to USB2 speed if connected during boot. Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51195/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index ddfd704..9603059 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -16,6 +16,7 @@ select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_USB_ACPI + select EARLY_TCSS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index e8b3466..be6a92d 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -10,6 +10,7 @@ #include <gpio.h> #include <intelblocks/gpio.h> #include <security/tpm/tss.h> +#include <soc/early_tcss.h> #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -141,6 +142,60 @@ } } +static bool is_correct_port(const struct device *dev, int port) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port + && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static const struct drivers_intel_pmc_mux_conn_config *get_connector_config(int port) +{ + const struct drivers_intel_pmc_mux_conn_config *config = NULL; + const struct device *pmc = NULL; + const struct device *mux = NULL; + DEVTREE_CONST struct device *conn = NULL; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list->children) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return NULL; + } + + + /* + * Find specified port underneath PMC.MUX; If the port is not found return and + * print out error statement. + */ + mux = pmc->link_list->children; + while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) { + if (is_correct_port(conn, port)) + break; + } + + if (conn) + config = (const struct drivers_intel_pmc_mux_conn_config *) + conn->chip_info; + + return config; +} + +unsigned int mainboard_tcss_get_port_info(struct tcss_mux *mux_info) +{ + int port = 0; + const struct drivers_intel_pmc_mux_conn_config *mux_config; + while ((mux_config = get_connector_config(port)) != NULL) { + struct tcss_mux mux_data; + mux_data.usb2_port = mux_config->usb2_port_number; + mux_data.usb3_port = mux_config->usb3_port_number; + + mux_info[port] = mux_data; + port++; + } + + /* return port as number of ports */ + return port; +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; -- To view, visit https://review.coreboot.org/c/coreboot/+/51195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Gerrit-Change-Number: 51195 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
by Brandon Breitenstein (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Patrick Rudolph. Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51194 ) Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot ...................................................................... soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that devices connected on the ports are not initialized till the ports are set to the appropriate mode. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that the devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 4 files changed, 67 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index bf204f5..c1c5aca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -244,6 +244,11 @@ help Enable displays to be detected over Type-C ports during boot. +config EARLY_TCSS + bool "Enable early TCSS device Init" + help + Enables TCSS to initialize devices before Kernel. + config DATA_BUS_WIDTH int default 128 diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c index 8616bb1..ff87be8 100644 --- a/src/soc/intel/tigerlake/early_tcss.c +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -104,6 +104,29 @@ return -1; } +static int send_pmc_disconnect_request(int port, struct tcss_mux mux_data, + struct pmc_ipc_buffer *res) +{ + uint32_t cmd; + struct pmc_ipc_buffer req = { 0 }; + + cmd = tcss_make_conn_cmd( + PMC_IPC_TCSS_DISC_REQ_RES, + mux_data.usb3_port, + mux_data.usb2_port, + 0, 0, 0, 0); + + req.buf[0] = cmd; + + printk(BIOS_DEBUG, "port C%d DISC req: usage %d usb3 %d usb2 %d\n", + port, + GET_TCSS_CD_FIELD(USAGE, cmd), + GET_TCSS_CD_FIELD(USB3, cmd), + GET_TCSS_CD_FIELD(USB2, cmd)); + + return send_pmc_req(CONNECT_REQ, &req, res, PMC_IPC_DISC_REQ_SIZE); +} + static int send_pmc_connect_request(int port, struct tcss_mux mux_data, struct pmc_ipc_buffer *res) { @@ -241,6 +264,16 @@ return 0; } +static void initialize_mux_to_disc_mode(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *rbuf = NULL; + int ret = 0; + + ret = send_pmc_disconnect_request(port, mux_data, rbuf); + if (ret) + printk(BIOS_ERR, "Failed to setup port:%d to inial state\n", port); +} + static void update_tcss_mux(int port, struct tcss_mux mux_data) { struct pmc_ipc_buffer *rbuf = NULL; @@ -268,7 +301,7 @@ static int system_requires_early_display(void) { - if (!CONFIG(VBOOT)) + if (!CONFIG(VBOOT) || !CONFIG(EARLY_TCSS_DISPLAY)) return 1; else if (vboot_recovery_mode_enabled() || vboot_developer_mode_enabled()) return 1; @@ -286,14 +319,28 @@ if (!system_requires_early_display()) return; - mainboard_early_tcss_enable(mux_info, &num_ports); + num_ports = mainboard_tcss_get_port_info(mux_info); + + for (i = 0; i < num_ports; i++) + initialize_mux_to_disc_mode(i, mux_info[i]); + + /* If early display is not supported end with setting ports to disconnect */ + if (!system_requires_early_display()) + return; + + num_ports = mainboard_tcss_fill_mux_info(mux_info); for (i = 0; i < num_ports; i++) update_tcss_mux(i, mux_info[i]); } -__weak void mainboard_early_tcss_enable(struct tcss_mux *mux_info, unsigned int *num_ports) +__weak unsigned int mainboard_tcss_fill_mux_info(struct tcss_mux *mux_info) { - /* to be overwritten by each mainboard that needs early tcss */ + /* to be overwritten by each mainboard that needs early tcss display */ +} + +__weak unsigned int mainboard_tcss_get_port_info(struct tcss_mux *mux_info) +{ + /* to be overwritten by each mainboard that needs tcss ports configured */ } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c5501b7..1d57002 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -462,7 +462,7 @@ /* TCSS specific initialization here */ printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", __FILE__, __func__); - if (CONFIG(EARLY_TCSS_DISPLAY)) + if (CONFIG(EARLY_TCSS)) tcss_early_configure(); break; default: diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h index cee4c12..0a0d957 100644 --- a/src/soc/intel/tigerlake/include/soc/early_tcss.h +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -5,10 +5,12 @@ #define PMC_IPC_USBC_SUBCMD_ID 0x0 #define PMC_IPC_CMD 0x0 #define PMC_IPC_TCSS_CONN_REQ_RES 0x0 +#define PMC_IPC_TCSS_DISC_REQ_RES 0x1 #define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2 #define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3 #define PMC_IPC_TCSS_HPD_REQ_RES 0x4 #define PMC_IPC_CONN_REQ_SIZE 2 +#define PMC_IPC_DISC_REQ_SIZE 2 #define PMC_IPC_ALT_REQ_SIZE 8 #define PMC_IPC_SAFE_REQ_SIZE 1 #define PMC_IPC_HPD_REQ_SIZE 2 @@ -138,4 +140,11 @@ * must be overridden by the mainboard with its specific mux data stored in a struct tcss_mux * struct as defined above. */ -void mainboard_early_tcss_enable(struct tcss_mux *mux_info, unsigned int *num_ports); +unsigned int mainboard_tcss_fill_mux_info(struct tcss_mux *mux_info); + +/* + * Weak mainboard method to get only the port information to initialize the muxes to + * disconnect mode during boot. + * returns total number of ports. + */ +unsigned int mainboard_tcss_get_port_info(struct tcss_mux *mux_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/51194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Gerrit-Change-Number: 51194 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd_blobs: update submodule pointer
by Marshall Dawson (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Nikolai Vyssotski, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51193 ) Change subject: amd_blobs: update submodule pointer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Gerrit-Change-Number: 51193 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Mar 2021 22:03:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by Furquan Shaikh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50897 ) Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... Patch Set 9: Code-Review+1 (1 comment) Patchset: PS9: Looks okay to me. Let's see if others have any comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 22:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Disable legacy DMA IO ports
by Marshall Dawson (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Paul Menzel, Angel Pons, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51076 ) Change subject: soc/amd/cezanne: Disable legacy DMA IO ports ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694 Gerrit-Change-Number: 51076 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Mar 2021 22:00:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd_blobs: update submodule pointer
by Nikolai Vyssotski (Code Review) 02 Mar '21

02 Mar '21

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51193 ) Change subject: amd_blobs: update submodule pointer ...................................................................... amd_blobs: update submodule pointer Pick up build 0x26 Picasso FSP binaries. The changes include increased FSPS UPD block size from 0x152 to 0x202. Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/51193/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 302c9f6..3b1a734 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 302c9f61488b2117f5315e4094ec044cc8ceb0ea +Subproject commit 3b1a73470c4fe89195922b693232614fe279ca55 -- To view, visit https://review.coreboot.org/c/coreboot/+/51193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Gerrit-Change-Number: 51193 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by Cliff Huang (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50897 ) Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50897/comment/69e6b33b_241ebb4e PS6, Line 357: CnviBtCore > Rather than silently updating the config silently, what do you think about asserting if the mainboar […] good point. built/tested/committed. -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 21:31:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/tigerlake: Add Acoustic features
by Furquan Shaikh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Shaunak Saha, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50870 ) Change subject: intel/tigerlake: Add Acoustic features ...................................................................... Patch Set 3: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50870/comment/bd7c4345_5541cc20 PS3, Line 24: Can you also please mention here that TGL has a single VR domain(Vccin)? Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. Patchset: PS3: Thanks Shaunak! -- To view, visit https://review.coreboot.org/c/coreboot/+/50870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Gerrit-Change-Number: 50870 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 21:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by Cliff Huang (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Wonkyu Kim, Selma Bensaid, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50897 to look at the new patch set (#9). Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50897/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: fix BT enumeration issue
by Tim Wawrzynczak (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Aamir Bohra. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51178 ) Change subject: mb/google/brya: fix BT enumeration issue ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Gerrit-Change-Number: 51178 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 20:32:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2021