coreboot-gerrit March 2021

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Change in coreboot[master]: MAINTAINERS: Add Jakub as maintainer for tests/
by Jan Dabros (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: jacz(a)semihalf.com. Jan Dabros has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51189 ) Change subject: MAINTAINERS: Add Jakub as maintainer for tests/ ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10 Gerrit-Change-Number: 51189 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jacz(a)semihalf.com Gerrit-Attention: jacz(a)semihalf.com Gerrit-Comment-Date: Tue, 02 Mar 2021 18:05:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: elog: Support logging CSE Lite info in elog
by Furquan Shaikh (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Martin Roth, Jamie Ryu, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50472 ) Change subject: elog: Support logging CSE Lite info in elog ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50472/comment/3a08762d_a92cd940 PS6, Line 25: 2 | 2021-01-21 08:46:18 | CSE Info | Lite | 13.50.0.1269 | 13.50.0.1269 : | YES | 0x5 | 0x3 | RO : 3 | 2021-01-21 08:46:21 | CSE Info | Lite | 13.50.0.1269 | 13.50.0.1269 : | YES | 0x5 | 0x0 | RW > To move logging cse lite info in ramstage would require us to move heci command implementations to c […] If we move System boot to happen before romstage, I think the timeline would look much better. Something like: 0 | ... | System boot | xxxx 1 | ... | CSE Info | Lite | a.b.c.d | a.b.c.d | YES | 0x5 | 0x3 | RO 2 | ... | System boot | xxxy 3 | ... | CSE Info | Lite | a.b.c.d | a.b.c.d | YES | 0x5 | 0x3 | RW 4 | ... BTW, I am not sure what "YES" really means. Anyways, since it is related to displaying info only, we can address that in the mosys CL. https://review.coreboot.org/c/coreboot/+/50472/comment/86132448_d88de8e3 PS6, Line 29: 4 | 2021-01-21 08:46:25 | System boot | 3098 > Can we move "System boot" event log to romstage? or can we have the timeline in this order ? […] Moving system boot to romstage or even bootblock sounds okay to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/50472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib183941d1fa0a9971e30b4092ea3d23daaa29334 Gerrit-Change-Number: 50472 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 18:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Fix logging
by Arthur Heymans (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Patrick Rudolph, Christian Walter. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51100 ) Change subject: security/intel/txt: Fix logging ...................................................................... Patch Set 1: (1 comment) File src/security/intel/txt/txt_register.h: https://review.coreboot.org/c/coreboot/+/51100/comment/6aec6bf2_1e976b59 PS1, Line 29: ACMERROR_TXT_PROGRESS_SHIFT > now progress and minor overlap I don't have any document saying something about progress code. Mine says it's either ACM started or not; or the source: MLE or ACM. Can we get rid of it? -- To view, visit https://review.coreboot.org/c/coreboot/+/51100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9c7140c7d51605e2708cbbc4a79d3ac37965656 Gerrit-Change-Number: 51100 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 18:04:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
by John Zhao (Code Review) 02 Mar '21

02 Mar '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51191 ) Change subject: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active ...................................................................... soc/intel/alderlake: Drop 100ms delay and do not poll Link Active Clone Tigerlake platform to drop the 100ms delay and do not poll Link Active State for TBT PCIe root ports in order to improve the resume time. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 --- M src/soc/intel/alderlake/acpi/tcss_pcierp.asl 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/51191/1 diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index abca5d1..e03bf7f 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -140,18 +140,6 @@ Local1 = L23R } STAT = 0x1 - - /* Wait for LA = 1 */ - Local0 = 0 - Local1 = LASX - While (Local1 == 0) { - If (Local0 > 20) { - Break - } - Sleep(5) - Local0++ - Local1 = LASX - } } /* @@ -192,8 +180,6 @@ If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ } Method (_PS3, 0, Serialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/51191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Gerrit-Change-Number: 51191 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add new IRQ module
by build bot (Jenkins) (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Nico Huber. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49408 ) Change subject: soc/intel/common: Add new IRQ module ...................................................................... Patch Set 17: (2 comments) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/49408/comment/b49be4a7_59789405 PS17, Line 106: static enum pci_pin find_shareable_pin(enum pci_pin fn_pin_map[MAX_FNS], please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49408/comment/ec15102b_f2496998 PS17, Line 224: printk(BIOS_ERR, "ERROR: %s: No free pins left for UNIQUE IRQ\n", __func__); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/49408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Gerrit-Change-Number: 49408 Gerrit-PatchSet: 17 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 02 Mar 2021 17:43:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: elog: Support logging CSE Lite info in elog
by Krishna P Bhat D (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Jamie Ryu, Rizwan Qureshi, Sridhar Siricilla, Patrick Rudolph, Karthik Ramasubramanian. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50472 ) Change subject: elog: Support logging CSE Lite info in elog ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50472/comment/7c0d74b7_d08101c4 PS6, Line 25: 2 | 2021-01-21 08:46:18 | CSE Info | Lite | 13.50.0.1269 | 13.50.0.1269 : | YES | 0x5 | 0x3 | RO : 3 | 2021-01-21 08:46:21 | CSE Info | Lite | 13.50.0.1269 | 13.50.0.1269 : | YES | 0x5 | 0x0 | RW > These two entries can be a bit confusing. […] To move logging cse lite info in ramstage would require us to move heci command implementations to common cse lib. Also, calling these commands again from ramstage would add additional time overhead. We can think of, 1) Logging the parameters only when CSE boots from RW. 2) To add an additional elog event in cse_board_reset indicating it is a cse initiated global reset. Your thoughts? https://review.coreboot.org/c/coreboot/+/50472/comment/2592acaa_74076046 PS6, Line 29: 4 | 2021-01-21 08:46:25 | System boot | 3098 > Humm.. this is what I was referring to. […] Can we move "System boot" event log to romstage? or can we have the timeline in this order ? 1. CSE lite info log, booting from RO 2. CSE initiated global reset 3. CSE lite info log, booting from RW 4. System boot -- To view, visit https://review.coreboot.org/c/coreboot/+/50472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib183941d1fa0a9971e30b4092ea3d23daaa29334 Gerrit-Change-Number: 50472 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 17:38:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: configs/config.google_volteer.build_test_purposes: Add file
by Angel Pons (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Francois Toguo Fotso. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51155 ) Change subject: configs/config.google_volteer.build_test_purposes: Add file ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Doesn't look like this build failure is related to CrashLog Done, hopefully -- To view, visit https://review.coreboot.org/c/coreboot/+/51155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Gerrit-Change-Number: 51155 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 17:35:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/chipset.cb: rename alias for SATA controllers
by Felix Held (Code Review) 02 Mar '21

02 Mar '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51190 ) Change subject: soc/amd/cezanne/chipset.cb: rename alias for SATA controllers ...................................................................... soc/amd/cezanne/chipset.cb: rename alias for SATA controllers Renoir/Cezanne have two SATA controllers with 2 ports each, so call them sata_0 and sata_1. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 --- M src/soc/amd/cezanne/chipset.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/51190/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index e82d435..5e3d269 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -32,8 +32,8 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B - device pci 0.0 alias sata_ahci off end # SATA AHCI Mode - device pci 0.1 alias sata_raid off end # SATA Controller; SATA Raid/AHCI Mode + device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode + device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end -- To view, visit https://review.coreboot.org/c/coreboot/+/51190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 Gerrit-Change-Number: 51190 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs/config.google_volteer.build_test_purposes: Add file
by Francois Toguo Fotso (Code Review) 02 Mar '21

02 Mar '21

Attention is currently required from: Angel Pons. Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51155 ) Change subject: configs/config.google_volteer.build_test_purposes: Add file ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Doesn't look like this build failure is related to CrashLog -- To view, visit https://review.coreboot.org/c/coreboot/+/51155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Gerrit-Change-Number: 51155 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Mar 2021 17:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Enable required devices in devicetree
by Felix Held (Code Review) 02 Mar '21

02 Mar '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51095 ) Change subject: mb/amd/majolica: Enable required devices in devicetree ...................................................................... mb/amd/majolica: Enable required devices in devicetree Most devices are now disabled by default in the chipset. Enable the iGPU and two XHCI controllers that are required to boot the board. BUG=b:180528708 TEST=To be tested Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index a141552..2695f60 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -3,6 +3,11 @@ chip soc/amd/cezanne device domain 0 on + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on end # USB 3.1 (USB0) + device ref xhci_1 on end # USB 3.1 (USB1) + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/51095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c Gerrit-Change-Number: 51095 Gerrit-PatchSet: 4 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2021