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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 )
Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables
......................................................................
Patch Set 8:
(5 comments)
File src/southbridge/intel/common/acpi_pirq_gen.h:
https://review.coreboot.org/c/coreboot/+/50857/comment/edd54748_c1cedde5
PS7, Line 55: [32][4]
> Do we have names for the `32` and `4` magic numbers?
Sure, will add.
File src/southbridge/intel/common/acpi_pirq_gen.c:
https://review.coreboot.org/c/coreboot/+/50857/comment/14a2e2db_2b378951
PS7, Line 45: pirq_map->gsi[pirq - PIRQ_A]);
> nit: Even though braces aren't strictly necessary for either branch of this conditional block, I'd s […]
Done
https://review.coreboot.org/c/coreboot/+/50857/comment/eced6a03_8946b720
PS7, Line 75: /* pop scope */
> Huh?
forgot to remove
https://review.coreboot.org/c/coreboot/+/50857/comment/0b7cdff3_3a852dc7
PS7, Line 85: char matrix[32][4];
> Since `intel_create_pirq_matrix()` may not always initialise all elements, I'd add an explicit zero […]
Done
File src/southbridge/intel/common/rcba_pirq.c:
https://review.coreboot.org/c/coreboot/+/50857/comment/620789ab_fc0f1be6
PS7, Line 57: int_pin - PCI_INT_A
> This appears four times in the loop body. Maybe: […]
+1.
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Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Nick Vaccaro, Aamir Bohra, Srinidhi N Kaushik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/tigerlake: Enable support for common IRQ block
......................................................................
soc/intel/tigerlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows tigerlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463
---
M src/soc/intel/tigerlake/Kconfig
D src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/fsp_params.c
5 files changed, 151 insertions(+), 165 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/49409/13
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
......................................................................
soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
Add a new function to fill out the data structures necessary to generate
a _PRT table.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62
---
M src/soc/intel/common/block/include/intelblocks/irq.h
M src/soc/intel/common/block/irq/irq.c
2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/51159/2
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Change subject: soc/intel/common: Add new IRQ module
......................................................................
soc/intel/common: Add new IRQ module
The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if
the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of
rules that the input IRQ table must conform to:
1) One entry per slot/function
2) Functions using PIRQs must use IOxAPIC IRQs 16-23
3) Single-function devices must use INTA
4) Each slot must have consistent INTx<->PIRQy mappings
5) Some functions have special interrupt pin requirements
6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN)
7) Some functions require a unique IRQ number
8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its
IRQ through IO-APIC.
Since the FSP has no visibility into the actual GPIOs used on the board
when GpioOverride is selected, IRQ conflicts can occur between PCI devices
and GPIOs. This patch gives SoC code the ability to generate a table of
PCI IRQs that will meet the FSPs rules and also not conflict with GPIO
IRQs.
BUG=b:171580862
TEST=Boot with patch series on volteer, verify IO-APIC IRQs in
`/proc/interrupts` match what is expected. No `GSI INT` or
`could not derive routing` messages seen in `dmesg` output.
Verified TPM, touchpad, touchscreen IRQs all function as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c
---
A src/soc/intel/common/block/include/intelblocks/irq.h
A src/soc/intel/common/block/irq/Kconfig
A src/soc/intel/common/block/irq/Makefile.inc
A src/soc/intel/common/block/irq/irq.c
4 files changed, 417 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/49408/17
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Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing
......................................................................
soc/intel/common: Add function to lpc_lib to return PIRQ routing
In order to fill out static entries for a _PRT table for
soc/intel/common, the PIRQ<->IRQ mapping is required. This patch adds
a function lpc_get_pch_pirq_routing() which returns this mapping.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be
---
M src/soc/intel/common/block/include/intelblocks/itss.h
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/itss/itss.c
M src/soc/intel/common/block/lpc/lpc_lib.c
4 files changed, 20 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/50858/6
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I'd like you to reexamine a change. Please visit
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Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables
......................................................................
sb/intel/common: Refactor _PRT generation to support GSI-based tables
Newer Intel SoCs also support _PRT tables, but they route PCI devices to
more than just PIRQs, and statically specify IRQs insteade of using link
devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this
additional use case.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868
---
M src/southbridge/intel/common/acpi_pirq_gen.c
M src/southbridge/intel/common/acpi_pirq_gen.h
M src/southbridge/intel/common/rcba_pirq.c
3 files changed, 133 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/50857/8
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