Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51189 )
Change subject: MAINTAINERS: Add Jakub as maintainer for tests/
......................................................................
MAINTAINERS: Add Jakub as maintainer for tests/
He practically is, so let's make it official.
Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M MAINTAINERS
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/51189/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 97bd8e1..2d8613a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -798,6 +798,11 @@
S: Maintained
F: src/vendorcode/eltan/
+TESTS
+M: Jakub Czapiga <jacz(a)semihalf.com>
+S: Maintained
+F: tests/
+
MISSING: TIMERS / DELAYS
MISSING: TIMESTAMPS
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50858 )
Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/lpc_lib.h:
https://review.coreboot.org/c/coreboot/+/50858/comment/5b470838_4b5354a3
PS3, Line 108: lpc_get_pch_pirq_routing
> Should we add `legacy` or `pic` in the name to indicate that this is the PIRQ# routing only for PIC/ […]
Done
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51047 )
Change subject: mb/google/guybrush: Add eSPI configuration
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/51047/comment/1f11b715_9fd99f33
PS3, Line 7: .generic_io_range[0] = {
: .base = 0x62,
: /*
: * Only 0x62 and 0x66 are required. But, this is not supported by
: * standard IO decodes and there are only 4 generic I/O windows
: * available. Hence, open a window from 0x62-0x67.
: */
: .size = 5,
: },
> Are we supporting ps/2 touchpoint?
We should be able to support PS/2 mouse, but this is needed for the keyboard and EC communication as well.
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Change subject: mb/google/guybrush: Add eSPI configuration
......................................................................
Patch Set 10: Code-Review+2
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51045 )
Change subject: soc/amd/cezanne: Fill out pci devices in chipset.cb
......................................................................
soc/amd/cezanne: Fill out pci devices in chipset.cb
BUG=b:180528708
TEST=builds
Signed-off-by: Mathew King <mathewk(a)chromium.org>
Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/cezanne/chipset.cb
1 file changed, 49 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index 42c711a..e82d435 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -4,14 +4,54 @@
end
device domain 0 on
device pci 00.0 alias gnb on end
- device pci 14.0 on end # SMBus, primary FCH function
- device pci 18.0 on end # Data fabric [0-7]
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
- device pci 18.6 on end
- device pci 18.7 on end
+ device pci 0.2 alias iommu off end # IOMMU
+
+ device pci 1.0 on end # Dummy Host Bridge, do not disable
+ device pci 1.1 alias gpp_bridge_1_1 off end # GPP Bridge 0
+ device pci 1.2 alias gpp_bridge_1_2 off end # GPP Bridge 1
+ device pci 1.3 alias gpp_bridge_1_3 off end # GPP Bridge 2
+
+ device pci 2.0 on end # Dummy Host Bridge, do not disable
+ device pci 2.1 alias gpp_bridge_2_1 off end # GPP Bridge 0
+ device pci 2.2 alias gpp_bridge_2_2 off end # GPP Bridge 1
+ device pci 2.3 alias gpp_bridge_2_3 off end # GPP Bridge 2
+ device pci 2.4 alias gpp_bridge_2_4 off end # GPP Bridge 3
+ device pci 2.5 alias gpp_bridge_2_5 off end # GPP Bridge 4
+ device pci 2.6 alias gpp_bridge_2_6 off end # GPP Bridge 5
+ device pci 2.7 alias gpp_bridge_2_7 off end # GPP Bridge 6
+
+ device pci 8.0 on end # Dummy Host Bridge, do not disable
+ device pci 8.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
+ device pci 0.0 alias gfx off end # Internal GPU (GFX)
+ device pci 0.1 alias gfx_az off end # Display HD Audio Controller (GFXAZ)
+ device pci 0.2 alias crypto off end # Crypto Coprocessor
+ device pci 0.3 alias xhci_0 off end # USB 3.1 (USB0)
+ device pci 0.4 alias xhci_1 off end # USB 3.1 (USB1)
+ device pci 0.5 alias acp off end # Audio Processor (ACP)
+ device pci 0.6 alias standalone_az off end # Audio Processor HD Audio Controller (Standalone AZ)
+ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
+ end
+ device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+ device pci 0.0 alias sata_ahci off end # SATA AHCI Mode
+ device pci 0.1 alias sata_raid off end # SATA Controller; SATA Raid/AHCI Mode
+ device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
+ device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
+ end
+ device pci 8.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+ device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
+ device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio
+ end
+
+ device pci 14.0 alias smbus on end # SMBus, primary FCH function
+ device pci 14.3 alias lpc_bridge on end # LPC Bridge
+
+ device pci 18.0 alias data_fabric_0 on end # Data fabric [0-7]
+ device pci 18.1 alias data_fabric_1 on end
+ device pci 18.2 alias data_fabric_2 on end
+ device pci 18.3 alias data_fabric_3 on end
+ device pci 18.4 alias data_fabric_4 on end
+ device pci 18.5 alias data_fabric_5 on end
+ device pci 18.6 alias data_fabric_6 on end
+ device pci 18.7 alias data_fabric_7 on end
end
end
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51145 )
Change subject: mb/google/brya: Fix a few mistakes in brya0 overridetree
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/brya0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/51145/comment/1f5e51a6_5a807b7e
PS2, Line 72: sx9324
> I agree, but I checked with our kernel guy. […]
Ah, I see, I wasn't sure how Gwendal came up with the conversion between the two formats... we'll have to bother Semtech about it I suppose.
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