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Hello build bot (Jenkins), Mary Ruthven, Joel Kitching, Furquan Shaikh, Vadim Bendebury, Christian Walter, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51164
to look at the new patch set (#3).
Change subject: security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC
......................................................................
security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC
Add marshaling and unmarshaling support for cr50 vendor sub-command to
reset EC and a interface function to exchange the same.
BUG=b:181051734
TEST=Build and boot to OS in drawlat. Ensure that when the command is
issued, EC reset is triggered.
Change-Id: I46063678511d27fea5eabbd12fc3af0b1df68143
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
M src/security/tpm/tss/vendor/cr50/cr50.c
M src/security/tpm/tss/vendor/cr50/cr50.h
3 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/51164/3
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Change subject: lib/cbfs.c: Fix return value of failure to measure
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51099/comment/f469b53c_ea2848a9
PS1, Line 10: bootable.
> > Makes sense. […]
Done
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Change subject: picasso: Update FSP to build 0x26
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Abandoned
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Change subject: configs/config.google_volteer.build_test_purposes: Add file
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> I saw that error too but I don't understand why it thinks BOARD_GOOGLE_VOLTEER needs to be selected?
No clue, probably because of the filename
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Change subject: mb/google/volteer/variants/copano: Describe USB ports in devicetree
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/google/volteer: Fix FPMCU pwr/rst gpio handling
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50828/comment/d5b5bfd1_2f6eb2fe
PS8, Line 10: 2. Disable power and assert reset in ramstage gpio
> I had tested the previous version, just tested this iteration and it still works.
Thanks, Duncan !
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Change subject: soc/intel/skylake: Do not unhide P2SB before disabling HECI
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: lib/cbfs.c: Fix return value of failure to measure
......................................................................
Patch Set 1:
(1 comment)
Patchset:
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> True - you got it wrong Philipp. […]
Done
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