Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51197 )
Change subject: [WIP] vc/amd/cezanne: add platform_Descriptors.c ......................................................................
[WIP] vc/amd/cezanne: add platform_Descriptors.c
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 --- A src/vendorcode/amd/fsp/cezanne/platform_descriptors.h 1 file changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/51197/1
diff --git a/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h new file mode 100644 index 0000000..69125c6 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H +#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* Upstream Auto Speed Change Allowed */ +typedef enum { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISBLED, + SPDC_ENABLED, + SPDC_INVALID +} dxio_upstream_auto_speed_change; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4_GFX, + CLK_REQ5, + CLK_REQ6, + /* 0x08 is invalid */ + CLK_GPP_REQ0 = 0x09, + CLK_GPP_REQ1, + CLK_GPP_REQ2, + CLK_GPP_REQ3, + CLK_GPP_REQ4, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1 = 0, + AUX2, + AUX3, + AUX4, + AUX5, + AUX6, + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1 = 0, + HDP2, + HDP3, + HDP4, + HDP5, + HDP6, + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP = 0, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* Cezanne DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* + * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, + * configure bifurcation and other settings. Beware that the lane numbers in + * here are the logical and not the physical lane numbers! + * + * Cezanne DXIO logical lane to physical PCIe lane mapping: + * + * logical | FT6 | AM4 + * --------|------------|---------------------- + * [00:03] | GPP[00:03] | GPP[00:03] + * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] + * [08:11] | GPP[08:11] | GFX[15:12] + * [12:15] | n/a | GFX[11:08] + * [16:23] | GFX[00:07] | GFX[07:0] + * + * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 + * platform additionally supports mapping lanes 8 and 9 to a SATA controller. + * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet + * controllers. + */ +typedef struct __packed { + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // Currently unused by FSP + uint8_t port_present :1; // Should be TRUE if train link + uint8_t reserved_3 :7; + uint8_t device_number :5; // Desired root port device number + uint8_t function_number :3; // Desired root port function number + uint8_t link_speed_capability :2; // See dxio_link_speed_cap + uint8_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint8_t eq_preset :4; // Gen3 equalization preset + uint8_t link_aspm :2; // See dxio_aspm_type + uint8_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint8_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint8_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint8_t slot_power_limit_scale :2; // Currently unused by FSP + uint8_t reserved_4 :6; + uint8_t link_compliance_mode :1; // Currently unused by FSP + uint8_t link_safe_mode :1; // Currently unused by FSP + uint8_t sb_link :1; // Currently unused by FSP + uint8_t clk_pm_support :1; // Currently unused by FSP + uint8_t channel_type :3; // See dxio_sata_channel_type + uint8_t turn_off_unused_lanes :1; // Power down lanes if device not present + uint8_t reserved[4]; +} fsp_dxio_descriptor; + +#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */