coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/wdee: Configure WLAN for Wdee
by Maulik V Vaghela (Code Review) 07 Aug '20

07 Aug '20

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42098 ) Change subject: mb/google/wdee: Configure WLAN for Wdee ...................................................................... Abandoned Karthik has taken care of this in his patchset -- To view, visit https://review.coreboot.org/c/coreboot/+/42098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ac1c9a83fbbf03066c09774324313f62d58bc38 Gerrit-Change-Number: 42098 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: cpu/x86/mtrr: Add helper function to cache cbmem in romstage
by Arthur Heymans (Code Review) 07 Aug '20

07 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37199 ) Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ...................................................................... cpu/x86/mtrr: Add helper function to cache cbmem in romstage Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB. Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR. Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..2658388 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -11,3 +11,5 @@ bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c + +romstage-y += cbmem_cache.c \ No newline at end of file diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c new file mode 100644 index 0000000..8753e9e --- /dev/null +++ b/src/cpu/x86/mtrr/cbmem_cache.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include <cpu/x86/cache.h> +#include <arch/cpu.h> +#include <program_loading.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> + +void setup_romstage_wb_cbmem_cache(void) +{ + int mtrr_num = get_free_var_mtrr(); + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t stage_cache_base, stage_cache_end; + size_t stage_cache_size; + size_t stage_cache_mtrr_size = 4 * KiB; + + printk(BIOS_DEBUG, "Setting MTRR's for cbmem and stage cache\n"); + + /* postcar will do invd so we need a way to make sure things are in memory + which is only possible if clflush is supported. */ + if (!clflush_supported()) { + printk(BIOS_WARNING, "CLFLUSH not supported, not caching cbmem!\n"); + if (CONFIG(COMPRESS_POSTCAR)) + printk(BIOS_WARNING, "Decompressing POSTCAR will be slow!\n"); + + return; + } + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache cbmem\n!"); + return; + } + /* Often cbmem_top is chosen to be aligned already to optimize MTRR + usage in the postcar frame so this should not be too worrisome. */ + top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB); + set_var_mtrr(mtrr_num, top_of_ram - 4 * MiB, 4 * MiB, MTRR_TYPE_WRBACK); + + if (!CONFIG(TSEG_STAGE_CACHE)) + return; + mtrr_num = get_free_var_mtrr(); + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache TSEG stage cache\n!"); + return; + } + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + stage_cache_end = stage_cache_base + stage_cache_size; + + /* Find MTRR to cover TSEG stage cache */ + while (1) { + /* Do some sanity check before it gets absurdly. */ + if (stage_cache_mtrr_size > 64 * MiB) { + printk(BIOS_WARNING, "Not caching stage cache, too large\n"); + return; + } + if (ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size) + + stage_cache_mtrr_size > stage_cache_end) + break; + stage_cache_mtrr_size *= 2; + } + set_var_mtrr(mtrr_num, ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size), + stage_cache_mtrr_size, MTRR_TYPE_WRBACK); +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..abdecfe 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -95,6 +95,8 @@ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); +void setup_romstage_wb_cbmem_cache(void); + /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); -- To view, visit https://review.coreboot.org/c/coreboot/+/37199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Gerrit-Change-Number: 37199 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/trembyle: update USB OC pin mapping
by Felix Held (Code Review) 07 Aug '20

07 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44268 ) Change subject: mb/google/zork/trembyle: update USB OC pin mapping ...................................................................... mb/google/zork/trembyle: update USB OC pin mapping The old USB OC pin mapping caused suspend to error out with an over- current condition on the USB ports. I found out that there are different versions of the schematics; this patch changes the mapping to the one found in the other version. BUG=b:162912099 Change-Id: I4f24273ce486982b60f7927b0f9eb4a2c14cf0d6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/variants/trembyle/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44268/1 diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 26d9a3e..8b5c14f 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -24,8 +24,8 @@ # USB OC pin mapping register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 # Enable I2C2 for trackpad, touchscreen, pen at 400kHz -- To view, visit https://review.coreboot.org/c/coreboot/+/44268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f24273ce486982b60f7927b0f9eb4a2c14cf0d6 Gerrit-Change-Number: 44268 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/usb/ehci_debug.c: Remove dead assignment
by HAOUAS Elyes (Code Review) 07 Aug '20

07 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44287 ) Change subject: drivers/usb/ehci_debug.c: Remove dead assignment ...................................................................... drivers/usb/ehci_debug.c: Remove dead assignment Change-Id: Id175f5a8087dd2751db3449fcb169372e2b534b2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/usb/ehci_debug.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44287/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5998172..81322a6 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -558,7 +558,6 @@ if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) { dprintk(BIOS_INFO, "No device in EHCI debug port.\n"); write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM); - ret = -4; goto err; } dprintk(BIOS_INFO, "EHCI debug port enabled.\n"); @@ -569,7 +568,6 @@ ret = dbgp_probe_gadget(port, &info->ep_pipe[0]); if (ret < 0) { dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n"); - ret = -6; goto err; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id175f5a8087dd2751db3449fcb169372e2b534b2 Gerrit-Change-Number: 44287 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: xeon_sp/cpx: Set HWP base feature
by Johnny Lin (Code Review) 07 Aug '20

07 Aug '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44171 ) Change subject: xeon_sp/cpx: Set HWP base feature ...................................................................... xeon_sp/cpx: Set HWP base feature Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44171/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 1df5c13..cf903b8 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -64,6 +64,18 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic(); + /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/44171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Gerrit-Change-Number: 44171 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/intel/wildcatpoint/iobp.c: Align with Lynxpoint
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42622 ) Change subject: sb/intel/wildcatpoint/iobp.c: Align with Lynxpoint ...................................................................... sb/intel/wildcatpoint/iobp.c: Align with Lynxpoint Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/wildcatpoint/iobp.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42622/1 diff --git a/src/southbridge/intel/wildcatpoint/iobp.c b/src/southbridge/intel/wildcatpoint/iobp.c index 72cb111..51dd8a6 100644 --- a/src/southbridge/intel/wildcatpoint/iobp.c +++ b/src/southbridge/intel/wildcatpoint/iobp.c @@ -93,10 +93,10 @@ status = RCBA16(IOBPS); if (status & IOBPS_TX_MASK) { printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - //return; + return; } - //printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); + printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -- To view, visit https://review.coreboot.org/c/coreboot/+/42622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10 Gerrit-Change-Number: 42622 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: security/intel/txt: Fix variable MTRR handling
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44183 ) Change subject: security/intel/txt: Fix variable MTRR handling ...................................................................... security/intel/txt: Fix variable MTRR handling The MSR macros were treated as memory addresses and the loops had off-by-one errors. This resulted in a hang right before GETSEC. Tested on Asrock B85M Pro4, ACM complains about the missing TPM. Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 23 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44183/1 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 0dd5237..fffb6b0 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -31,7 +31,7 @@ .macro PUSH_VAR_MTRR movl %ebx, %ecx shll %ecx - addl MTRR_PHYS_BASE(0), %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx rdmsr push %eax push %edx @@ -44,7 +44,7 @@ .macro POP_VAR_MTRR movl %ebx, %ecx shll %ecx - addl MTRR_PHYS_MASK(0), %ecx + addl $(MTRR_PHYS_MASK(0)), %ecx pop %edx pop %eax wrmsr @@ -54,19 +54,6 @@ wrmsr .endm -.macro CLEAR_VAR_MTRR - movl %ebx, %ecx - shll %ecx - addl MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - xorl %eax, %eax - wrmsr - incl %ecx /* MTRR_PHYS_MASK */ - xorl %edx, %edx - xorl %eax, %eax - wrmsr -.endm - .align 4 .text @@ -125,7 +112,7 @@ rdmsr andl $(0xff), %eax cmp %ebx, %eax - jge body_push_var_mtrrs + jg body_push_var_mtrrs /* * Disable cache. @@ -168,9 +155,22 @@ andl $(0xff), %eax movl %eax, %ebx + xorl %eax, %eax + xorl %edx, %edx + + jmp cond_clear_var_mtrrs + body_clear_var_mtrrs: - CLEAR_VAR_MTRR + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx + wrmsr + incl %ecx /* MTRR_PHYS_MASK */ + wrmsr + +cond_clear_var_mtrrs: + decl %ebx jnz body_clear_var_mtrrs @@ -274,9 +274,14 @@ andl $(0xff), %eax movl %eax, %ebx + jmp cond_pop_var_mtrrs + body_pop_var_mtrrs: POP_VAR_MTRR + +cond_pop_var_mtrrs: + decl %ebx jnz body_pop_var_mtrrs @@ -301,7 +306,7 @@ /* Enable cache */ movl %cr0, %eax andl $(~(CR0_CD | CR0_NW)), %eax - movl %eax, %cr0 + movl %eax, %cr0 /* Pop GDT */ addl $8, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/44183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a Gerrit-Change-Number: 44183 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use PCI bitwise ops
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42154 ) Change subject: sb/intel/lynxpoint: Use PCI bitwise ops ...................................................................... sb/intel/lynxpoint: Use PCI bitwise ops Some cases could not be factored out while keeping reproducibility. Also mark some potential bugs with a FIXME comment, since fixing them while also keeping the binary unchanged is pretty much impossible. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I27d6aaa59e12a337f80a6d3387cc9c8ae5949384 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 11 files changed, 89 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42154/1 diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f415170..cf360ff 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -41,9 +41,7 @@ pci_write_config32(dev, 0x120, reg32); if (!pch_is_lp()) { - reg16 = pci_read_config16(dev, 0x78); - reg16 &= ~(1 << 11); - pci_write_config16(dev, 0x78, reg16); + pci_and_config16(dev, 0x78, ~(1 << 11)); } } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); @@ -53,8 +51,7 @@ pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) reg32 &= ~(1UL << 31); @@ -70,11 +67,8 @@ reg8 |= (1 << 4); pci_write_config8(dev, 0x43, reg8); - if (!pch_is_lp()) { - reg32 = pci_read_config32(dev, 0xc0); - reg32 |= (1 << 17); - pci_write_config32(dev, 0xc0, reg32); - } + if (!pch_is_lp()) + pci_or_config32(dev, 0xc0, 1 << 17); /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); @@ -84,19 +78,14 @@ reg32 |= (1 << 14); pci_write_config32(dev, 0xc4, reg32); - if (!pch_is_lp()) { - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1UL << 31); - pci_write_config32(dev, 0xd0, reg32); - } + if (!pch_is_lp()) + pci_and_config32(dev, 0xd0, ~(1UL << 31)); - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status if (pch_is_lp()) { reg16 = read32(base + 0x0012); @@ -104,9 +93,7 @@ write32(base + 0x0012, reg16); /* disable Auto Voltage Detector */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x42, reg8); + pci_or_config8(dev, 0x42, 1 << 2); } } diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index b015ea2..68ea598 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -9,15 +9,7 @@ */ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8a61b29..9278b67 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -336,8 +336,7 @@ pch_config_rcba(lpt_lp_pm_rcba); - pci_write_config32(dev, 0xac, - pci_read_config32(dev, 0xac) | (1 << 21)); + pci_or_config32(dev, 0xac, 1 << 21); pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0UL, 0x00c00000); @@ -426,9 +425,7 @@ reg16 |= (1 << 2); // PCI CLKRUN# Enable pci_write_config16(dev, GEN_PMCON_1, reg16); - reg32 = pci_read_config32(dev, 0x64); - reg32 |= (1 << 6); - pci_write_config32(dev, 0x64, reg32); + pci_or_config32(dev, 0x64, 1 << 6); /* * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 @@ -482,22 +479,15 @@ static void pch_disable_smm_only_flashing(struct device *dev) { - u8 reg8; - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); + + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); } static void pch_fixups(struct device *dev) { - u8 gen_pmcon_2; - /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); /* * Enable DMI ASPM in the PCH diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index aeab0c7..43f36f3 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -567,7 +567,6 @@ { struct me_hfs hfs; u32 reg32; - u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -595,9 +594,8 @@ mkhi_end_of_post(); /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + pci_and_config16(PCH_ME_DEV, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index e3c5bb2..db5dd2e 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -80,9 +80,7 @@ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); } /* Set bit in function disable register to hide this device */ @@ -285,8 +283,6 @@ void pch_enable(struct device *dev) { - u16 reg16; - /* PCH PCIe Root Ports are handled in PCIe driver. */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) return; @@ -295,9 +291,8 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d957e8d..94750d8 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -196,41 +196,40 @@ rp = root_port_number(dev); if (!is_rp_enabled(rp)) { - static const uint32_t high_bit = (1UL << 31); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); if (!is_lp) { if (rp == 1 && !is_rp_enabled(2) && !is_rp_enabled(3) && !is_rp_enabled(4)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } if (rp == 5 && !is_rp_enabled(6) && !is_rp_enabled(7) && !is_rp_enabled(8)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } continue; } - pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pci_update_config32(dev, 0x420, ~high_bit, high_bit); + pci_or_config8(dev, 0xe2, 3 << 4); + pci_or_config32(dev, 0x420, 1 << 31); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pci_update_config32(dev, 0x420, ~0, (3 << 29)); + pci_or_config32(dev, 0x420, 3 << 29); /* Enable static clock gating. */ if (rp == 1 && !is_rp_enabled(2) && !is_rp_enabled(3) && !is_rp_enabled(4)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } else if (rp == 5 || rp == 6) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } continue; } @@ -238,29 +237,30 @@ enabled_ports++; /* Enable dynamic clock gating. */ - pci_update_config8(dev, 0xe1, 0xfc, 0x03); + pci_or_config8(dev, 0xe1, 0x03); if (is_lp) { - pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_or_config8(dev, 0xe2, 1 << 6); pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); } /* Update PECR1 register. */ - pci_update_config8(dev, 0xe8, ~0, 1); + pci_or_config8(dev, 0xe8, 1); + /* FIXME: Are we supposed to update this register with a constant boolean? */ pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pci_update_config32(dev, 0x420, ~0, (3 << 29)); + pci_or_config32(dev, 0x420, 3 << 29); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); } if (!enabled_ports && is_lp && rpc.ports[0]) - pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_or_config8(rpc.ports[0], 0xe1, 1 << 6); } static void root_port_commit_config(void) @@ -276,7 +276,6 @@ for (i = 0; i < rpc.num_ports; i++) { struct device *dev; - u16 reg16; dev = rpc.ports[i]; @@ -291,9 +290,8 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -603,11 +601,11 @@ } } - pci_update_config32(dev, 0x338, ~(1 << 26), 0); + pci_and_config32(dev, 0x338, ~(1 << 26)); } /* Enable LTR in Root Port. */ - pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); + pci_or_config32(dev, 0x64, 1 << 11); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); @@ -618,7 +616,7 @@ else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pci_update_config32(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); @@ -626,21 +624,21 @@ pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); /* Set Invalid Recieve Range Check Enable in MPC register. */ - pci_update_config32(dev, 0xd8, ~0, (1 << 25)); + pci_or_config32(dev, 0xd8, 1 << 25); - pci_update_config8(dev, 0xf5, 0x3f, 0); + pci_and_config8(dev, 0xf5, 0x3f); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) - pci_update_config8(dev, 0xf7, ~0xc, 0); + pci_and_config8(dev, 0xf7, ~0x0c); /* Set EOI forwarding disable. */ - pci_update_config32(dev, 0xd4, ~0, (1 << 1)); + pci_or_config32(dev, 0xd4, 1 << 1); /* Set something involving advanced error reporting. */ pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); if (is_lp) - pci_update_config32(dev, 0x100, ~0, (1 << 29)); + pci_or_config32(dev, 0x100, 1 << 29); /* Read and write back write-once capability registers. */ pci_update_config32(dev, 0x34, ~0, 0); @@ -651,8 +649,6 @@ static void pci_init(struct device *dev) { - u16 reg16; - printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ @@ -665,10 +661,8 @@ // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_update_config16(dev, PCI_BRIDGE_CONTROL, + ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); @@ -682,10 +676,8 @@ #endif /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); - pci_write_config16(dev, 0x06, reg16); - reg16 = pci_read_config16(dev, 0x1e); - pci_write_config16(dev, 0x1e, reg16); + pci_update_config16(dev, 0x06, ~0, 0); + pci_update_config16(dev, 0x1e, ~0, 0); } static void pch_pcie_enable(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 47e6f9b..dc53071 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -47,11 +47,10 @@ printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, 0x24, 0); + /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); pci_write_config8(dev, 0x09, 0x80); @@ -77,8 +76,8 @@ pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + } else if (config->sata_ahci) { u32 *abar; @@ -128,10 +127,8 @@ } pci_write_config32(dev, 0x98, reg32); - /* Setup register 9Ch */ - reg16 = 0; /* Disable alternate ID */ - reg16 |= (1 << 5); /* BWG step 12 */ - pci_write_config16(dev, 0x9c, reg16); + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); /* SATA Initialization register */ reg32 = 0x183; @@ -165,19 +162,21 @@ reg32 &= ~0x00000002; } write32(abar + 0x09, reg32); + } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, 0x24, 0); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); - /* Native mode capable on both primary and secondary (0xa) + /* + * Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf + * + * FIXME: Does not match the code. */ pci_write_config8(dev, 0x09, 0x8f); @@ -208,8 +207,7 @@ pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 39003f6..7e8c03f 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -15,6 +15,7 @@ u16 reg16; /* Enable clock gating */ + /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); pci_write_config32(dev, 0x80, reg16); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8bbe3fe..c0838c6 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -63,7 +63,6 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -73,9 +72,7 @@ continue; /* Disable Bus Mastering for this one device */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); @@ -414,8 +411,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8..4323f30 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -14,22 +14,18 @@ void usb_ehci_disable(pci_devfn_t dev) { - u16 reg16; - /* Set 0xDC[0]=1 */ pci_or_config32(dev, 0xdc, (1 << 0)); /* Set D3Hot state and disable PME */ - reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); - reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); - reg16 |= PWR_CTL_SET_D3; - pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, EHCI_PWR_CTL_STS, ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK), + PWR_CTL_SET_D3); /* Clear memory and bus master */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable device */ switch (dev) { @@ -121,21 +117,15 @@ static void usb_ehci_clock_gating(struct device *dev) { - u32 reg32; - /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 5) | (1 << 2) | (1 << 1); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 5) | (1 << 2) | (1 << 1)); /* Dx:F0:78h[1:0] = 11b */ - reg32 = pci_read_config32(dev, 0x78); - reg32 |= (1 << 1) | (1 << 0); - pci_write_config32(dev, 0x78, reg32); + pci_or_config32(dev, 0x78, (1 << 1) | (1 << 0)); } static void usb_ehci_init(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 8684aa9..d1e0275 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -157,7 +157,6 @@ /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { - u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); @@ -166,15 +165,10 @@ if (pch_is_lp()) { /* Set D0 state */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Clear PCI 0xB0[14:13] */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - pci_write_config32(dev, 0xb0, reg32); + pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); @@ -200,17 +194,13 @@ void usb_xhci_route_all(void) { u32 port_mask, route; - u16 reg16; /* Skip if EHCI is already disabled */ if (RCBA32(FD) & PCH_DISABLE_EHCI1) return; /* Set D0 state */ - reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Set USB3 superspeed enable */ port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); @@ -242,7 +232,6 @@ static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; - u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); @@ -266,9 +255,7 @@ pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ - reg16 = pci_read_config16(dev, 0x44); - reg16 |= (1 << 9) | (1 << 7) | (1 << 3); - pci_write_config16(dev, 0x44, reg16); + pci_or_config16(dev, 0x44, (1 << 9) | (1 << 7) | (1 << 3)); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { @@ -281,23 +268,17 @@ pci_write_config32(dev, 0xa0, reg32); /* D20:F0:A4h[13] = 0 */ - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= ~(1 << 13); - pci_write_config32(dev, 0xa4, reg32); + pci_and_config32(dev, 0xa4, ~(1 << 13)); } static void usb_xhci_init(struct device *dev) { u32 reg32; - u16 reg16; u8 *mem_base = usb_xhci_mem_base(dev); config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Enable clock gating first */ usb_xhci_clock_gating(dev); @@ -321,10 +302,7 @@ write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - reg32 |= (1 << 17); - pci_write_config32(dev, 0xb0, reg32); + pci_update_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)), 1 << 17); } reg32 = pci_read_config32(dev, 0x50); @@ -340,15 +318,10 @@ pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1UL << 31); - pci_write_config32(dev, 0x44, reg32); + pci_or_config32(dev, 0x44, 1 << 31); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ - reg32 = pci_read_config32(dev, 0x40); - reg32 &= ~(1 << 23); /* unsupported request */ - reg32 |= (1UL << 31); - pci_write_config32(dev, 0x40, reg32); + pci_update_config32(dev, 0x40, ~(1 << 23), 1 << 31); /* unsupported request */ if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or -- To view, visit https://review.coreboot.org/c/coreboot/+/42154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d6aaa59e12a337f80a6d3387cc9c8ae5949384 Gerrit-Change-Number: 42154 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY] mb/asrock/b85m_pro4: Select DRIVERS_GENESYSLOGIC_GL9763E
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44161 ) Change subject: [TESTONLY] mb/asrock/b85m_pro4: Select DRIVERS_GENESYSLOGIC_GL9763E ...................................................................... [TESTONLY] mb/asrock/b85m_pro4: Select DRIVERS_GENESYSLOGIC_GL9763E This is just to build test the code. Change-Id: Ib0b78cf874ab28d2b6ed687c1a63bcca3d788d2c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44161/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc65120..f4a2b89 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select CPU_INTEL_HASWELL + select DRIVERS_GENESYSLOGIC_GL9763E select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT -- To view, visit https://review.coreboot.org/c/coreboot/+/44161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b78cf874ab28d2b6ed687c1a63bcca3d788d2c Gerrit-Change-Number: 44161 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/lynxpoint: Consider root ports being disabled by strap
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44155 ) Change subject: sb/intel/lynxpoint: Consider root ports being disabled by strap ...................................................................... sb/intel/lynxpoint: Consider root ports being disabled by strap PCIe RPC (Root Port Configuration) straps will force-disable some root port functions if some root ports have a width greater than x1. In two cases, this affects the last function. The PCIe init code will never finish configuring the root ports if that is the case: it assumes that the last function will eventually run through the code, but it doesn't. If PCIe initialization does not complete, pressing the power button will not power off the board, unless it is held for about five seconds. Also, Windows 10 will show a BSOD about MACHINE CHECK EXCEPTION, and lock up instead of rebooting. Depending on the microcode version, the BSOD may not be visible. This happens even when the root port is not populated. Use the strap fuse configuration value to know which configuration the PCH is strapped to. If needed, update the number of ports accordingly. In addition, print the updated value to ease debugging PCIe init code. Tested on Asrock B85M Pro4, PCIe initialization completes successfully. Change-Id: Id6da3a1f45467f00002a5ed41df8650f4a74eeba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44155/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d2950e7..5323e74 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -100,6 +100,36 @@ } } +static void update_num_ports(void) +{ + /* + * The last visible function depends on the strapped root port width: + * + * +-----+----+----+----+----+ + * | RPC | #5 | #6 | #7 | #8 | + * +-----+----+----+----+----+ + * | 0 | x1 | x1 | x1 | x1 | + * | 1 | x2 | | x1 | x1 | + * | 2 | x2 | | x2 | | + * | 3 | x4 | | | | + * +-----+----+----+----+----+ + */ + switch ((rpc.strpfusecfg2 >> 14) & 0x3) { + case 0: + case 1: + break; + case 2: + rpc.num_ports = MIN(rpc.num_ports, 7); + break; + case 3: + rpc.num_ports = MIN(rpc.num_ports, 5); + break; + } + + printk(BIOS_DEBUG, "Adjusted number of PCIe root ports to %d as per strpfusecfg2\n", + rpc.num_ports); +} + static void root_port_init_config(struct device *dev) { int rp; @@ -137,6 +167,10 @@ case 5: rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc); rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c); + + if (!pch_is_lp()) + update_num_ports(); + break; case 6: rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c); -- To view, visit https://review.coreboot.org/c/coreboot/+/44155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6da3a1f45467f00002a5ed41df8650f4a74eeba Gerrit-Change-Number: 44155 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020