Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42098 )
Change subject: mb/google/wdee: Configure WLAN for Wdee
......................................................................
Abandoned
Karthik has taken care of this in his patchset
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0ac1c9a83fbbf03066c09774324313f62d58bc38
Gerrit-Change-Number: 42098
Gerrit-PatchSet: 5
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37199 )
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage
......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache.
In most circumstances this memory is set up as UC, so to speed
up these operations like decompressing postcar, this has to be
set up as WB.
Note: This should only be attempted on platforms where some form
of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/mtrr/Makefile.inc
A src/cpu/x86/mtrr/cbmem_cache.c
M src/include/cpu/x86/mtrr.h
3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/1
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index 129d05d..2658388 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -11,3 +11,5 @@
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
+
+romstage-y += cbmem_cache.c
\ No newline at end of file
diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c
new file mode 100644
index 0000000..8753e9e
--- /dev/null
+++ b/src/cpu/x86/mtrr/cbmem_cache.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
+#include <program_loading.h>
+#include <commonlib/region.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+
+void setup_romstage_wb_cbmem_cache(void)
+{
+ int mtrr_num = get_free_var_mtrr();
+ uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t stage_cache_base, stage_cache_end;
+ size_t stage_cache_size;
+ size_t stage_cache_mtrr_size = 4 * KiB;
+
+ printk(BIOS_DEBUG, "Setting MTRR's for cbmem and stage cache\n");
+
+ /* postcar will do invd so we need a way to make sure things are in memory
+ which is only possible if clflush is supported. */
+ if (!clflush_supported()) {
+ printk(BIOS_WARNING, "CLFLUSH not supported, not caching cbmem!\n");
+ if (CONFIG(COMPRESS_POSTCAR))
+ printk(BIOS_WARNING, "Decompressing POSTCAR will be slow!\n");
+
+ return;
+ }
+ if (mtrr_num < 0) {
+ printk(BIOS_DEBUG, "No MTRR free to cache cbmem\n!");
+ return;
+ }
+ /* Often cbmem_top is chosen to be aligned already to optimize MTRR
+ usage in the postcar frame so this should not be too worrisome. */
+ top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
+ set_var_mtrr(mtrr_num, top_of_ram - 4 * MiB, 4 * MiB, MTRR_TYPE_WRBACK);
+
+ if (!CONFIG(TSEG_STAGE_CACHE))
+ return;
+ mtrr_num = get_free_var_mtrr();
+ if (mtrr_num < 0) {
+ printk(BIOS_DEBUG, "No MTRR free to cache TSEG stage cache\n!");
+ return;
+ }
+ stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size);
+ stage_cache_end = stage_cache_base + stage_cache_size;
+
+ /* Find MTRR to cover TSEG stage cache */
+ while (1) {
+ /* Do some sanity check before it gets absurdly. */
+ if (stage_cache_mtrr_size > 64 * MiB) {
+ printk(BIOS_WARNING, "Not caching stage cache, too large\n");
+ return;
+ }
+ if (ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size)
+ + stage_cache_mtrr_size > stage_cache_end)
+ break;
+ stage_cache_mtrr_size *= 2;
+ }
+ set_var_mtrr(mtrr_num, ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size),
+ stage_cache_mtrr_size, MTRR_TYPE_WRBACK);
+}
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 29256c8..abdecfe 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -95,6 +95,8 @@
void x86_setup_fixed_mtrrs_no_enable(void);
void x86_mtrr_check(void);
+void setup_romstage_wb_cbmem_cache(void);
+
/* Insert a temporary MTRR range for the duration of coreboot's runtime.
* This function needs to be called after the first MTRR solution is derived. */
void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
--
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Gerrit-Change-Number: 37199
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44268 )
Change subject: mb/google/zork/trembyle: update USB OC pin mapping
......................................................................
mb/google/zork/trembyle: update USB OC pin mapping
The old USB OC pin mapping caused suspend to error out with an over-
current condition on the USB ports. I found out that there are different
versions of the schematics; this patch changes the mapping to the one
found in the other version.
BUG=b:162912099
Change-Id: I4f24273ce486982b60f7927b0f9eb4a2c14cf0d6
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/google/zork/variants/trembyle/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44268/1
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
index 26d9a3e..8b5c14f 100644
--- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -24,8 +24,8 @@
# USB OC pin mapping
register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0
- register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0
- register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1
+ register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0
+ register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1
register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1
# Enable I2C2 for trackpad, touchscreen, pen at 400kHz
--
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Gerrit-Change-Id: I4f24273ce486982b60f7927b0f9eb4a2c14cf0d6
Gerrit-Change-Number: 44268
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44155 )
Change subject: sb/intel/lynxpoint: Consider root ports being disabled by strap
......................................................................
sb/intel/lynxpoint: Consider root ports being disabled by strap
PCIe RPC (Root Port Configuration) straps will force-disable some root
port functions if some root ports have a width greater than x1. In two
cases, this affects the last function. The PCIe init code will never
finish configuring the root ports if that is the case: it assumes that
the last function will eventually run through the code, but it doesn't.
If PCIe initialization does not complete, pressing the power button will
not power off the board, unless it is held for about five seconds. Also,
Windows 10 will show a BSOD about MACHINE CHECK EXCEPTION, and lock up
instead of rebooting. Depending on the microcode version, the BSOD may
not be visible. This happens even when the root port is not populated.
Use the strap fuse configuration value to know which configuration the
PCH is strapped to. If needed, update the number of ports accordingly.
In addition, print the updated value to ease debugging PCIe init code.
Tested on Asrock B85M Pro4, PCIe initialization completes successfully.
Change-Id: Id6da3a1f45467f00002a5ed41df8650f4a74eeba
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44155/1
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index d2950e7..5323e74 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -100,6 +100,36 @@
}
}
+static void update_num_ports(void)
+{
+ /*
+ * The last visible function depends on the strapped root port width:
+ *
+ * +-----+----+----+----+----+
+ * | RPC | #5 | #6 | #7 | #8 |
+ * +-----+----+----+----+----+
+ * | 0 | x1 | x1 | x1 | x1 |
+ * | 1 | x2 | | x1 | x1 |
+ * | 2 | x2 | | x2 | |
+ * | 3 | x4 | | | |
+ * +-----+----+----+----+----+
+ */
+ switch ((rpc.strpfusecfg2 >> 14) & 0x3) {
+ case 0:
+ case 1:
+ break;
+ case 2:
+ rpc.num_ports = MIN(rpc.num_ports, 7);
+ break;
+ case 3:
+ rpc.num_ports = MIN(rpc.num_ports, 5);
+ break;
+ }
+
+ printk(BIOS_DEBUG, "Adjusted number of PCIe root ports to %d as per strpfusecfg2\n",
+ rpc.num_ports);
+}
+
static void root_port_init_config(struct device *dev)
{
int rp;
@@ -137,6 +167,10 @@
case 5:
rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc);
rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c);
+
+ if (!pch_is_lp())
+ update_num_ports();
+
break;
case 6:
rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c);
--
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