coreboot-gerrit August 2020

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 07 Aug '20

07 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > > Patch Set 2: > > > > > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > > > > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > > > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > > > > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. > > > > "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. > > > > @Nate: is this* valid for SKL/KBL as well? > Yes, this is valid and exactly the point, why native SGX init can't be used. LT_MEMORY_LOCK must be set, *before* native SGX init (well, more specifically before microcode reload). That conflicts with the requirement of FSP-S to be able to write registers. > At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected Yes, SGX works. No, not in a secure way with native SGX init without LT_MEMORY_LOCK. -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 22:44:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 07 Aug '20

07 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. > > "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. > > @Nate: is this* valid for SKL/KBL as well? Yes, this is valid and exactly the point, why native SGX init can't be used. LT_MEMORY_LOCK must be set, *before* native SGX init (well, more specifically before microcode reload). That conflicts with the requirement of FSP-S to be able to write registers. -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 22:43:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Pratikkumar V Prajapati (Code Review) 07 Aug '20

07 Aug '20

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. @Nate: is this* valid for SKL/KBL as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 22:34:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 07 Aug '20

07 Aug '20

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Pratikkumar V Prajapati (Code Review) 07 Aug '20

07 Aug '20

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 21:57:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h
by Felix Singer (Code Review) 07 Aug '20

07 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44027 ) Change subject: soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h ...................................................................... soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h Change-Id: Ic83cfbe2a715db317d94c2b9c6cdd8c58a43612f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/include/soc/pci_devs.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44027/1 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 60c5f3a..75f1ead 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -28,6 +28,10 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEV_SLOT_TS 0x04 +#define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) +#define SA_DEV_TS PCI_DEV(0, SA_DEV_SLOT_TS, 0) + #define SA_DEV_SLOT_GMM 0x08 #define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) #define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/44027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83cfbe2a715db317d94c2b9c6cdd8c58a43612f Gerrit-Change-Number: 44027 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Set Heci1Disable depending on devicetree config
by Felix Singer (Code Review) 07 Aug '20

07 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44177 ) Change subject: soc/intel/cnl: Set Heci1Disable depending on devicetree config ...................................................................... soc/intel/cnl: Set Heci1Disable depending on devicetree config Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/duffy/overridetree.cb M src/mainboard/google/hatch/variants/faffy/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/overridetree.cb M src/mainboard/google/hatch/variants/noibat/overridetree.cb M src/mainboard/google/hatch/variants/puff/overridetree.cb M src/mainboard/google/hatch/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/fsp_params.c 13 files changed, 13 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44177/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e9daf0d..4011693 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -418,7 +417,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cb314ab..a12b71c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -29,8 +29,6 @@ register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable heci communication - register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix @@ -312,7 +310,7 @@ device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 2f2b643..7f75c78 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -369,6 +367,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 8aff8d1..c1c44a6 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -376,6 +374,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index 01691ff..67e62e7 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -369,6 +367,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index cac7516..2de90ec 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -284,6 +282,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index c78364d..7ead982 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -308,6 +306,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index c394977..d7b2298 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -303,6 +301,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f22c626..bacc6dc 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" @@ -350,7 +349,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1a8e624..e79a8a5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,7 +15,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" @@ -369,7 +368,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 01d970c..0b40a5c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -8,9 +8,6 @@ register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - # HECI - register "HeciEnabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index f0f5ebe..9cdeeab 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -197,9 +197,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off # Management Engine Interface 1 - register "HeciEnabled" = "0" - end + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0853cca..0779ce2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -525,7 +525,8 @@ params->Heci3Enabled = config->Heci3Enabled; #if !CONFIG(HECI_DISABLE_USING_SMM) - params->Heci1Disabled = !config->HeciEnabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE); + params->Heci1Disabled = !is_dev_enabled(dev); #endif params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/44177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Gerrit-Change-Number: 44177 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/zork: Don't generate power resource for Raydium TS
by Raul Rangel (Code Review) 07 Aug '20

07 Aug '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43467 ) Change subject: mb/google/zork: Don't generate power resource for Raydium TS ...................................................................... mb/google/zork: Don't generate power resource for Raydium TS The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF method to the kernel. These are contradictory. The ownership of the GPIO should be mutually exclusive between either the OS or the FW. The linux kernel driver has support for the reset GPIO, so omit the power resource. I also changed the default GPIO value to high to leave the device in reset. The kernel will de-assert this when it's ready to talk with the device. It also asserts it before entering sleep, so the value is consistent. BUG=b:160854397 TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+ times. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/dalboz/overridetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb 6 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43467/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 23b5458..c7e9823 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -166,7 +166,7 @@ /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), /* USI_RESET */ - PAD_GPO(GPIO_140, LOW), + PAD_GPO(GPIO_140, HIGH), /* USB_HUB_RST_L */ PAD_GPO(GPIO_141, HIGH), /* BT_DISABLE */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 640b765..4d2e609 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -158,7 +158,7 @@ /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), /* USI_RESET */ - PAD_GPO(GPIO_140, LOW), + PAD_GPO(GPIO_140, HIGH), /* UART1_RXD - FPMCU */ PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), /* UART1_TXD - FPMCU */ diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 229469e..8491e9d 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -83,8 +83,6 @@ register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" - register "has_power_resource" = "1" device i2c 10 on end end chip drivers/i2c/hid diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 81fc4fd..cffc2c3 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -52,8 +52,6 @@ register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" - register "has_power_resource" = "1" device i2c 39 on end end chip drivers/i2c/generic diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index f7366ac..64a391e 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -75,8 +75,6 @@ register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" - register "has_power_resource" = "1" device i2c 39 on end end chip drivers/i2c/hid diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 22aced2..e28adc5 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -143,8 +143,6 @@ register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" - register "has_power_resource" = "1" device i2c 39 on end end chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/43467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e Gerrit-Change-Number: 43467 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: soc/amd/picasso/acpi: remove AOAC device enables from global NVS
by Felix Held (Code Review) 07 Aug '20

07 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... soc/amd/picasso/acpi: remove AOAC device enables from global NVS These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/southbridge.c 3 files changed, 1 insertion(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44245/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6e63b8d..6790a5f 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -25,19 +25,6 @@ TMPS, 8, // 0x17 - Temperature Sensor ID TCRT, 8, // 0x18 - Critical Threshold TPSV, 8, // 0x19 - Passive Threshold - Offset (0x20), // 0x20 - AOAC Device Enables - , 7, - IC2E, 1, // I2C2, 7 - IC3E, 1, // I2C3, 8 - IC4E, 1, // I2C4, 9 - , 1, - UT0E, 1, // UART0, 11 - UT1E, 1, // UART1, 12 - , 3, - UT2E, 1, // UART2, 16 - , 9, - UT23, 1, // UART3, 26 - ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index b6708c8..2abcdd3 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -25,9 +25,7 @@ uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */ - uint8_t pad1[6]; - aoac_devs_t aoac; /* 0x20 - AOAC device enables */ - uint8_t unused[220]; + uint8_t unused[230]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 54d7640..0b45c10 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -347,22 +347,6 @@ al2ahb_clock_gate(); } -static void set_sb_final_nvs(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2); - gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3); - gnvs->aoac.espi = 1; -} - void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; @@ -370,8 +354,6 @@ if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); - - set_sb_final_nvs(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Tim Wawrzynczak (Code Review) 07 Aug '20

07 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > I am checking on this, on the SKL, CNL, ICL it still maps to LSB. […] Gotcha, thanks Aamir, I am finding the documentation around this register kind of confusing 😕 -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Fri, 07 Aug 2020 16:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit August 2020