Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43291 )
Change subject: mb/elmex/pcm205401: Add comment about the code
......................................................................
mb/elmex/pcm205401: Add comment about the code
It's not missing, it's just not where one expects it to be.
Change-Id: I377b68cbdc9266048074dc326490750777a6fbf5
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/elmex/pcm205401/Kconfig
M src/mainboard/elmex/pcm205401/Kconfig.name
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43291/1
diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig
index fbb8e9e..53e7920 100644
--- a/src/mainboard/elmex/pcm205401/Kconfig
+++ b/src/mainboard/elmex/pcm205401/Kconfig
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
+# The code for this board is under elmex/pcm205400
+
if BOARD_ELMEX_PCM205401
config MAINBOARD_PART_NUMBER
diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name
index f70b215..eb14cac 100644
--- a/src/mainboard/elmex/pcm205401/Kconfig.name
+++ b/src/mainboard/elmex/pcm205401/Kconfig.name
@@ -1,2 +1,4 @@
+# The code for this board is under elmex/pcm205400
+
config BOARD_ELMEX_PCM205401
bool "pcm205401"
--
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Gerrit-Change-Id: I377b68cbdc9266048074dc326490750777a6fbf5
Gerrit-Change-Number: 43291
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44182 )
Change subject: mb/asrock/b85m_pro4: Support LPC TPM
......................................................................
mb/asrock/b85m_pro4: Support LPC TPM
This mainboard has a 18-pin LPC header, where one can plug in a TPM.
Untested, as I don't have a TPM.
Change-Id: I14a159c373987d8b12fde18f327a9eb387c01de8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/asrock/b85m_pro4/Kconfig
M src/mainboard/asrock/b85m_pro4/devicetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44182/1
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig
index dc65120..0a13281 100644
--- a/src/mainboard/asrock/b85m_pro4/Kconfig
+++ b/src/mainboard/asrock/b85m_pro4/Kconfig
@@ -12,6 +12,7 @@
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_USES_IFD_GBE_REGION
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index 106df54..d257f18 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -103,6 +103,9 @@
device pnp 2e.16 off end # Deep sleep
device pnp 2e.17 off end # GPIOA
end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM
+ end
end
device pci 1f.2 on end # SATA (AHCI)
device pci 1f.3 on end # SMBus
--
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Gerrit-Change-Id: I14a159c373987d8b12fde18f327a9eb387c01de8
Gerrit-Change-Number: 44182
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Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44181 )
Change subject: security/intel/txt: Allow using CF9 reset, too
......................................................................
security/intel/txt: Allow using CF9 reset, too
Soften the hard dependency on SOC_INTEL_COMMON_BLOCK_SA by allowing CF9
resets to be used in place of global resets. If both types of reset are
available, prefer a global reset. This preserves current behavior, and
allows more platforms to use the TXT support code, such as Haswell.
Change-Id: I034fa0b342135e7101c21646be8fd6b5d3252d9e
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/security/intel/txt/Kconfig
M src/security/intel/txt/common.c
2 files changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44181/1
diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig
index edb13a5..3dd912e 100644
--- a/src/security/intel/txt/Kconfig
+++ b/src/security/intel/txt/Kconfig
@@ -9,7 +9,7 @@
depends on (TPM1 || TPM2)
depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
depends on PLATFORM_HAS_DRAM_CLEAR
- depends on SOC_INTEL_COMMON_BLOCK_SA
+ depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET)
if INTEL_TXT
diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c
index d3e18376..5a5d637 100644
--- a/src/security/intel/txt/common.c
+++ b/src/security/intel/txt/common.c
@@ -10,11 +10,27 @@
#include <cpu/x86/mp.h>
#include <lib.h>
#include <smp/node.h>
+
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA)
#include <soc/intel/common/reset.h>
+#else
+#include <cf9_reset.h>
+#endif
+
#include "txt.h"
#include "txt_register.h"
#include "txt_getsec.h"
+/* Usual security practice: if an unexpected error happens, reboot */
+static void __noreturn txt_reset_platform(void)
+{
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA)
+ global_reset();
+#else
+ full_reset();
+#endif
+}
+
/**
* Dump the ACM error status bits.
*
@@ -307,7 +323,7 @@
msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if (!(msr.lo & BIT(0))) {
printk(BIOS_ERR, "TEE-TXT: IA32_FEATURE_CONTROL is not locked\n");
- global_reset();
+ txt_reset_platform();
}
printk(BIOS_DEBUG, "TEE-TXT: IA32_FEATURE_CONTROL\n");
--
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Gerrit-Change-Number: 44181
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 )
Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime
......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42794/16//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/42794/16//COMMIT_MSG@21
PS16, Line 21:
Please mention, what happens, if a GCC without the patch is used. Will the coreboot with Asan enabled fail to build, or build and fail to run?
--
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Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Gerrit-Change-Number: 42794
Gerrit-PatchSet: 16
Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Comment-Date: Fri, 07 Aug 2020 07:35:53 +0000
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Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44274 )
Change subject: mb/google/volteer: support variant defined spd paths
......................................................................
mb/google/volteer: support variant defined spd paths
Allow variants to override the SPD_SOURCE_PATH to allow supporting
different types of DDR.
BUG=b:163065661
TEST="emerge-volteer coreboot" and verify all variants build.
Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/volteer/spd/Makefile.inc
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44274/1
diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc
index e125994..d0cc720 100644
--- a/src/mainboard/google/volteer/spd/Makefile.inc
+++ b/src/mainboard/google/volteer/spd/Makefile.inc
@@ -4,7 +4,11 @@
ifneq ($(SPD_SOURCES),)
SPD_BIN = $(obj)/spd.bin
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/tigerlake/spd/lp4x/$(f))
+ifeq ($(SPD_SOURCE_PATH),)
+SPD_SOURCE_PATH := src/soc/intel/tigerlake/spd/lp4x/
+endif
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), $$(SPD_SOURCE_PATH)/$(f))
# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
--
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