coreboot-gerrit August 2020

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Change in coreboot[master]: mb/elmex/pcm205401: Add comment about the code
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43291 ) Change subject: mb/elmex/pcm205401: Add comment about the code ...................................................................... mb/elmex/pcm205401: Add comment about the code It's not missing, it's just not where one expects it to be. Change-Id: I377b68cbdc9266048074dc326490750777a6fbf5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/elmex/pcm205401/Kconfig M src/mainboard/elmex/pcm205401/Kconfig.name 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43291/1 diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index fbb8e9e..53e7920 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +# The code for this board is under elmex/pcm205400 + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215..eb14cac 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,4 @@ +# The code for this board is under elmex/pcm205400 + config BOARD_ELMEX_PCM205401 bool "pcm205401" -- To view, visit https://review.coreboot.org/c/coreboot/+/43291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377b68cbdc9266048074dc326490750777a6fbf5 Gerrit-Change-Number: 43291 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Support LPC TPM
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44182 ) Change subject: mb/asrock/b85m_pro4: Support LPC TPM ...................................................................... mb/asrock/b85m_pro4: Support LPC TPM This mainboard has a 18-pin LPC header, where one can plug in a TPM. Untested, as I don't have a TPM. Change-Id: I14a159c373987d8b12fde18f327a9eb387c01de8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/b85m_pro4/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44182/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc65120..0a13281 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -12,6 +12,7 @@ select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 106df54..d257f18 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -103,6 +103,9 @@ device pnp 2e.16 off end # Deep sleep device pnp 2e.17 off end # GPIOA end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end end device pci 1f.2 on end # SATA (AHCI) device pci 1f.3 on end # SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/44182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14a159c373987d8b12fde18f327a9eb387c01de8 Gerrit-Change-Number: 44182 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: Add `intel_ht_supported` function
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44210 ) Change subject: cpu/intel/common: Add `intel_ht_supported` function ...................................................................... cpu/intel/common: Add `intel_ht_supported` function Change-Id: I90c0378c4042dec39c8c86c1d2339a5cbcfe78e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/hyperthreading.c 2 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44210/1 diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 57a5fe6..df14668 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -3,7 +3,7 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H -#include <stdint.h> +#include <types.h> void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); @@ -18,6 +18,11 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version); /* + * Returns true if CPU supports Hyper-Threading. + */ +bool intel_ht_supported(void); + +/* * Returns true if it's not thread 0 on a hyperthreading enabled core. */ bool intel_ht_sibling(void); diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index d686149..fce7576 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -3,6 +3,13 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/common/common.h> #include <arch/cpu.h> +#include <types.h> + +bool intel_ht_supported(void) +{ + /* Is HyperThreading supported? */ + return !!(cpuid_edx(1) & CPUID_FEAURE_HTT); +} /* * Return true if running thread does not have the smallest lapic ID @@ -13,8 +20,7 @@ struct cpuid_result result; unsigned int core_ids, apic_ids, threads; - /* Is Hyper-Threading supported */ - if (!(cpuid_edx(1) & CPUID_FEAURE_HTT)) + if (!intel_ht_supported()) return false; apic_ids = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/44210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90c0378c4042dec39c8c86c1d2339a5cbcfe78e3 Gerrit-Change-Number: 44210 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Allow using CF9 reset, too
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44181 ) Change subject: security/intel/txt: Allow using CF9 reset, too ...................................................................... security/intel/txt: Allow using CF9 reset, too Soften the hard dependency on SOC_INTEL_COMMON_BLOCK_SA by allowing CF9 resets to be used in place of global resets. If both types of reset are available, prefer a global reset. This preserves current behavior, and allows more platforms to use the TXT support code, such as Haswell. Change-Id: I034fa0b342135e7101c21646be8fd6b5d3252d9e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/Kconfig M src/security/intel/txt/common.c 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44181/1 diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index edb13a5..3dd912e 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -9,7 +9,7 @@ depends on (TPM1 || TPM2) depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE depends on PLATFORM_HAS_DRAM_CLEAR - depends on SOC_INTEL_COMMON_BLOCK_SA + depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) if INTEL_TXT diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index d3e18376..5a5d637 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -10,11 +10,27 @@ #include <cpu/x86/mp.h> #include <lib.h> #include <smp/node.h> + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include <soc/intel/common/reset.h> +#else +#include <cf9_reset.h> +#endif + #include "txt.h" #include "txt_register.h" #include "txt_getsec.h" +/* Usual security practice: if an unexpected error happens, reboot */ +static void __noreturn txt_reset_platform(void) +{ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) + global_reset(); +#else + full_reset(); +#endif +} + /** * Dump the ACM error status bits. * @@ -307,7 +323,7 @@ msr_t msr = rdmsr(IA32_FEATURE_CONTROL); if (!(msr.lo & BIT(0))) { printk(BIOS_ERR, "TEE-TXT: IA32_FEATURE_CONTROL is not locked\n"); - global_reset(); + txt_reset_platform(); } printk(BIOS_DEBUG, "TEE-TXT: IA32_FEATURE_CONTROL\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/44181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I034fa0b342135e7101c21646be8fd6b5d3252d9e Gerrit-Change-Number: 44181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/kblrvp: Factor out `IoBufferOwnership`
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43909 ) Change subject: mb/intel/kblrvp: Factor out `IoBufferOwnership` ...................................................................... mb/intel/kblrvp: Factor out `IoBufferOwnership` RVP11 and RVP3 set it to zero, the other two omit the setting. Tested with BUILD_TIMELESS=1, Intel RVP7 does not change. Change-Id: I6b393f0f2269f62b415456c17ba5962f46a1c5d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb 3 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43909/1 diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 60cbb4e..f8d533e 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,6 +20,7 @@ register "speed_shift_enable" = "1" # Enable DPTF + register "IoBufferOwnership" = "0" register "dptf_enable" = "1" # FSP Configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fa50283..98ab6df 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -3,7 +3,6 @@ # FSP Configuration register "EnableAzalia" = "1" register "DspEnable" = "0" - register "IoBufferOwnership" = "0" register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 355f199..4765c81 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -9,7 +9,6 @@ # FSP Configuration register "EnableAzalia" = "1" register "DspEnable" = "1" - register "IoBufferOwnership" = "0" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/43909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b393f0f2269f62b415456c17ba5962f46a1c5d1 Gerrit-Change-Number: 43909 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/kblrvp: Factor out `HeciEnabled`
by Angel Pons (Code Review) 07 Aug '20

07 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43908 ) Change subject: mb/intel/kblrvp: Factor out `HeciEnabled` ...................................................................... mb/intel/kblrvp: Factor out `HeciEnabled` RVP8 does not set it, and the other variants set it to zero. So, factor it out. It does not match the devicetree, so also add a FIXME comment. Tested with BUILD_TIMELESS=1, Intel RVP7 does not change. Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 4 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43908/1 diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 898739c..60cbb4e 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -127,7 +127,11 @@ device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01..355f199 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -10,7 +10,6 @@ register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 07d7385..a0984ea 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -14,7 +14,6 @@ register "gen2_dec" = "0x000c0201" # FSP Configuration - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 91abfe6..f15072c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -8,7 +8,6 @@ register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" -- To view, visit https://review.coreboot.org/c/coreboot/+/43908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Gerrit-Change-Number: 43908 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Log CSE FW Status Registers before triggering recovery
by Sridhar Siricilla (Code Review) 07 Aug '20

07 Aug '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43537 ) Change subject: soc/intel/common: Log CSE FW Status Registers before triggering recovery ...................................................................... soc/intel/common: Log CSE FW Status Registers before triggering recovery The patch log CSE Firmware Status Registers(FWSTS1, FWSTS2 & FWSTS3) before triggering recovery to help debugging. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I90e9f5897408bfc37a69cf0bb23bff18a146b9e2 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/43537/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a12f2d0..e51b8d6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -153,8 +153,16 @@ struct cse_bp_info bp_info; } __packed; +static void cse_log_status_registers(void) +{ + printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1:0x%x, HFSTS2:0x%x HFST3:0x%x\n", + me_read_config32(PCI_ME_HFSTS1), me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); +} + static void cse_trigger_recovery(uint8_t rec_sub_code) { + /* Log CSE Firmware Status Registers to help debugging */ + cse_log_status_registers(); if (CONFIG(VBOOT)) { struct vb2_context *ctx; ctx = vboot_get_context(); -- To view, visit https://review.coreboot.org/c/coreboot/+/43537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90e9f5897408bfc37a69cf0bb23bff18a146b9e2 Gerrit-Change-Number: 43537 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Paul Menzel (Code Review) 07 Aug '20

07 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/42794/16//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42794/16//COMMIT_MSG@21 PS16, Line 21: Please mention, what happens, if a GCC without the patch is used. Will the coreboot with Asan enabled fail to build, or build and fail to run? -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 16 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 07:35:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: support variant defined spd paths
by Nick Vaccaro (Code Review) 07 Aug '20

07 Aug '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44274 ) Change subject: mb/google/volteer: support variant defined spd paths ...................................................................... mb/google/volteer: support variant defined spd paths Allow variants to override the SPD_SOURCE_PATH to allow supporting different types of DDR. BUG=b:163065661 TEST="emerge-volteer coreboot" and verify all variants build. Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/spd/Makefile.inc 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44274/1 diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index e125994..d0cc720 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -4,7 +4,11 @@ ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/tigerlake/spd/lp4x/$(f)) +ifeq ($(SPD_SOURCE_PATH),) +SPD_SOURCE_PATH := src/soc/intel/tigerlake/spd/lp4x/ +endif + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), $$(SPD_SOURCE_PATH)/$(f)) # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) -- To view, visit https://review.coreboot.org/c/coreboot/+/44274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e Gerrit-Change-Number: 44274 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7
by Subrata Banik (Code Review) 07 Aug '20

07 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41674 ) Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7 ...................................................................... soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7 This patch fixes SATA device detection issue connected at Port > 2 on Intel H-PCH. TEST=Able to detect SATA device connect at Port 4 on CML-H. Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/41674/1 diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index d3f82ed..3e475d1 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -41,7 +41,7 @@ if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; - port_impl &= 0x07; /* bit 0-2 */ + port_impl &= 0xFF; /* bit 0-7 */ /* Port enable */ temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); -- To view, visit https://review.coreboot.org/c/coreboot/+/41674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e Gerrit-Change-Number: 41674 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020