coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
by Subrata Banik (Code Review) 07 Aug '20

07 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44205 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ...................................................................... soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE This patch ensures that bootblock/pch.c clear PCI_COMMAND_MASTER (BIT 2) prior to program PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1). Also performs beiow operations 1. Use pci_and_config16 instead pci_read and write 2. Use setbits32 instread mmio read and write Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 16 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44205/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index ae52f45..5dd9fb6 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -59,26 +59,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 6ebf910..0503455 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -40,26 +40,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 1260bc8..12b210d 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -44,26 +44,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9fc5ce1..e8cfc52 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -49,26 +49,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Gerrit-Change-Number: 44205 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/nvidia/optimus: Write _ROM method
by Patrick Rudolph (Code Review) 07 Aug '20

07 Aug '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: drivers/nvidia/optimus: Write _ROM method ...................................................................... Patch Set 4: > Patch Set 4: > > > Please explain why this is needed. The generic PCI driver should already do the same. > > 1. Without an ACPI name declared, a scope cannot be written to the device. > 2. Are you referring to device/pci_device.c? I see that it should call `pci_rom_ssdt`, but it hadn't been successful for me. Possibly due to 1? (or in my case, CB:43070. I'll test again.) In case the device has no acpi name/scope that's a SoC bug, as it simply doesn't provide those names yet. A console log will show what's missing. -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Prasun Gera Gerrit-Comment-Date: Fri, 07 Aug 2020 04:38:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/nvidia/optimus: Write _ROM method
by Benjamin Doron (Code Review) 07 Aug '20

07 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: drivers/nvidia/optimus: Write _ROM method ...................................................................... Patch Set 4: > Please explain why this is needed. The generic PCI driver should already do the same. 1. Without an ACPI name declared, a scope cannot be written to the device. 2. Are you referring to device/pci_device.c? I see that it should call `pci_rom_ssdt`, but it hadn't been successful for me. Possibly due to 1? (or in my case, CB:43070. I'll test again.) -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Prasun Gera Gerrit-Comment-Date: Fri, 07 Aug 2020 04:15:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/nvidia/optimus: Write _ROM method
by Patrick Rudolph (Code Review) 07 Aug '20

07 Aug '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: drivers/nvidia/optimus: Write _ROM method ...................................................................... Patch Set 4: Please explain why this is needed. The generic PCI driver should already do the same. -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Prasun Gera Gerrit-Comment-Date: Fri, 07 Aug 2020 03:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings"
by Paul Fagerburg (Code Review) 07 Aug '20

07 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Amanda Hwang, EricR Lai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43076 to review the following change. Change subject: Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings" ...................................................................... Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings" This reverts commit 3d813cbede650a89a519d5896652328e4ecf88c6. Reason for revert: the CL made the build unstable. Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04 --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc D src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 0 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43076/1 diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 343c7db..13269db 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -romstage-y += memory.c - bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c deleted file mode 100644 index 754c7a0..0000000 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> - -static const struct lpddr4x_cfg halvor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - - .ect = 1, /* Enable Early Command Training */ -}; - -const struct lpddr4x_cfg *variant_memory_params(void) -{ - return &halvor_memcfg; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04 Gerrit-Change-Number: 43076 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT
by Subrata Banik (Code Review) 07 Aug '20

07 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44062 ) Change subject: src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT ...................................................................... src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT This patch removes the unnecessary enforcement of MP PPI in ICL in order to have parity with other IA-SoC. Now it allows user to select USE_INTEL_FSP_MP_INIT if required. TEST=Able to build and boot ICL platform with either USE_INTEL_FSP_MP_INIT or USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selected. Change-Id: I25288a24cdf9dceec45a90e4e7233225a6cab508 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/fsp_params.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44062/1 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index d4485c6..0130d2c 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -71,8 +71,9 @@ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) params->Usb3OverCurrentPin[i] = 0; - /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); mainboard_silicon_init_params(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/44062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25288a24cdf9dceec45a90e4e7233225a6cab508 Gerrit-Change-Number: 44062 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Update dq/dqs mappings
by Amanda Hwang (Code Review) 07 Aug '20

07 Aug '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43988 ) Change subject: Update dq/dqs mappings ...................................................................... Update dq/dqs mappings Update dq/dqs mappings based on halvor schematics. BUG=b:162042254 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43988/1 diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db..343c7db 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c + bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000..51359e5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *(void) +{ + return &halvor_memcfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Gerrit-Change-Number: 43988 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: dedede: modify magolor config to SPI ROM size 16MB
by Ren Kuo (Code Review) 07 Aug '20

07 Aug '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44204 ) Change subject: dedede: modify magolor config to SPI ROM size 16MB ...................................................................... dedede: modify magolor config to SPI ROM size 16MB modify magolor config to SPI ROM size 16MB BUG=b:58540772 BRANCH=None TEST= build firmware and check the magolor bin size Change-Id: Ie7ddf698fde1dbf663859d5654946bc08abe737c --- M src/mainboard/google/dedede/Kconfig.name 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44204/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index bfcc427..40738a0 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -59,4 +59,3 @@ bool "-> Magolor" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP - select BOARD_ROMSIZE_KB_32768 -- To view, visit https://review.coreboot.org/c/coreboot/+/44204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7ddf698fde1dbf663859d5654946bc08abe737c Gerrit-Change-Number: 44204 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: gpio: Pull down HiZ pins after reading tristate GPIO strapping
by Julius Werner (Code Review) 06 Aug '20

06 Aug '20

Hello Furquan Shaikh, Alexandru Stan, Douglas Anderson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44253 to review the following change. Change subject: gpio: Pull down HiZ pins after reading tristate GPIO strapping ...................................................................... gpio: Pull down HiZ pins after reading tristate GPIO strapping People who know a lot more about electrons and stuff than I do tell me that leaving a HiZ pin floating without a pull resistor may waste power. So if we find a pin to be HiZ when reading tristate strapping GPIOs, we should make sure the internal pull-down is enabled when we're done with it. (For pins that are externally pulled high or low, we should continue to leave the internal pull disabled instead.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1669823c8a7faab536e0441cb4c6cfeb9f696189 --- M src/lib/gpio.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44253/1 diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 3f3ae60..801a3b3 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -114,6 +114,12 @@ printk(BIOS_DEBUG, "%c ", tristate_char[temp]); result = (result * 3) + temp; + /* Disable pull to avoid wasting power. For HiZ we leave the + pull-down enabled, since letting them float freely back and + forth may waste power in the SoC's GPIO input logic. */ + if (temp != Z) + gpio_input(gpio[index]); + /* * For binary_first we keep track of the normal ternary result * and whether we found any pin that was a Z. We also determine @@ -159,10 +165,6 @@ printk(BIOS_DEBUG, "= %d (%s base3 number system)\n", result, binary_first ? "binary_first" : "standard"); - /* Disable pull up / pull down to conserve power */ - for (index = 0; index < num_gpio; ++index) - gpio_input(gpio[index]); - return result; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1669823c8a7faab536e0441cb4c6cfeb9f696189 Gerrit-Change-Number: 44253 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Kangheui Won (Code Review) 06 Aug '20

06 Aug '20

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/44266/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44266/1//COMMIT_MSG@9 PS1, Line 9: Follow-up for CB:42473. > Please reference commit hashes, as that is, what git works with. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 22:39:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit August 2020