coreboot-gerrit August 2020

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Change in coreboot[master]: security/intel/txt: Avoid shifting by a negative value
by John Zhao (Code Review) 06 Aug '20

06 Aug '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44186 ) Change subject: security/intel/txt: Avoid shifting by a negative value ...................................................................... security/intel/txt: Avoid shifting by a negative value Coverity detects an integer handling issue with BAD_SHIFT. The inline function log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } could return -1, which causes shifting by a negative amount value and has undefined behavior. Add sanity check for the acm_header->size to avoid shifting negative value. Found-by: Coverity CID 1431124 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ic687349b14917e39d2a8186968037ca2521c7cdc --- M src/security/intel/txt/common.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44186/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index d3e18376..d641585 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -138,6 +138,7 @@ { const struct acm_header_v0 *acm_header = (struct acm_header_v0 *)ptr; uint32_t max_size_acm_area = 0; + const size_t acm_len = 0; if (acm_header->module_type != CHIPSET_ACM) return ACM_E_TYPE_NOT_MATCH; @@ -163,7 +164,8 @@ * SAFER MODE EXTENSIONS REFERENCE. * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D */ - const size_t acm_len = 1UL << log2_ceil((acm_header->size & 0xffffff) << 2); + if (acm_header->size != 0) + acm_len = 1UL << log2_ceil((acm_header->size & 0xffffff) << 2); if (max_size_acm_area < acm_len) { printk(BIOS_ERR, "TEE-TXT: BIOS ACM doesn't fit into AC execution region\n"); return ACM_E_NOT_FIT_INTO_CPU_ACM_MEM; -- To view, visit https://review.coreboot.org/c/coreboot/+/44186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic687349b14917e39d2a8186968037ca2521c7cdc Gerrit-Change-Number: 44186 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/pirq_routing.c: Drop unneeded `continue`
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44178 ) Change subject: arch/x86/pirq_routing.c: Drop unneeded `continue` ...................................................................... arch/x86/pirq_routing.c: Drop unneeded `continue` Change-Id: I714247da261d4dd1b6a722436d71404f9862e958 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/pirq_routing.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44178/1 diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 18a36cd..71d47d5 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -106,8 +106,6 @@ /* If it's not yet routed, use it */ if (!already_routed) break; - /* But if it was already routed, try the next one */ - continue; } /* Now we got our IRQ */ return irq; -- To view, visit https://review.coreboot.org/c/coreboot/+/44178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I714247da261d4dd1b6a722436d71404f9862e958 Gerrit-Change-Number: 44178 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Drop inexistent device from DMAR
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44147 ) Change subject: nb/intel/sandybridge: Drop inexistent device from DMAR ...................................................................... nb/intel/sandybridge: Drop inexistent device from DMAR There's no `function 1` on the iGPU device for this northbridge. Change-Id: I597446f703165447c3a0d0c1536583b08bc8450c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44147/1 diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index ccec36c..827f1f4 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -50,14 +50,12 @@ tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); tmp = current; current += acpi_create_igfx_rmrr(current); if (current != tmp) { current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_rmrr_fixup(tmp, current); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I597446f703165447c3a0d0c1536583b08bc8450c Gerrit-Change-Number: 44147 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Deduplicate PCIEXBAR decoding
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44122 ) Change subject: nb/intel/sandybridge: Deduplicate PCIEXBAR decoding ...................................................................... nb/intel/sandybridge: Deduplicate PCIEXBAR decoding We can use `decode_pcie_bar` instead, as other northbridges do. Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 7 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 755d446..2c98674 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -11,48 +11,19 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - struct device *const dev = pcidev_on_root(0, 0); - - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & (0xffffffffULL << 28); - max_buses = 256; - break; - case 1: /* 128M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 27); - max_buses = 128; - break; - case 2: /* 64M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 26); - max_buses = 64; - break; - default: /* RSVD */ - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, - max_buses - 1); + max_buses - 1); return current; } - static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 8f1db97..e670c09 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -40,7 +40,7 @@ static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 264d1e2..72724a3 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -177,6 +177,8 @@ void report_memory_config(void); enum platform_type get_platform_type(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include <device/device.h> struct acpi_rsdp; -- To view, visit https://review.coreboot.org/c/coreboot/+/44122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Gerrit-Change-Number: 44122 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: trogdor: SoC makefile BLOB support
by Paul Menzel (Code Review) 06 Aug '20

06 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile BLOB support ...................................................................... Patch Set 87: (3 comments) https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@7 PS87, Line 7: trogdor: SoC makefile BLOB support Please make it a statement by using a verb (in imperative mood). https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@7 PS87, Line 7: BLOB blob https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@8 PS87, Line 8: Please elaborate what blobs are added, and what they are. -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 87 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 10:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Paul Menzel (Code Review) 06 Aug '20

06 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/44266/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44266/1//COMMIT_MSG@9 PS1, Line 9: Follow-up for CB:42473. Please reference commit hashes, as that is, what git works with. Please do not forget the git commit message summary either. -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 10:26:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Kangheui Won (Code Review) 06 Aug '20

06 Aug '20

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Aug 2020 09:04:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by Ravi kumar (Code Review) 06 Aug '20

06 Aug '20

Ravi kumar has uploaded a new patch set (#78) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... HACK trogdor: optimize coreboot.rom for T32 flash script HACK Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/security/vboot/Makefile.inc A util/qualcomm/optimize_coreboot 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36278/78 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 78 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: SoC makefile BLOB support
by Ravi kumar (Code Review) 06 Aug '20

06 Aug '20

Ravi kumar has uploaded a new patch set (#87) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile BLOB support ...................................................................... trogdor: SoC makefile BLOB support Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/87 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 87 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/haswell/smmrelocate.c: Align with Broadwell
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42621 ) Change subject: cpu/intel/haswell/smmrelocate.c: Align with Broadwell ...................................................................... cpu/intel/haswell/smmrelocate.c: Align with Broadwell Change-Id: I8c2589141551028622a0ae1a183a74ebceb2acfb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42621/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 0f7585a..5e4e028 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -111,7 +111,7 @@ msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur @@ -284,6 +284,6 @@ * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, + pci_write_config8(pcidev_path_on_root(PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2589141551028622a0ae1a183a74ebceb2acfb Gerrit-Change-Number: 42621 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020