coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/skylake: set LT_LOCK_MEMORY only when using native MP init
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44243 ) Change subject: soc/intel/skylake: set LT_LOCK_MEMORY only when using native MP init ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78 Gerrit-Change-Number: 44243 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 19:54:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common,skl: lock LT_LOCK_MEMORY once, not per-thread
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44242 ) Change subject: soc/intel/common,skl: lock LT_LOCK_MEMORY once, not per-thread ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Gerrit-Change-Number: 44242 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 05 Aug 2020 19:54:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Hello Varshit B Pandya, build bot (Jenkins), Nico Huber, Patrick Georgi, Subrata Banik, Varun Joshi, Arthur Heymans, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36356 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST FSP does not set LT_LOCK_MEMORY when SkipMpInit=1. Therefore, set LT_LOCK_MEMORY at end of POST, when native MP init is used to protect SMM in accordance to Intel BWG. Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/finalize.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/36356/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver
by Tim Wawrzynczak (Code Review) 05 Aug '20

05 Aug '20

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver ...................................................................... mb/intel/jasperlake_rvp: Replace static camera ACPI by driver This change updates devicetree to enable SSDT generation for world facing and user facing cameras of jasperlake_rvp. Also removes DSDT changes related to the world facing camera. Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41758 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb D src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl 8 files changed, 111 insertions(+), 334 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 51e5e3c..d6fbe81 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -7,6 +7,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI @@ -14,6 +15,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_JASPERLAKE select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index f47424f..be883b4c 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -45,9 +45,6 @@ } #endif - /* Camera */ - #include <variant/acpi/camera.asl> - #include <southbridge/intel/common/acpi/sleepstates.asl> /* Mainboard specific */ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl deleted file mode 100644 index 1413998..0000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C5) -{ - PowerResource (FCPR, 0x00, 0x0000) - { - Name (STA, Zero) - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - If ((STA == Zero)) - { - /* Enable CLK1 */ - MCON(1, 1) // Clock 1, 19.2MHz - /* Pull PWREN(GPIO R6) high */ - STXS(GPP_D4) - Sleep(5) /* 5 us */ - /* Pull RST(GPIO H12) low */ - CTXS(GPP_C19) - Sleep(5) /* 5 us */ - /* Pull RST high */ - STXS(GPP_C19) - Sleep(5) /* 5 us */ - STA = 1 - } - } - - Method (_OFF, 0, Serialized) /* _OFF: Power Off */ - { - If ((STA == One)) - { - /* Pull RST low */ - CTXS(GPP_C19) - /* Pull PWREN low */ - CTXS(GPP_D4) - /* Disable CLK0 */ - MCOF(1) /* Clock 1 */ - STA = 0 - } - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA) - } - } - - Device (CAM1) - { - Name (_HID, "OVTI5675") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02 - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 0x1AD27480 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } - - Device (VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hadware ID */ - - Name (_UID, 0x03) /* _UID: Unique ID */ - - Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ - { - I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ - { - FCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package(0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9714" - } - } - }) - } -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl deleted file mode 100644 index 48650c9..0000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl deleted file mode 100644 index cebf15e..0000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (_SB.PCI0.IPU0) -{ - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C5.CAM1, - Zero, - Zero - } - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl deleted file mode 100644 index 013b26f..0000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) // _ADR: Address - - Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name - } -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index ae2aaf3..1681b71 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -158,7 +158,21 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device - device pci 05.0 on end #IPU + device pci 05.0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 @@ -292,8 +306,100 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 Cam 0 - device pci 19.1 on end # I2C #5 Cam 1 and VCM + device pci 19.0 on # I2C #4 Cam 0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI2740"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + end + device pci 19.1 on # I2C #5 Cam 1 and VCM + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + device i2c 0C on end + end + end + device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl deleted file mode 100644 index 318b0de..0000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/acpi/camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 27 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/mipi_camera: Handling IPU generic device
by Sugnan Prabhu S (Code Review) 05 Aug '20

05 Aug '20

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44025 ) Change subject: drivers/intel/mipi_camera: Handling IPU generic device ...................................................................... drivers/intel/mipi_camera: Handling IPU generic device Includes changes in mipi_camera driver to handle generic device which fixes the IPU device probing. Change-Id: I309edd065719cb8250f1241898bb5854004d2a9f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c 1 file changed, 22 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44025/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 51686d0..6f237a9 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -761,8 +761,6 @@ static void write_pci_camera_device(const struct device *dev) { - struct drivers_intel_mipi_camera_config *config = dev->chip_info; - if (dev->path.type != DEVICE_PATH_PCI) { printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); return; @@ -770,8 +768,7 @@ acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR_pci_device(dev); - acpigen_write_name_string("_DDN", config->device_type == INTEL_ACPI_CAMERA_CIO2 ? - "Camera and Imaging Subsystem" : "Imaging Unit"); + acpigen_write_name_string("_DDN", "Camera and Imaging Subsystem"); } static void write_i2c_camera_device(const struct device *dev, const char *scope) @@ -784,11 +781,6 @@ .resource = scope, }; - if (dev->path.type != DEVICE_PATH_I2C) { - printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); - return; - } - acpigen_write_device(acpi_device_name(dev)); /* add power resource */ @@ -930,18 +922,29 @@ acpigen_pop_len(); /* Guarded power resource operations scope */ } - /* Device */ - scope = acpi_device_scope(dev); - if (!scope) - return; + switch (dev->path.type) { + case DEVICE_PATH_I2C: + scope = acpi_device_scope(dev); + if (!scope) + return; - acpigen_write_scope(scope); - - if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || - config->device_type == INTEL_ACPI_CAMERA_IMGU) - write_pci_camera_device(dev); - else + acpigen_write_scope(scope); write_i2c_camera_device(dev, scope); + break; + case DEVICE_PATH_GENERIC: + pdev = dev->bus->dev; + scope = acpi_device_scope(pdev); + if (!scope) + return; + + acpigen_write_scope(scope); + write_pci_camera_device(pdev); + break; + default: + printk(BIOS_ERR, "Unsupported device type: %x\n" + "OS camera driver will likely not work\n", dev->path.type); + return; + } write_camera_device_common(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/44025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309edd065719cb8250f1241898bb5854004d2a9f Gerrit-Change-Number: 44025 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: sb/intel/i82801{gx,ix,jx}/acpi/lpc.asl: Drop dead code
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43220 ) Change subject: sb/intel/i82801{gx,ix,jx}/acpi/lpc.asl: Drop dead code ...................................................................... sb/intel/i82801{gx,ix,jx}/acpi/lpc.asl: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Also drop unnecessary #undef directive from one mainboard. Change-Id: I613e77723d108641f16ec732358849c3bc0e49e0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/getac/p470/dsdt.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl 4 files changed, 0 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/43220/1 diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index e6865dd..3fdc158 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #define ENABLE_TPM -#undef ENABLE_FDC // There is no Floppy for this laptop #include <acpi/acpi.h> DefinitionBlock( diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 0b0e987..bdb592f 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -216,32 +216,4 @@ Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 6fc2a84..c8f4b75 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -216,32 +216,4 @@ Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 20d9aaf..df62050 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -216,32 +216,4 @@ Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/43220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I613e77723d108641f16ec732358849c3bc0e49e0 Gerrit-Change-Number: 43220 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: {sb,soc}/intel/*/acpi/lpc.asl: Drop dead code
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43264 ) Change subject: {sb,soc}/intel/*/acpi/lpc.asl: Drop dead code ...................................................................... {sb,soc}/intel/*/acpi/lpc.asl: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Iddc635dc5bbc7a8b42e97f4e2f6d579a839d874b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl 7 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/43264/1 diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 02e1085..d0bd00a 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -102,8 +102,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 8b52bc7..0a22162 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -118,10 +118,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -/* - * Disable as Windows doesn't like it, and systems don't seem to use it. - * IRQNoFlags() { 8 } - */ }) } diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 4591bb0..fe0b11a 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -185,8 +185,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index bdb592f..07dea82 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -167,8 +167,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index c8f4b75..ec26fa1 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -167,8 +167,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index df62050..5335a60 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -167,8 +167,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index f296b5d..e9c1a30 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -192,8 +192,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/43264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddc635dc5bbc7a8b42e97f4e2f6d579a839d874b Gerrit-Change-Number: 43264 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: {nb,soc}/intel: Use get_current_microcode_rev() for ucode version
by Subrata Banik (Code Review) 05 Aug '20

05 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44175 ) Change subject: {nb,soc}/intel: Use get_current_microcode_rev() for ucode version ...................................................................... {nb,soc}/intel: Use get_current_microcode_rev() for ucode version This patch removes all redundant read microcode version implementation from SoC directory and refer from cpu/intel/microcode/microcode.c file. TEST=Able to get correct microcode version. Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/northbridge/intel/haswell/report_platform.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/jasperlake/bootblock/report_platform.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/tigerlake/bootblock/report_platform.c 8 files changed, 17 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44175/1 diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8ea4175..8c1b987 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <arch/cpu.h> +#include <cpu/intel/microcode.h> #include <string.h> #include <southbridge/intel/lynxpoint/pch.h> #include <device/pci_ops.h> @@ -14,7 +15,6 @@ u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; const char *mode[] = {"NOT ", ""}; index = 0x80000000; @@ -35,13 +35,9 @@ while (cpu_name[0] == ' ') cpu_name++; - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpu_id, - microcode_ver.hi, cpu_name); + get_current_microcode_rev(), cpu_name); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index a7b5873..e79e28a 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -3,6 +3,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> @@ -64,18 +65,12 @@ { uint32_t i, cpu_id, cpu_feature_flag; char cpu_name[49]; - msr_t microcode_ver; const char *support = "Supported"; const char *no_support = "Not Supported"; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -86,7 +81,8 @@ } printk(BIOS_INFO, "CPU: %s\n", cpu_name); - printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, microcode_ver.hi); + printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, + get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); printk(BIOS_INFO, "CPU: AES %s, TXT %s, VT %s\n", diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 1029395..3d122fc 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/pci.h> #include <string.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <soc/cpu.h> #include <soc/pch.h> @@ -98,11 +99,7 @@ while (cpu_name[0] == ' ') cpu_name++; - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -114,7 +111,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index b29cf7d..87b4be7 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> @@ -12,8 +13,6 @@ #include <soc/pch.h> #include <soc/pci_devs.h> -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -170,17 +169,11 @@ u32 i, cpu_id, cpu_feature_flag; char cpu_name[49]; int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -192,7 +185,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index f001e3b..898b0e3 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -12,8 +13,6 @@ #include <soc/pci_devs.h> #include <string.h> -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -83,7 +82,6 @@ const char cpu_not_found[] = "Platform info not available"; const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13]; @@ -108,11 +106,7 @@ cpu_name++; } - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -124,7 +118,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 10d7b0d..a907099 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> @@ -13,8 +14,6 @@ #include <soc/pci_devs.h> #include <string.h> -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -67,12 +66,7 @@ const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -84,7 +78,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index d306879..957b4c2 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/name.h> #include <device/pci.h> @@ -153,17 +154,11 @@ u32 i, cpu_id, cpu_feature_flag; char cpu_name[49]; int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -175,7 +170,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6acc0c3..03d65a4 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -9,6 +9,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -18,8 +19,6 @@ #include <soc/pci_devs.h> #include <string.h> -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -104,7 +103,6 @@ const char cpu_not_found[] = "Platform info not available"; const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13]; @@ -129,11 +127,7 @@ cpu_name++; } - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -145,7 +139,7 @@ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Gerrit-Change-Number: 44175 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voxel: Add Raydium touchscreen support
by David Wu (Code Review) 05 Aug '20

05 Aug '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44055 ) Change subject: mb/google/volteer/var/voxel: Add Raydium touchscreen support ...................................................................... mb/google/volteer/var/voxel: Add Raydium touchscreen support Enable the Raydium touchscreen support BUG=b:157402209 BRANCH=master TEST= 1. emerge-volteer coreboot chromeos-bootimage 2. boot up on voxel DUT and make sure the raydium TS can work. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44055/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0..43296d5 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -63,6 +63,20 @@ register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end end # I2C1 0xA0E9 device pci 15.2 on chip drivers/i2c/sx9310 -- To view, visit https://review.coreboot.org/c/coreboot/+/44055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 Gerrit-Change-Number: 44055 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: mb/google/vilboz: update telemetry settings for vilboz
by Peichao Li (Code Review) 05 Aug '20

05 Aug '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43278 ) Change subject: mb/google/vilboz: update telemetry settings for vilboz ...................................................................... mb/google/vilboz: update telemetry settings for vilboz update telemetry value for SDLE test result. BUG=b:160698427 BRANCH=None TEST=emerge-zork coreboot Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/43278/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 79f26f2..82271e3 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -18,6 +18,11 @@ # End : OPN Performance Configuration + register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_offset" = "0-1" + register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_offset" = "68" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/43278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf Gerrit-Change-Number: 43278 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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