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Change in coreboot[master]: drivers/generic/genesyslogic: Add driver for Genesys Loigc GL9763E
by Ben Chuang (Code Review) 05 Aug '20

05 Aug '20

Ben Chuang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43751 ) Change subject: drivers/generic/genesyslogic: Add driver for Genesys Loigc GL9763E ...................................................................... drivers/generic/genesyslogic: Add driver for Genesys Loigc GL9763E Set single request AXI, disable ASPM L0s and enable SSC. Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com> Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56 --- A src/drivers/generic/genesyslogic/Kconfig A src/drivers/generic/genesyslogic/Makefile.inc A src/drivers/generic/genesyslogic/gli9763e.c A src/drivers/generic/genesyslogic/gli9763e.h 4 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43751/1 diff --git a/src/drivers/generic/genesyslogic/Kconfig b/src/drivers/generic/genesyslogic/Kconfig new file mode 100644 index 0000000..e215cfa --- /dev/null +++ b/src/drivers/generic/genesyslogic/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_GLI9763E + bool diff --git a/src/drivers/generic/genesyslogic/Makefile.inc b/src/drivers/generic/genesyslogic/Makefile.inc new file mode 100644 index 0000000..9f5a2eb --- /dev/null +++ b/src/drivers/generic/genesyslogic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_GLI9763E) += gli9763e.c diff --git a/src/drivers/generic/genesyslogic/gli9763e.c b/src/drivers/generic/genesyslogic/gli9763e.c new file mode 100644 index 0000000..66b0af5 --- /dev/null +++ b/src/drivers/generic/genesyslogic/gli9763e.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for GenesysLogic 9763E */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include "gli9763e.h" + +static inline int pci_read_config_dword(struct device *dev, int where, + u32 *val) +{ + *val = pci_read_config32(dev, where); + return 0; +} + +static inline int pci_write_config_dword(struct device *dev, int where, + u32 val) +{ + pci_write_config32(dev, where, val); + return 0; +} + +static void gli_set_gl9763e(struct device *pdev) +{ + u32 value; + + pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); + value &= ~GLI_9763E_VHS_REV; + value |= ((u32)GLI_9763E_VHS_REV_W << GLI_9763E_VHS_REV_SHIFT); + pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); + + pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); + value |= GLI_9763E_SCR_AXI_REQ; + pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); + + pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG_REG_2, &value); + value &= ~GLI_9763E_CFG_REG_2_L0S; + pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG_REG_2, value); + + pci_read_config_dword(pdev, PCIE_GLI_9763E_PLL_CTL_2, &value); + value &= ~GLI_9763E_PLL_CTL_2_MAX_SSC; + value |= ((u32)MAX_SSC_30000PPM << GLI_9763E_PLL_CTL_2_MAX_SSC_SHIFT); + pci_write_config_dword(pdev, PCIE_GLI_9763E_PLL_CTL_2, value); + + pci_read_config_dword(pdev, PCIE_GLI_9763E_PLL_CTL, &value); + value |= GLI_9763E_PLL_CTL_SSC; + pci_write_config_dword(pdev, PCIE_GLI_9763E_PLL_CTL, value); + + pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); + value &= ~GLI_9763E_VHS_REV; + value |= ((u32)GLI_9763E_VHS_REV_R << GLI_9763E_VHS_REV_SHIFT); + pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); +} + +static void gli9763e_init(struct device *dev) +{ + printk(BIOS_INFO, "GL9763E: init\n"); + pci_dev_init(dev); + gli_set_gl9763e(dev); +} + +static struct device_operations gli9763e_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = gli9763e_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9763E, + 0 +}; + +static const struct pci_driver genesyslogic_gli9763e __pci_driver = { + .ops = &gli9763e_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_ops = { + CHIP_NAME("Genesys Logic GL9763E") +}; diff --git a/src/drivers/generic/genesyslogic/gli9763e.h b/src/drivers/generic/genesyslogic/gli9763e.h new file mode 100644 index 0000000..586870f --- /dev/null +++ b/src/drivers/generic/genesyslogic/gli9763e.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for GenesysLogic 9763E */ + +#include <types.h> + +#define PCI_VENDOR_ID_GLI 0x17a0 +#define PCI_DEVICE_ID_GLI_9763E 0xe763 + +#define PCIE_GLI_9763E_VHS 0x884 +#define GLI_9763E_VHS_REV 0xF00 +#define GLI_9763E_VHS_REV_SHIFT 16 +#define GLI_9763E_VHS_REV_R 0x0 +#define GLI_9763E_VHS_REV_M 0x1 +#define GLI_9763E_VHS_REV_W 0x2 +#define PCIE_GLI_9763E_SCR 0x8E0 +#define GLI_9763E_SCR_AXI_REQ BIT(9) + +#define PCIE_GLI_9763E_CFG_REG_2 0x8A4 +#define GLI_9763E_CFG_REG_2_L0S BIT(11) + +#define PCIE_GLI_9763E_PLL_CTL 0x938 +#define GLI_9763E_PLL_CTL_SSC BIT(19) + +#define PCIE_GLI_9763E_PLL_CTL_2 0x93C +#define GLI_9763E_PLL_CTL_2_MAX_SSC 0xFFFF0000 +#define GLI_9763E_PLL_CTL_2_MAX_SSC_SHIFT 16 +#define MAX_SSC_30000PPM 0xF5C3 -- To view, visit https://review.coreboot.org/c/coreboot/+/43751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56 Gerrit-Change-Number: 43751 Gerrit-PatchSet: 1 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-MessageType: newchange

6 30

Change in coreboot[master]: mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI node
by Lucas Chen (Code Review) 05 Aug '20

05 Aug '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44107 ) Change subject: mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI node ...................................................................... mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI node a. USI_REPORT_EN is no longer set to high in coreboot. Instead GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this pad as required. b. Add Delay after stop_gpio Low - 300ms BUG=b:162263398 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4 --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44107/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index a4cdac6..1f97d1c 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -79,6 +79,8 @@ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_delay_ms" = "300" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/44107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4 Gerrit-Change-Number: 44107 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: src: Use space after 'if', 'for'
by HAOUAS Elyes (Code Review) 05 Aug '20

05 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44173 ) Change subject: src: Use space after 'if', 'for' ...................................................................... src: Use space after 'if', 'for' Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/oprom/realmode/x86.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/roda/rk886ex/m3885.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/intel/skylake/sd.c 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44173/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5215934..d230d5c 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -130,7 +130,7 @@ { /* If the mainboard_interrupt_handler isn't called first. */ - if(!intXX_handler[i]) + if (!intXX_handler[i]) { /* Now set the default functions that are actually * needed to initialize the option roms. This is diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 8b54b99..33541b2 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -254,7 +254,7 @@ * we're out of here. * If it's not ready after a second, then we're in big trouble. */ - for(i = 0; i < 1000; i++){ + for (i = 0; i < 1000; i++){ if (gpio_get_value(dp_hpd)) break; mdelay(1); diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index d99db80..53fdfba 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -129,13 +129,13 @@ unsigned long *l = (void *)0x40000000; int bad = 0; unsigned long i; - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); l[i] = 0xffffffff - i; } - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); if (l[i] != (0xffffffff - i)){ @@ -177,7 +177,7 @@ } - for(i = 0; i < amt; i += 4){ + for (i = 0; i < amt; i += 4){ if (rdev_readat(boot_dev, &in, i, 4) < 4) { printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 6756e0e..59dd575 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -251,7 +251,7 @@ maxvars = m3885_get_variable(0x00); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); for (i = 0; i < ARRAY_SIZE(variables); i+=3) { - if(variables[i + 0] > maxvars) + if (variables[i + 0] > maxvars) continue; reg8 = m3885_get_variable(variables[i + 0]); reg8 &= ~(variables[i + 1]); diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 52166ed..489340a 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -498,7 +498,7 @@ FOR_EACH_BYTELANE(lane) { saved_dqs_center[channel][lane] /= RT_LOOPS; while (saved_dqs_center[channel][lane]--) { - if(rt_increment_dqs(&s->rt_dqs[channel][lane]) + if (rt_increment_dqs(&s->rt_dqs[channel][lane]) == CB_ERR) /* Should never happen */ printk(BIOS_ERR, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 332af32..57d5ef4 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -2166,7 +2166,7 @@ if (!fast_boot) { if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { - if(do_write_training(s)) + if (do_write_training(s)) die("DQ write training failed!"); } if (do_read_training(s)) diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 1f40d98..ba56182 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -8,7 +8,7 @@ config_t *config = config_of(dev); /* Nothing to write if GPIO is not set in devicetree */ - if(!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) + if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) return -1; if (config->sdcard_cd_gpio_default) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Gerrit-Change-Number: 44173 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src: Use space after switch, while
by HAOUAS Elyes (Code Review) 05 Aug '20

05 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44172 ) Change subject: src: Use space after switch, while ...................................................................... src: Use space after switch, while Change-Id: I150591aa3624895c4c321101a251547dd23d1db5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/t60/early_init.c M src/mainboard/lenovo/x60/dock.c M src/northbridge/intel/x4x/dq_dqs.c 5 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44172/1 diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 5414f8b..b8163e71 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ { /* Enable 14.318MHz CLK on CLKIN */ pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) return 1; diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 378d673..55be038 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -75,7 +75,7 @@ /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -102,7 +102,7 @@ /* startup 14.318MHz Clock */ dock_write_register(0x29, 0xa0); /* wait until clock is settled */ - while(!(dock_read_register(0x29) & 0x10) && timeout--) + while (!(dock_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -171,7 +171,7 @@ timeout = 1000; - while(!(inb(DLPC_CONTROL) & 8) && timeout--) + while (!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index ad2c58e..0a1ae53 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -25,7 +25,7 @@ pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); /* Enable COM1 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 25c1aac..3abe5c1 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -72,7 +72,7 @@ /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -99,7 +99,7 @@ timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while (!(inb(0x164c) & 8) && timeout--) udelay(1000); if (!timeout) { @@ -121,7 +121,7 @@ dock_write_register(0x29, 0x06); /* wait until clock is settled */ timeout = 1000; - while(!(dock_read_register(0x29) & 0x08) && timeout--) + while (!(dock_read_register(0x29) & 0x08) && timeout--) udelay(1000); if (!timeout) diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index dda4174..52166ed 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -220,7 +220,7 @@ expected_result == FAILING ? "failing" : "succeeding", channel); memset(pass_count, 0, sizeof(pass_count)); - while(succes_mask) { + while (succes_mask) { test_result = test_dq_aligned(s, channel); FOR_EACH_BYTELANE(lane) { if (((test_result >> lane) & 1) != expected_result) { @@ -390,7 +390,7 @@ FOR_EACH_BYTELANE(lane) rt_set_dqs(channel, lane, 0, &dqs_setting[lane]); - while(status == CB_SUCCESS) { + while (status == CB_SUCCESS) { test_result = test_dqs_aligned(s, channel); if (test_result == (expected_result == SUCCEEDING ? 0 : 0xff)) return CB_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/44172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I150591aa3624895c4c321101a251547dd23d1db5 Gerrit-Change-Number: 44172 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… PS2, Line 116: mp_run_on_all_cpus > For #1) Your right that LT_LOCK_MEMORY is package scoped. […] @Nate thank you very much! -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 09:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/google/puff Add device_index for NIC
by Andrew McRae (Code Review) 05 Aug '20

05 Aug '20

Andrew McRae has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37881 ) Change subject: mainboard/google/puff Add device_index for NIC ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c508139757c9e92986a9c83b1dd7dc05bdbefd6 Gerrit-Change-Number: 37881 Gerrit-PatchSet: 2 Gerrit-Owner: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: mb/{google/rambi,bostentech/gbty4}: Clean up mainboard.c
by Arthur Heymans (Code Review) 05 Aug '20

05 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44136 ) Change subject: mb/{google/rambi,bostentech/gbty4}: Clean up mainboard.c ...................................................................... mb/{google/rambi,bostentech/gbty4}: Clean up mainboard.c This cleans up some unneeded no-ops in the mainboard.c files of baytrail boards. Change-Id: I7662f6e860d672a99b211488122bec073cc78acf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/bostentech/gbyt4/mainboard.c M src/mainboard/google/rambi/mainboard.c 2 files changed, 2 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44136/1 diff --git a/src/mainboard/bostentech/gbyt4/mainboard.c b/src/mainboard/bostentech/gbyt4/mainboard.c index c385846..d0131bc 100644 --- a/src/mainboard/bostentech/gbyt4/mainboard.c +++ b/src/mainboard/bostentech/gbyt4/mainboard.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <acpi/acpi.h> #include <arch/interrupt.h> -#include <smbios.h> -#include <soc/gpio.h> -#include <bootstate.h> - -void mainboard_suspend_resume(void) -{ -} #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) @@ -102,27 +93,14 @@ } #endif -static void mainboard_init(struct device *dev) -{ - -} - -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - return 0; -} - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; #if CONFIG(VGA_ROM_RUN) - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); #endif } diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 0f729bf..41d9795 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -5,7 +5,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <acpi/acpi.h> #include <arch/interrupt.h> #include <smbios.h> #include "ec.h" @@ -14,10 +13,6 @@ #include <bootstate.h> #include <vendorcode/google/chromeos/chromeos.h> -void mainboard_suspend_resume(void) -{ -} - #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7662f6e860d672a99b211488122bec073cc78acf Gerrit-Change-Number: 44136 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: include/device/azalia_device.h: Include <stdint.h>
by HAOUAS Elyes (Code Review) 05 Aug '20

05 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44134 ) Change subject: include/device/azalia_device.h: Include <stdint.h> ...................................................................... include/device/azalia_device.h: Include <stdint.h> This file is using anly <stdint.h>. So replace <types.h> with <stdint.h>. Change-Id: Ib58532837941d5324b28bc2c607d70555ce9caee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/azalia_device.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/44134/1 diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9026091..fe23c70 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -3,10 +3,10 @@ #ifndef DEVICE_AZALIA_H #define DEVICE_AZALIA_H -#include <types.h> #include <acpi/acpi.h> #include <device/mmio.h> #include <device/device.h> +#include <stdint.h> void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; -- To view, visit https://review.coreboot.org/c/coreboot/+/44134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib58532837941d5324b28bc2c607d70555ce9caee Gerrit-Change-Number: 44134 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/zork: update DRAM SPD table for dirinboz
by Kevin Chiu (Code Review) 05 Aug '20

05 Aug '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43991 ) Change subject: mb/google/zork: update DRAM SPD table for dirinboz ...................................................................... mb/google/zork: update DRAM SPD table for dirinboz DRAM support list 0x00 HYNIX HMA851S6CJR6N-VK 0x01 HYNIX H5ANAG6NCMR-VKC 0x02 Samsung K4A8G165WC-BCTD 0x03 Samsung K4AAG165WB-MCTD 0x04 Samsung K4A8G165WC-BCWE 0x05 HYNIX H5AN8G6NDJR-XNC 0x06 HYNIX H5ANAG6NCMR-XNC 0x07 Micron MT40A512M16TB-062E:J 0x08 Micron MT40A1G16KD-062E:E 0x09 Samsung K4AAG165WA-BCTD 0x0A Samsung K4AAG165WA-BCWE BUG=b:161579679 BRANCH=master TEST=build Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- A src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43991/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc new file mode 100644 index 0000000..480e757 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 +APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010 +APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101 +APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x1 # 0b0110 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0111 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b1000 +APCB_SOURCES += samsung-K4AAG165WA-BCTD_x1 # 0b1001 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 -- To view, visit https://review.coreboot.org/c/coreboot/+/43991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299 Gerrit-Change-Number: 43991 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Subrata Banik (Code Review) 05 Aug '20

05 Aug '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... soc/intel/common: Include Alder Lake device IDs Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 19 files changed, 447 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 35c86d9..da41cb8 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2892,6 +2892,70 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 #define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0 0x7a00 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1 0x7a01 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2 0x7a02 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3 0x7a03 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4 0x7a04 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5 0x7a05 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6 0x7a06 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7 0x7a07 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8 0x7a08 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9 0x7a09 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10 0x7a0a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11 0x7a0b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12 0x7a0c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13 0x7a0d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14 0x7a0e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15 0x7a0f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16 0x7a10 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17 0x7a11 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18 0x7a12 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19 0x7a13 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20 0x7a14 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21 0x7a15 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22 0x7a16 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23 0x7a17 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24 0x7a18 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25 0x7a19 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26 0x7a1a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27 0x7a1b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28 0x7a1c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29 0x7a1d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3 0x7a83 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4 0x7a84 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5 0x7a85 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6 0x7a86 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7 0x7a87 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8 0x7a88 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9 0x7a89 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10 0x7a8a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11 0x7a8b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12 0x7a8c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13 0x7a8d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14 0x7a8e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15 0x7a8f +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16 0x7a90 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17 0x7a91 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18 0x7a92 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19 0x7a93 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20 0x7a94 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21 0x7a95 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22 0x7a96 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23 0x7a97 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24 0x7a98 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25 0x7a99 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26 0x7a9a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27 0x7a9b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28 0x7a9c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29 0x7a9d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30 0x7a9e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3130,6 +3194,48 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP4 0x51bb +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP5 0x51bc +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP6 0x51bd +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP7 0x51be +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP8 0x51bf +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP9 0x51b0 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP10 0x51b1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP11 0x51b2 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP12 0x51b3 + +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP1 0x7ab8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP2 0x7ab9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP3 0x7aba +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP4 0x7abb +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP5 0x7abc +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP6 0x7abd +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP7 0x7abe +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP8 0x7abf +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP9 0x7ab0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP10 0x7ab1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP11 0x7ab2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP12 0x7ab3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP13 0x7ab4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP14 0x7ab5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP15 0x7ab6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP16 0x7ab7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP17 0x7ac0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP18 0x7ac1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP19 0x7ac2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP20 0x7ac3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP21 0x7ac4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP22 0x7ac5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP23 0x7ac6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP24 0x7ac7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP25 0x7ac8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26 0x7ac9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27 0x7aca +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3184,6 +3290,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 #define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 +#define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3262,6 +3370,20 @@ #define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 #define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C0 0x51e8 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C1 0x51e9 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C2 0x51ea +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C3 0x51eb +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C4 0x51c5 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C5 0x51c6 + +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C0 0x7acc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C1 0x7acd +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C2 0x7ace +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C3 0x7acf +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C4 0x7afc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 @@ -3305,6 +3427,22 @@ #define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 #define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART0 0x51a8 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART1 0x51a9 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART2 0x51c7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART3 0x51da +#define PCI_DEVICE_ID_INTEL_ADP_P_UART4 0x51db +#define PCI_DEVICE_ID_INTEL_ADP_P_UART5 0x51dc +#define PCI_DEVICE_ID_INTEL_ADP_P_UART6 0x51dd + +#define PCI_DEVICE_ID_INTEL_ADP_S_UART0 0x7aa8 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART1 0x7aa9 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART2 0x7afe +#define PCI_DEVICE_ID_INTEL_ADP_S_UART3 0x7adc +#define PCI_DEVICE_ID_INTEL_ADP_S_UART4 0x7add +#define PCI_DEVICE_ID_INTEL_ADP_S_UART5 0x7ade +#define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 @@ -3355,6 +3493,24 @@ #define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb #define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4 +#define PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI 0x51a4 +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI0 0x51aa +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI1 0x51ab +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI2 0x51fb +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI3 0x51fd +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI4 0x51fe +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI5 0x51de +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI6 0x51df + +#define PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI 0x7aa4 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI0 0x7aaa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI1 0x7aab +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI2 0x7afb +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI3 0x7af9 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI4 0x7afa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI5 0x7aee +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI6 0x7aef + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3468,6 +3624,20 @@ #define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 #define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 +#define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff +#define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_1 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_2 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_3 0x4603 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_4 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_5 0x4611 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_6 0x4612 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_7 0x4613 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 + /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 #define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 @@ -3533,6 +3703,30 @@ #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 #define PCI_DEVICE_ID_INTEL_JSL_ID_4 0x4e14 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_1 0x4660 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_2 0x4664 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_3 0x4668 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_4 0x466c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_5 0x4670 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_6 0x4640 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_7 0x4644 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_8 0x4648 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_9 0x464c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_10 0x4650 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_11 0x4630 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_12 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_13 0x4673 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_14 0x4623 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_15 0x0060 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_3 0x4641 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_4 0x4649 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_5 0x4621 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_6 0x4609 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 @@ -3546,6 +3740,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 #define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 +#define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3564,6 +3760,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded +#define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed +#define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3581,6 +3779,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 #define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 +#define PCI_DEVICE_ID_INTEL_ADP_P_P2SB 0x7a20 +#define PCI_DEVICE_ID_INTEL_ADP_S_P2SB 0x7aa0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3593,6 +3793,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def +#define PCI_DEVICE_ID_INTEL_ADP_P_SRAM 0x7a6f +#define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3611,6 +3813,15 @@ #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 #define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1 0x7ad0 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2 0x7ad1 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3 0x7ad2 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4 0x7ad3 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5 0x7ad4 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6 0x7ad5 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7 0x7ad6 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8 0x7ad7 +#define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3636,6 +3847,14 @@ #define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 #define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 #define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE0 0x51e0 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE1 0x51e1 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE2 0x51e4 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE3 0x51e5 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE0 0x7ae8 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE1 0x7ae9 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE2 0x7aec +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE3 0x7aed /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3650,6 +3869,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee +#define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee +#define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 90bae16..1d6205c 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -75,7 +75,9 @@ { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0}, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index fecc71e..4b598e2 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -893,6 +893,14 @@ PCI_DEVICE_ID_INTEL_JSP_CSE1, PCI_DEVICE_ID_INTEL_JSP_CSE2, PCI_DEVICE_ID_INTEL_JSP_CSE3, + PCI_DEVICE_ID_INTEL_ADP_P_CSE0, + PCI_DEVICE_ID_INTEL_ADP_P_CSE1, + PCI_DEVICE_ID_INTEL_ADP_P_CSE2, + PCI_DEVICE_ID_INTEL_ADP_P_CSE3, + PCI_DEVICE_ID_INTEL_ADP_S_CSE0, + PCI_DEVICE_ID_INTEL_ADP_S_CSE1, + PCI_DEVICE_ID_INTEL_ADP_S_CSE2, + PCI_DEVICE_ID_INTEL_ADP_S_CSE3, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 2360d7d..776a22b 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -24,6 +24,15 @@ PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, PCI_DEVICE_ID_INTEL_JSP_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_P_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7b01ee6..38d41df 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -282,6 +282,19 @@ PCI_DEVICE_ID_INTEL_EHL_GT2_3, PCI_DEVICE_ID_INTEL_JSL_GT1, PCI_DEVICE_ID_INTEL_JSL_GT2, + PCI_DEVICE_ID_INTEL_ADL_GT0, + PCI_DEVICE_ID_INTEL_ADL_GT1, + PCI_DEVICE_ID_INTEL_ADL_GT1_1, + PCI_DEVICE_ID_INTEL_ADL_GT1_2, + PCI_DEVICE_ID_INTEL_ADL_GT1_3, + PCI_DEVICE_ID_INTEL_ADL_GT1_4, + PCI_DEVICE_ID_INTEL_ADL_GT1_5, + PCI_DEVICE_ID_INTEL_ADL_GT1_6, + PCI_DEVICE_ID_INTEL_ADL_GT1_7, + PCI_DEVICE_ID_INTEL_ADL_GT1_8, + PCI_DEVICE_ID_INTEL_ADL_GT1_9, + PCI_DEVICE_ID_INTEL_ADL_P_GT2, + PCI_DEVICE_ID_INTEL_ADL_S_GT1, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index ec70f52..e4bcf99 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -72,6 +72,15 @@ PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, PCI_DEVICE_ID_INTEL_JSP_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_P_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f7c241d..0de3bd3 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -250,6 +250,18 @@ PCI_DEVICE_ID_INTEL_JSP_I2C3, PCI_DEVICE_ID_INTEL_JSP_I2C4, PCI_DEVICE_ID_INTEL_JSP_I2C5, + PCI_DEVICE_ID_INTEL_ADP_P_I2C0, + PCI_DEVICE_ID_INTEL_ADP_P_I2C1, + PCI_DEVICE_ID_INTEL_ADP_P_I2C2, + PCI_DEVICE_ID_INTEL_ADP_P_I2C3, + PCI_DEVICE_ID_INTEL_ADP_P_I2C4, + PCI_DEVICE_ID_INTEL_ADP_P_I2C5, + PCI_DEVICE_ID_INTEL_ADP_S_I2C0, + PCI_DEVICE_ID_INTEL_ADP_S_I2C1, + PCI_DEVICE_ID_INTEL_ADP_S_I2C2, + PCI_DEVICE_ID_INTEL_ADP_S_I2C3, + PCI_DEVICE_ID_INTEL_ADP_S_I2C4, + PCI_DEVICE_ID_INTEL_ADP_S_I2C5, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e03d8bd..10dd19b 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -43,7 +43,8 @@ #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 #define CPUID_ELKHARTLAKE_A0 0x90660 - +#define CPUID_ALDERLAKE_S_A0 0x90670 +#define CPUID_ALDERLAKE_P_A0 0x906a0 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ea85911..212fd70 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -233,6 +233,70 @@ PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 4f4ab43..d97cd8d 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -143,6 +143,8 @@ PCI_DEVICE_ID_INTEL_TGL_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, PCI_DEVICE_ID_INTEL_JSP_P2SB, + PCI_DEVICE_ID_INTEL_ADP_P_P2SB, + PCI_DEVICE_ID_INTEL_ADP_S_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ada380e..e506905 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -291,6 +291,46 @@ PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP13, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP14, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP15, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP16, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP17, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP18, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP19, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP20, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP21, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP22, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP23, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP24, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP25, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 84e22a2..24f28e3 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -122,6 +122,8 @@ PCI_DEVICE_ID_INTEL_TGP_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, PCI_DEVICE_ID_INTEL_JSP_PMC, + PCI_DEVICE_ID_INTEL_ADP_P_PMC, + PCI_DEVICE_ID_INTEL_ADP_S_PMC, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ac8fefb..ae9f650 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -86,6 +86,8 @@ PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, PCI_DEVICE_ID_INTEL_JSP_SMBUS, + PCI_DEVICE_ID_INTEL_ADP_P_SMBUS, + PCI_DEVICE_ID_INTEL_ADP_S_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index cd5c4d4..295df09 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -87,6 +87,22 @@ PCI_DEVICE_ID_INTEL_JSP_SPI1, PCI_DEVICE_ID_INTEL_JSP_SPI2, PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_P_SPI0, + PCI_DEVICE_ID_INTEL_ADP_P_SPI1, + PCI_DEVICE_ID_INTEL_ADP_P_SPI2, + PCI_DEVICE_ID_INTEL_ADP_P_SPI3, + PCI_DEVICE_ID_INTEL_ADP_P_SPI4, + PCI_DEVICE_ID_INTEL_ADP_P_SPI5, + PCI_DEVICE_ID_INTEL_ADP_P_SPI6, + PCI_DEVICE_ID_INTEL_ADP_S_SPI0, + PCI_DEVICE_ID_INTEL_ADP_S_SPI1, + PCI_DEVICE_ID_INTEL_ADP_S_SPI2, + PCI_DEVICE_ID_INTEL_ADP_S_SPI3, + PCI_DEVICE_ID_INTEL_ADP_S_SPI4, + PCI_DEVICE_ID_INTEL_ADP_S_SPI5, + PCI_DEVICE_ID_INTEL_ADP_S_SPI6, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 67099df..426a5f7 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -41,6 +41,8 @@ PCI_DEVICE_ID_INTEL_TGL_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, PCI_DEVICE_ID_INTEL_JSP_SRAM, + PCI_DEVICE_ID_INTEL_ADP_P_SRAM, + PCI_DEVICE_ID_INTEL_ADP_S_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5da2800..195a8e7 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -381,6 +381,30 @@ PCI_DEVICE_ID_INTEL_JSL_ID_2, PCI_DEVICE_ID_INTEL_JSL_ID_3, PCI_DEVICE_ID_INTEL_JSL_ID_4, + PCI_DEVICE_ID_INTEL_ADL_S_ID_1, + PCI_DEVICE_ID_INTEL_ADL_S_ID_2, + PCI_DEVICE_ID_INTEL_ADL_S_ID_3, + PCI_DEVICE_ID_INTEL_ADL_S_ID_4, + PCI_DEVICE_ID_INTEL_ADL_S_ID_5, + PCI_DEVICE_ID_INTEL_ADL_S_ID_6, + PCI_DEVICE_ID_INTEL_ADL_S_ID_7, + PCI_DEVICE_ID_INTEL_ADL_S_ID_8, + PCI_DEVICE_ID_INTEL_ADL_S_ID_9, + PCI_DEVICE_ID_INTEL_ADL_S_ID_10, + PCI_DEVICE_ID_INTEL_ADL_S_ID_11, + PCI_DEVICE_ID_INTEL_ADL_S_ID_12, + PCI_DEVICE_ID_INTEL_ADL_S_ID_13, + PCI_DEVICE_ID_INTEL_ADL_S_ID_14, + PCI_DEVICE_ID_INTEL_ADL_S_ID_15, + PCI_DEVICE_ID_INTEL_ADL_P_ID_1, + PCI_DEVICE_ID_INTEL_ADL_P_ID_2, + PCI_DEVICE_ID_INTEL_ADL_P_ID_3, + PCI_DEVICE_ID_INTEL_ADL_P_ID_4, + PCI_DEVICE_ID_INTEL_ADL_P_ID_5, + PCI_DEVICE_ID_INTEL_ADL_P_ID_6, + PCI_DEVICE_ID_INTEL_ADL_P_ID_7, + PCI_DEVICE_ID_INTEL_ADL_P_ID_8, + PCI_DEVICE_ID_INTEL_ADL_P_ID_9, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index fac0577..ed4f9c6 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -274,6 +274,20 @@ PCI_DEVICE_ID_INTEL_JSP_UART0, PCI_DEVICE_ID_INTEL_JSP_UART1, PCI_DEVICE_ID_INTEL_JSP_UART2, + PCI_DEVICE_ID_INTEL_ADP_S_UART0, + PCI_DEVICE_ID_INTEL_ADP_S_UART1, + PCI_DEVICE_ID_INTEL_ADP_S_UART2, + PCI_DEVICE_ID_INTEL_ADP_S_UART3, + PCI_DEVICE_ID_INTEL_ADP_S_UART4, + PCI_DEVICE_ID_INTEL_ADP_S_UART5, + PCI_DEVICE_ID_INTEL_ADP_S_UART6, + PCI_DEVICE_ID_INTEL_ADP_P_UART0, + PCI_DEVICE_ID_INTEL_ADP_P_UART1, + PCI_DEVICE_ID_INTEL_ADP_P_UART2, + PCI_DEVICE_ID_INTEL_ADP_P_UART3, + PCI_DEVICE_ID_INTEL_ADP_P_UART4, + PCI_DEVICE_ID_INTEL_ADP_P_UART5, + PCI_DEVICE_ID_INTEL_ADP_P_UART6, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index a5cd9ca..54cb076 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -33,6 +33,8 @@ PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, PCI_DEVICE_ID_INTEL_JSP_XDCI, + PCI_DEVICE_ID_INTEL_ADP_P_XDCI, + PCI_DEVICE_ID_INTEL_ADP_S_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9d312d0..47f2567 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -121,6 +121,8 @@ PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, PCI_DEVICE_ID_INTEL_JSP_XHCI, + PCI_DEVICE_ID_INTEL_ADP_P_XHCI, + PCI_DEVICE_ID_INTEL_ADP_S_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit August 2020