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Change in coreboot[master]: sb/intel/i82801gx: Use PCI bitwise ops
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42191 ) Change subject: sb/intel/i82801gx: Use PCI bitwise ops ...................................................................... sb/intel/i82801gx: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c 9 files changed, 50 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/42191/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 205fb0d..0ce3316 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -196,37 +196,21 @@ struct resource *res; u32 codec_mask; u8 reg8; - u32 reg32; // ESD - reg32 = pci_read_config32(dev, 0x134); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x134, reg32); + pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16); // Link1 description - reg32 = pci_read_config32(dev, 0x140); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x140, reg32); + pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16); // Port VC0 Resource Control Register - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~0x000000ff, 1); // VCi traffic class - reg8 = pci_read_config8(dev, 0x44); - reg8 |= (7 << 0); // TC7 - pci_write_config8(dev, 0x44, reg8); + pci_or_config8(dev, 0x44, 7 << 0); // TC7 // VCi Resource Control - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - reg32 |= (1 << 24); // VCi ID - reg32 |= (0x80 << 0); // VCi map - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -246,14 +230,11 @@ reg8 = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status #if 0 /* Set routing pin */ pci_write_config32(dev, 0xf8, 0x0); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index b0f73e8..308dfc8 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -6,13 +6,8 @@ static void enable_spi_prefetch(void) { - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); + /* Prefetching and Caching Enabled */ + pci_update_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL, ~(3 << 2), 2 << 2); } void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a913873..61fc8d9 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -61,9 +61,6 @@ #if ENV_ROMSTAGE void i82801gx_early_init(void) { - uint8_t reg8; - uint32_t reg32; - enable_smbus(); /* Setting up Southbridge. In the northbridge code. */ @@ -84,22 +81,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD); /* USB transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17)); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27)); /* Enable IOAPIC */ RCBA8(OIC) = 0x03; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 0bfe8eb..e11e89d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -252,18 +252,13 @@ static void i82801gx_configure_cstates(struct device *dev) { - u8 reg8; - - reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration - reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown - pci_write_config8(dev, 0xa9, reg8); + // Enable Popup & Popdown + pci_or_config8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2)); // Set Deeper Sleep configuration to recommended values - reg8 = pci_read_config8(dev, 0xaa); - reg8 &= 0xf0; - reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us - reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us - pci_write_config8(dev, 0xaa, reg8); + // Deeper Sleep to Stop CPU: 34-40us + // Deeper Sleep to Sleep: 15us + pci_update_config8(dev, 0xaa, ~0x0f, (2 << 2) | (2 << 0)); } static void i82801gx_rtc_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 7472438..d72bd81 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -10,29 +10,21 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); - /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 &= ~PCI_BRIDGE_CTL_SERR; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + /* Disable parity error response and SERR */ + pci_and_config16(dev, PCI_BRIDGE_CONTROL, + ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR)); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); + pci_update_config8(dev, SMLT, 0x07, 0x04 << 3); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index adf0e49..c297ac9 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -41,7 +41,6 @@ static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); @@ -50,41 +49,29 @@ /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it - pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); + pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, + PCI_BRIDGE_CTL_NO_ISA); /* Enable IO xAPIC on this PCIe port */ - reg32 = pci_read_config32(dev, 0xd8); - reg32 |= (1 << 7); - pci_write_config32(dev, 0xd8, reg32); + pci_or_config32(dev, 0xd8, 1 << 7); /* Enable Backbone Clock Gating */ - reg32 = pci_read_config32(dev, 0xe1); - reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); - pci_write_config32(dev, 0xe1, reg32); + pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); /* Set VC0 transaction class */ - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~0x000000ff, 1); /* Mask completion timeouts */ - reg32 = pci_read_config32(dev, 0x148); - reg32 |= (1 << 14); - pci_write_config32(dev, 0x148, reg32); + pci_or_config32(dev, 0x148, 1 << 14); /* Enable common clock configuration */ // Are there cases when we don't want that? - reg16 = pci_read_config16(dev, 0x50); - reg16 |= (1 << 6); - pci_write_config16(dev, 0x50, reg16); + pci_or_config16(dev, 0x50, 1 << 6); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); @@ -95,7 +82,7 @@ printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16); diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index c98a645..1718253 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -61,11 +61,10 @@ if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ - pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); + pci_update_config8(dev, SATA_MAP, (u8)~0xc3, 0x40); } else { - /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); + /* Set map to ide */ + pci_and_config8(dev, SATA_MAP, (u8)~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -73,7 +72,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u8 ports; /* Get the chip configuration */ @@ -96,11 +94,10 @@ case SATA_MODE_IDE_LEGACY_COMBINED: printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0); + /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); pci_write_config8(dev, 0x09, 0x80); @@ -149,9 +146,7 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -192,23 +187,15 @@ pci_write_config8(dev, 0xa0, 0x78); pci_write_config8(dev, 0xa6, 0x22); pci_write_config8(dev, 0xa0, 0x88); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0c0c0; - reg32 |= 0x1b1b1212; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0c0c0, 0x1b1b1212); pci_write_config8(dev, 0xa0, 0x8c); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0ff00; - reg32 |= 0x121200aa; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0ff00, 0x121200aa); pci_write_config8(dev, 0xa0, 0x00); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); /* Sata Initialization Register */ - reg32 = pci_read_config32(dev, SATA_IR); - reg32 |= SCRD; // due to some bug - pci_write_config32(dev, SATA_IR, reg32); + pci_or_config32(dev, SATA_IR, SCRD); // due to some bug } static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8ce57df..08ba3d7 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -9,8 +9,6 @@ static void usb_init(struct device *dev) { - u8 reg8; - /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); @@ -20,9 +18,7 @@ pci_write_config8(dev, 0xca, 0x00); // Yes. Another Erratum - reg8 = pci_read_config8(dev, 0xca); - reg8 |= (1 << 0); - pci_write_config8(dev, 0xca, reg8); + pci_or_config8(dev, 0xca, 1 << 0); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7..0a66136 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -14,19 +14,13 @@ struct resource *res; u8 *base; u32 reg32; - u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 31) | (1 << 27)); - reg32 = pci_read_config32(dev, 0xfc); - reg32 &= ~(3 << 2); - reg32 |= (2 << 2) | (1 << 29) | (1 << 17); - pci_write_config32(dev, 0xfc, reg32); + pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ res = find_resource(dev, 0x10); @@ -35,9 +29,7 @@ write32(base + 0x24, reg32); /* workaround */ - reg8 = pci_read_config8(dev, 0x84); - reg8 |= (1 << 4); - pci_write_config8(dev, 0x84, reg8); + pci_or_config8(dev, 0x84, 1 << 4); printk(BIOS_DEBUG, "done.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Gerrit-Change-Number: 42191 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43687 ) Change subject: nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax ...................................................................... nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax This brings Ironlake closer to Sandy Bridge. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/acpi/hostbridge.asl 1 file changed, 28 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43687/1 diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 6a59fb5..324fb35 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -92,17 +91,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -122,23 +120,23 @@ Store ("Set TDP Down", Debug) /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100 /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -158,23 +156,23 @@ Store ("Set TDP Nominal", Debug) /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100 /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -305,20 +303,20 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - ShiftRight (Local0, 4, Local0) - Store (^MCHC.TUUD, Local1) + Local0 = ^MCHC.TLUD + Local0 >>= 4 + Local1 = ^MCHC.TUUD // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) - ShiftRight (Local0, 6, Local0) + Local0 = ^MCHC.TOM + Local0 >>= 6 } - ShiftLeft (Local0, 20, Local0) - Store (Local0, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) + Local0 <<= 20 + PMIN = Local0 + PLEN = PMAX - PMIN + 1 Return (MCRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/43687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6 Gerrit-Change-Number: 43687 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: nb/intel/sandybridge: Update to ASL 2.0 syntax
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44151 ) Change subject: nb/intel/sandybridge: Update to ASL 2.0 syntax ...................................................................... nb/intel/sandybridge: Update to ASL 2.0 syntax Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44151/1 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 0f70f8c..977d7a7 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -151,12 +151,12 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ CTCS = CTCD @@ -187,12 +187,12 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ PL1V = CTDN -- To view, visit https://review.coreboot.org/c/coreboot/+/44151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb Gerrit-Change-Number: 44151 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Change signature of `decode_pciebar`
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44141 ) Change subject: nb/intel/x4x: Change signature of `decode_pciebar` ...................................................................... nb/intel/x4x: Change signature of `decode_pciebar` Rename it and make it return an int, like other northbridges do. Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44141/1 diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 57173fd..c700076 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -12,7 +12,7 @@ u32 pciexbar = 0; u32 length = 0; - if (!decode_pciebar(&pciexbar, &length)) + if (!decode_pcie_bar(&pciexbar, &length)) return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e..6d40faf 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -57,7 +57,7 @@ } } -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 9c32dae..99b1f21 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -111,7 +111,7 @@ top32memk - (DEFAULT_HECIBAR >> 10), IORESOURCE_RESERVE); - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, index++, pcie_config_base >> 10, diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 133f31d..bb51c60 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -331,7 +331,7 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); -u8 decode_pciebar(u32 *const base, u32 *const len); +int decode_pcie_bar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); -- To view, visit https://review.coreboot.org/c/coreboot/+/44141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Gerrit-Change-Number: 44141 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Deduplicate PCIEXBAR decoding
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44120 ) Change subject: nb/intel/haswell: Deduplicate PCIEXBAR decoding ...................................................................... nb/intel/haswell: Deduplicate PCIEXBAR decoding Add `decode_pcie_bar` for consistency with other Intel northbridges. Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c 3 files changed, 11 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc..cc4487c 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -2,6 +2,7 @@ #include <types.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <acpi/acpi.h> #include <device/device.h> #include <device/pci_ops.h> @@ -10,44 +11,12 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - u32 mask; + u32 length, pciexbar; - dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & mask; - max_buses = 256; - break; - case 1: /* 128M */ - mask |= (1 << 27); - pciexbar = pciexbar_reg & mask; - max_buses = 128; - break; - case 2: /* 64M */ - mask |= (1 << 27) | (1 << 26); - pciexbar = pciexbar_reg & mask; - max_buses = 64; - break; - default: /* RSVD */ - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 5e28336..9a99c2a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -157,6 +157,8 @@ void report_platform_info(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include <device/device.h> struct acpi_rsdp; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0a5af4f..e1c26d1 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -51,6 +51,11 @@ return 0; } +int decode_pcie_bar(u32 *const base, u32 *const len) +{ + return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len); +} + static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) -- To view, visit https://review.coreboot.org/c/coreboot/+/44120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Gerrit-Change-Number: 44120 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/pineview: Refactor `decode_pcie_bar`
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44140 ) Change subject: nb/intel/pineview: Refactor `decode_pcie_bar` ...................................................................... nb/intel/pineview: Refactor `decode_pcie_bar` Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS, Foxconn D41S remains identical. Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/memmap.c 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/44140/1 diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index ab0f31b..146fff2 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -19,11 +19,7 @@ { *base = 0; *len = 0; - const pci_devfn_t dev = HOST_BRIDGE; - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; + const struct { u16 num_buses; u32 addr_mask; @@ -34,7 +30,7 @@ {0, 0}, }; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR); /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) { @@ -42,9 +38,9 @@ return 0; } - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; + const u32 index = (pciexbar_reg >> 1) & 3; + const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask; + const int max_buses = busmask[index].num_buses; if (!pciexbar) { printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/44140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc Gerrit-Change-Number: 44140 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: Change signature of `decode_pciebar`
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44139 ) Change subject: nb/intel/pineview: Change signature of `decode_pciebar` ...................................................................... nb/intel/pineview: Change signature of `decode_pciebar` Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/pineview.h 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44139/1 diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 2edd462..9d85717 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -11,7 +11,7 @@ { u32 length, pciexbar; - if (!decode_pciebar(&pciexbar, &length)) + if (!decode_pcie_bar(&pciexbar, &length)) return current; const int max_buses = length / MiB; diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index bcf1487..ab0f31b 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -15,7 +15,7 @@ #include <cpu/intel/smm_reloc.h> #include <stdint.h> -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index e005bc9..a04b62b 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -114,7 +114,7 @@ (touud - top32memk) >> 10); } - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", pcie_config_base, pcie_config_size); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index d557d22..47257dd 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -185,7 +185,7 @@ void pineview_early_init(void); u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); -u8 decode_pciebar(u32 *const base, u32 *const len); +int decode_pcie_bar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ void get_mb_spd_addrmap(u8 *spd_addr_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/44139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Gerrit-Change-Number: 44139 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: Use `MiB` definition
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44124 ) Change subject: nb/intel/pineview: Use `MiB` definition ...................................................................... nb/intel/pineview: Use `MiB` definition Also constify a local variable while we're at it. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c 3 files changed, 10 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 5becf8d..2edd462 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpigen.h> #include <acpi/acpi.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <northbridge/intel/pineview/pineview.h> #include <types.h> @@ -9,12 +10,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) { u32 length, pciexbar; - int max_buses; if (!decode_pciebar(&pciexbar, &length)) return current; - max_buses = length >> 20; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index ad89aef..bcf1487 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -3,6 +3,7 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> @@ -51,7 +52,7 @@ } *base = pciexbar; - *len = max_buses << 20; + *len = max_buses * MiB; return 1; } @@ -87,11 +88,11 @@ switch ((esmramc >> 1) & 3) { case 0: - return 1 << 20; + return 1 * MiB; case 1: - return 2 << 20; + return 2 * MiB; case 2: - return 8 << 20; + return 8 * MiB; case 3: default: die("Bad TSEG setting.\n"); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 856eab3..e005bc9 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -18,7 +18,7 @@ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ -static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_base_k = 0xa0000 / KiB; static void add_fixed_resources(struct device *dev, int index) { @@ -33,8 +33,8 @@ | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); } static void mch_domain_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd Gerrit-Change-Number: 44124 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: [DONOTMERGE] security/intel/txt: Add Intel TXT support
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43617 ) Change subject: [DONOTMERGE] security/intel/txt: Add Intel TXT support ...................................................................... Abandoned TXT support is now merged -- To view, visit https://review.coreboot.org/c/coreboot/+/43617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f162f55350b5cb7f7483d0b87d0ba3ce0fcfa5 Gerrit-Change-Number: 43617 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/zork/var/vilboz: Enable support for garaged stylus
by Furquan Shaikh (Code Review) 04 Aug '20

04 Aug '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44153 ) Change subject: mb/google/zork/var/vilboz: Enable support for garaged stylus ...................................................................... mb/google/zork/var/vilboz: Enable support for garaged stylus This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for vilboz. BUG=b:157628650 Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44153/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 17cc17c..f9b7077 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -100,6 +100,18 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" -- To view, visit https://review.coreboot.org/c/coreboot/+/44153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Gerrit-Change-Number: 44153 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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