coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/broadwell: Add RMRRs after all DRHDs
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44111 ) Change subject: soc/intel/broadwell: Add RMRRs after all DRHDs ...................................................................... soc/intel/broadwell: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c 1 file changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44111/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index c76c8d2..760842b 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -435,22 +435,19 @@ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfxvtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4); + + /* First, add DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } /* VTVC0BAR has to be set, enabled, and in 32-bit space */ @@ -468,6 +465,16 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f Gerrit-Change-Number: 44111 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44110 ) Change subject: soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs ...................................................................... soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I4ee3ae6c45e2a2c921fbccbb62b853e4a141a58d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c 1 file changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44110/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 96a142a..ee1a543 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -171,19 +171,15 @@ unsigned long tmp; /* IGD has to be enabled, GFXVTBAR set and enabled. */ - if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { + const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten; + + /* First, add DRHD entries */ + if (emit_igd) { tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } /* DEFVTBAR has to be set and enabled. */ @@ -210,6 +206,15 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ee3ae6c45e2a2c921fbccbb62b853e4a141a58d Gerrit-Change-Number: 44110 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44109 ) Change subject: nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs ...................................................................... nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44109/1 diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 2cfb9ee..755d446 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -73,16 +73,35 @@ { const struct device *const igfx = pcidev_on_root(2, 0); + /* First, add DRHD entries */ if (igfx && igfx->enabled) { - unsigned long tmp; + const unsigned long tmp = current; - tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); + } - tmp = current; + { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* Then, add RMRR entries after all DRHD entries */ + if (igfx && igfx->enabled) { + const unsigned long tmp = current; + current += acpi_create_igfx_rmrr(current); if (current != tmp) { current += acpi_create_dmar_ds_pci(current, 0, 2, 0); @@ -91,19 +110,6 @@ } } - const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); - - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); - - acpi_dmar_drhd_fixup(tmp, current); - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0 Gerrit-Change-Number: 44109 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Remove dead assignments
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44150 ) Change subject: nb/intel/x4x: Remove dead assignments ...................................................................... nb/intel/x4x: Remove dead assignments The call to `decode_pcie_bar` always initializes these values. Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/acpi.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44150/1 diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index c700076..4088e75 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -9,8 +9,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar = 0; - u32 length = 0; + u32 pciexbar, length; if (!decode_pcie_bar(&pciexbar, &length)) return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/44150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0 Gerrit-Change-Number: 44150 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/acpi: clean up global NVS
by Felix Held (Code Review) 04 Aug '20

04 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44154 ) Change subject: soc/amd/picasso/acpi: clean up global NVS ...................................................................... soc/amd/picasso/acpi: clean up global NVS Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge to Picasso. This patch removes the unused fields. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h 2 files changed, 20 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44154/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 8147619..6e63b8d 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -17,25 +17,15 @@ /* Miscellaneous */ Offset (0x00), PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community - TMPS, 8, // 0x2B - Temperature Sensor ID - TLVL, 8, // 0x2C - Throttle Level Limit - FLVL, 8, // 0x2D - Current FAN Level - TCRT, 8, // 0x2E - Critical Threshold - TPSV, 8, // 0x2F - Passive Threshold - TMAX, 8, // 0x30 - CPU Tj_max - Offset (0x34), // 0x34 - AOAC Device Enables + LIDS, 8, // 0x01 - LID State + PWRS, 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold + Offset (0x20), // 0x20 - AOAC Device Enables , 7, IC2E, 1, // I2C2, 7 IC3E, 1, // I2C3, 8 diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 214ab1d..b6708c8 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -17,27 +17,17 @@ struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ - uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ - uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad relative offset */ - uint8_t tmps; /* 0x2B - Temperature Sensor ID */ - uint8_t tlvl; /* 0x2C - Throttle Level Limit */ - uint8_t flvl; /* 0x2D - Current FAN Level */ - uint8_t tcrt; /* 0x2E - Critical Threshold */ - uint8_t tpsv; /* 0x2F - Passive Threshold */ - uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t pad1[3]; - aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint8_t unused[200]; + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ + uint8_t pad1[6]; + aoac_devs_t aoac; /* 0x20 - AOAC device enables */ + uint8_t unused[220]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/c/coreboot/+/44154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d Gerrit-Change-Number: 44154 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Refactor `decode_pciebar`
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44142 ) Change subject: nb/intel/x4x: Refactor `decode_pciebar` ...................................................................... nb/intel/x4x: Refactor `decode_pciebar` Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/memmap.c 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/44142/1 diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 6d40faf..8a69ba8 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -61,11 +61,7 @@ { *base = 0; *len = 0; - const pci_devfn_t dev = PCI_DEV(0, 0, 0); - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; + const struct { u16 num_buses; u32 addr_mask; @@ -76,16 +72,16 @@ {0, 0}, }; - pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO); if (!(pciexbar_reg & 1)) { printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); return 0; } - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; + const u32 index = (pciexbar_reg >> 1) & 3; + const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask; + const int max_buses = busmask[index].num_buses; if (!pciexbar) { printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/44142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860 Gerrit-Change-Number: 44142 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44146 ) Change subject: nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding ...................................................................... nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding Other northbridges have a `decode_pcie_bar` function. Since it's not needed anywhere else, keep it as a static function for now. Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/acpi.c 1 file changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44146/1 diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index c954086..688dd5f 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -3,48 +3,48 @@ #define __SIMPLE_DEVICE__ #include <types.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <device/pci_ops.h> #include "ironlake.h" -unsigned long acpi_fill_mcfg(unsigned long current) +static int decode_pcie_bar(u32 *const base, u32 *const len) { - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + *base = 0; + *len = 0; - pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); - // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) - return current; + return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; + case 0: /* 256MB */ + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } - if (!pciexbar) + return 0; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + u32 length, pciexbar; + + if (!decode_pcie_bar(&pciexbar, &length)) return current; + const int max_buses = length / MiB; + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/44146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Gerrit-Change-Number: 44146 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Deduplicate PCIEXBAR decoding
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44145 ) Change subject: nb/intel/i945: Deduplicate PCIEXBAR decoding ...................................................................... nb/intel/i945: Deduplicate PCIEXBAR decoding We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c 3 files changed, 7 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44145/1 diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 75a6da5..232575f 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -3,46 +3,19 @@ #include <types.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <device/pci_ops.h> #include "i945.h" unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 5275d1b..64a945d 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +int decode_pcie_bar(u32 *const base, u32 *const len); + /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 20c9116..103b40f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -12,7 +12,7 @@ #include <cpu/intel/smm_reloc.h> #include "i945.h" -static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Gerrit-Change-Number: 44145 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Refactor `get_pcie_bar`
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44144 ) Change subject: nb/intel/i945: Refactor `get_pcie_bar` ...................................................................... nb/intel/i945: Refactor `get_pcie_bar` Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/northbridge.c 1 file changed, 20 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/44144/1 diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 0e8ea7e..20c9116 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/pci_ops.h> #include <stdint.h> @@ -11,32 +12,33 @@ #include <cpu/intel/smm_reloc.h> #include "i945.h" -static int get_pcie_bar(u32 *base) +static int decode_pcie_bar(u32 *const base, u32 *const len) { - struct device *dev; - u32 pciexbar_reg; - *base = 0; + *len = 0; - dev = pcidev_on_root(0, 0); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - return 256; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - return 128; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - return 64; + case 0: /* 256MB */ + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } return 0; @@ -162,13 +164,12 @@ static void mc_read_resources(struct device *dev) { - u32 pcie_config_base; - int buses; + u32 pcie_config_base, pcie_config_len; pci_dev_read_resources(dev); - buses = get_pcie_bar(&pcie_config_base); - if (buses) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { + const int buses = pcie_config_len / MiB; struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854 Gerrit-Change-Number: 44144 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Use ASL 2.0 syntax
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44152 ) Change subject: nb/intel/haswell: Use ASL 2.0 syntax ...................................................................... nb/intel/haswell: Use ASL 2.0 syntax Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44152/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index b8a1af8..1d4eba6 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -173,12 +173,12 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ CTCS = CTCD @@ -214,7 +214,7 @@ Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ PL1V = CTDN -- To view, visit https://review.coreboot.org/c/coreboot/+/44152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991 Gerrit-Change-Number: 44152 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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