coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Benjamin Doron (Code Review) 04 Aug '20

04 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/38318/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38318/9//COMMIT_MSG@11 PS9, Line 11: Tested on a Skylake-U laptop. > Please give the name. Done. Note that it's not in the tree yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 19:11:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Benjamin Doron (Code Review) 04 Aug '20

04 Aug '20

Hello build bot (Jenkins), Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38318 to look at the new patch set (#10). Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... soc/intel/skylake: Call mainboard ACPI sleep methods Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/platform.asl 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38318/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Tim Wawrzynczak (Code Review) 04 Aug '20

04 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@7 PS3, Line 7: nem NEM https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. does this mean that the enhanced mode never worked correctly in the first place? IOW, we were writing to reserved bits in IA32_PQR_ASSOC which didn't do anything here. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:52:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Paul Menzel (Code Review) 04 Aug '20

04 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/38318/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38318/9//COMMIT_MSG@11 PS9, Line 11: Tested on a Skylake-U laptop. Please give the name. -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:50:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Tim Wawrzynczak (Code Review) 04 Aug '20

04 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: PS3: > First we configure the PQR_ASSOC to pick mask2 . […] Ok, I see. Maybe I'm missing something, but does setting IA32_PQR_ASSOC when NEM mode is not enabled yet (for first setting it to 0x2) really do anything? My understanding was that the ways can't actually be protected until NEM mode is actually enabled, meaning that only the setting of 0x1 would "take effect". Could you help me understand this? -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… PS3, Line 2895: ADP > Add that name to the commit message too? IMHO, it's not a big deal. Plus, name clashes do exist: See `TGP` above, but `Tiger Point` is the codename of the NM10 chipset (usually paired with Pineview and Cedarview CPUs, more than a decade old): https://ark.intel.com/content/www/us/en/ark/products/codename/37533/tiger-p… -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:40:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Aamir Bohra (Code Review) 04 Aug '20

04 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: PS3: > Why bother to set the other masks (MASK_0 & MASK_1) if they're unused (PQR_ASSOC set to pick mask #2 […] First we configure the PQR_ASSOC to pick mask2 . fill the cache lines with access to data stack region and then switch to mask1 to protect the RW mapped ways from eviction. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:39:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Paul Menzel (Code Review) 04 Aug '20

04 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… PS3, Line 2895: ADP > Yes Angel Add that name to the commit message too? -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 17:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Pull up GPP_D16 instead of driving it
by Tim Wawrzynczak (Code Review) 04 Aug '20

04 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44116 ) Change subject: mb/google/volteer: Pull up GPP_D16 instead of driving it ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Gerrit-Change-Number: 44116 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 16:32:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: payload/seabios: Fix CBFS location on APL platform
by Felix Singer (Code Review) 04 Aug '20

04 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32327 Change subject: payload/seabios: Fix CBFS location on APL platform ...................................................................... payload/seabios: Fix CBFS location on APL platform Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M payloads/external/SeaBIOS/Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32327/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..594d37a 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -39,6 +39,9 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config -- To view, visit https://review.coreboot.org/c/coreboot/+/32327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Gerrit-Change-Number: 32327 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020