coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Shreesh Chhabbi (Code Review) 05 Aug '20

05 Aug '20

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: On TGL, QOS Mask 1 & 2 register offsets have got changed. Please help to incorporate the change into your patch. I had a WIP patch - https://review.coreboot.org/c/coreboot/+/43355. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Wed, 05 Aug 2020 05:26:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Refactor `get_pcie_bar`
by Patrick Rudolph (Code Review) 05 Aug '20

05 Aug '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44121 ) Change subject: nb/intel/sandybridge: Refactor `get_pcie_bar` ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Gerrit-Change-Number: 44121 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 05:20:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Subrata Banik (Code Review) 05 Aug '20

05 Aug '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/44108/3/src/include/device/pci_ids… PS3, Line 2895: ADP > IMHO, it's not a big deal. […] Thanks Angle for explaining this. @Paul, i hope you are good now as i have updated the commit msg too -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 03:44:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Subrata Banik (Code Review) 05 Aug '20

05 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Angel Pons, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44108 to look at the new patch set (#4). Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... soc/intel/common: Include Alder Lake device IDs Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 19 files changed, 447 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/44108/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver
by Sugnan Prabhu S (Code Review) 05 Aug '20

05 Aug '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver ...................................................................... Patch Set 26: (2 comments) https://review.coreboot.org/c/coreboot/+/41758/25//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41758/25//COMMIT_MSG@11 PS25, Line 11: > I believe this also adds support for CAM0, which was not the previous ASL. Done https://review.coreboot.org/c/coreboot/+/41758/11/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/11/src/mainboard/intel/jaspe… PS11, Line 398: device pci 05.0 on end # RP4 > This is incorrect, there is already a PCI device declared for 00:05.0 (see line 158). […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 26 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 05 Aug 2020 02:08:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver
by Sugnan Prabhu S (Code Review) 05 Aug '20

05 Aug '20

Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Wonkyu Kim, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41758 to look at the new patch set (#26). Change subject: mb/intel/jasperlake_rvp: Replace static camera ACPI by driver ...................................................................... mb/intel/jasperlake_rvp: Replace static camera ACPI by driver This change updates devicetree to enable SSDT generation for world facing and user facing cameras of jasperlake_rvp. Also removes DSDT changes related to the world facing camera. Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb D src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl 8 files changed, 111 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41758/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 26 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Nathaniel L Desimone (Code Review) 05 Aug '20

05 Aug '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… PS2, Line 116: mp_run_on_all_cpus > Current testing results: […] For #1) Your right that LT_LOCK_MEMORY is package scoped. For #2) PAVPC is locked in the middle of FSP-S (not @ end of PEI), and TSEGMB is locked in FSP-M. With SGX enabled, the flow needs to be this: 1. Pre-ucode SGX init 2. LT_LOCK_MEMORY 3. Reload ucode 4. Post-ucode SGX init I don't see any good way of doing SGX enabling with SkipMpInit == 1 since #1 and #4 are in the FSP. This is one of the reasons we added CpuMpPpi. With SGX disabled and SkipMpInit == 1, your change seems reasonable. I recommend you add an if statement here that only sets LT_LOCK_MEMORY iff FspmUpd->FspmConfig.SkipMpInit == 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 23:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x: Define and use `HOST_BRIDGE` macro
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44143 ) Change subject: nb/intel/x4x: Define and use `HOST_BRIDGE` macro ...................................................................... nb/intel/x4x: Define and use `HOST_BRIDGE` macro Other Intel northbridges do this. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 6 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/44143/1 diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 5db9382..328464a 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -13,5 +13,5 @@ reg32 = TPM32(0); reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); + pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 87c684c..d3c3308 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -15,32 +15,30 @@ void x4x_early_init(void) { - const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ - pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); /* Setup EPBAR. */ - pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(d0f0, D0F0_PAM(0), 0x30); - pci_write_config8(d0f0, D0F0_PAM(1), 0x33); - pci_write_config8(d0f0, D0F0_PAM(2), 0x33); - pci_write_config8(d0f0, D0F0_PAM(3), 0x33); - pci_write_config8(d0f0, D0F0_PAM(4), 0x33); - pci_write_config8(d0f0, D0F0_PAM(5), 0x33); - pci_write_config8(d0f0, D0F0_PAM(6), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(0), 0x30); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(1), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(2), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(3), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(4), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(5), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(6), 0x33); - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { + if (!(pci_read_config32(HOST_BRIDGE, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN); /* Set preallocated IGD size from CMOS */ u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ @@ -51,10 +49,10 @@ else if (gfxsize < 1) gfxsize = 1; /* Set GTT size to 2+2M */ - pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); + pci_write_config16(HOST_BRIDGE, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); } else { /* Does not feature internal graphics */ - pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); - pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); + pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(HOST_BRIDGE, D0F0_GGC, (1 << 1)); } } diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 8a69ba8..db0ab9c 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -72,7 +72,7 @@ {0, 0}, }; - const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO); + const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO); if (!(pciexbar_reg & 1)) { printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); @@ -95,13 +95,13 @@ static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC); return decode_tseg_size(esmramc); } static uintptr_t northbridge_get_tseg_base(void) { - return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); + return pci_read_config32(HOST_BRIDGE, D0F0_TSEG); } diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 174e8b5..9f361b6 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -122,11 +122,11 @@ const u32 eax = cpuid_ext(0x04, 0).eax; printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1); - u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), 0xe8); + u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8); if (!(capid & (1<<(79-64)))) printk(BIOS_WARNING, "iTPM enabled\n"); - capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + capid = pci_read_config32(HOST_BRIDGE, 0xe4); if (!(capid & (1<<(57-32)))) printk(BIOS_WARNING, "ME enabled\n"); @@ -246,7 +246,7 @@ u32 min_tCLK; u8 try_CAS; - u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f; + u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f; switch (s->max_fsb) { default: @@ -344,7 +344,7 @@ if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) return; /* IGD0EN gets disabled if not present before this code runs */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN); if (deven & IGD0EN) s->stacked_mode = 1; } @@ -593,9 +593,9 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); /* do magic 0xf0 thing. */ - pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2)); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2)); full_reset(); } @@ -616,7 +616,7 @@ timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); - pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); + pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); memset(&s, 0, sizeof(struct sysinfo)); @@ -671,7 +671,7 @@ checkreset_ddr2(s.boot_path); /* Detect dimms per channel */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9); + reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2); @@ -687,7 +687,7 @@ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1); + pci_or_config8(HOST_BRIDGE, 0xf4, 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 332af32..1aa7e39 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1270,14 +1270,14 @@ MCHBAR8(0x110) = (2 << 5) | (3 << 3); MCHBAR16(0x10e) = 0; MCHBAR32(0x108) = 0; - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000); + pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000); /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10); + pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10); /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000); + pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400); + pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000); + pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000); + pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000); } u32 test_address(int channel, int rank) @@ -1702,7 +1702,7 @@ 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; - ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); + ggc = pci_read_config16(HOST_BRIDGE, 0x52); gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, @@ -1733,20 +1733,20 @@ gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; - pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4); - pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6); + pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); + pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); if (reclaim) { - pci_write_config16(PCI_DEV(0, 0, 0), 0x98, + pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6)); - pci_write_config16(PCI_DEV(0, 0, 0), 0x9a, + pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6)); } - pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); + pci_write_config16(HOST_BRIDGE, 0xa2, touud); + pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); + pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20); /* Enable and set TSEG size to 2M */ - pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); - pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); + pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20); } static void set_enhanced_mode(struct sysinfo *s) @@ -1779,8 +1779,8 @@ MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; } - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1); + reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz ? 0x20000 : 0)); reg32 = 0x219100c2; @@ -1822,7 +1822,7 @@ if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) reg32 |= 0x20000; MCHBAR32(0x20) = reg32; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1); } static void power_settings(struct sysinfo *s) @@ -1943,7 +1943,7 @@ MCHBAR32(0x1110) = 0x10810350 & ~0x78; MCHBAR32(0x1114) = 0; x592 = 0xff; - if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3) + if (pci_read_config8(HOST_BRIDGE, 0x8) < 3) x592 = ~0x4; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { @@ -2056,7 +2056,7 @@ MCHBAR8_OR(0x5d8, 0x7); } if (CHANNEL_IS_POPULATED(s->dimms, 1)) { - if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) { + if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); MCHBAR8_OR(0x5d8, 1); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index bb51c60..45785a0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -9,6 +9,8 @@ /* * D0:F0 */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) + #include "hostbridge_regs.h" /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Gerrit-Change-Number: 44143 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "device/pci_device.c: Do not complain about disabled devices"
by Nico Huber (Code Review) 05 Aug '20

05 Aug '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44078 ) Change subject: Revert "device/pci_device.c: Do not complain about disabled devices" ...................................................................... Revert "device/pci_device.c: Do not complain about disabled devices" This reverts commit ad247ac5d8ef4a38bd1d61fbd28076f343a46c5c. It doesn't work like this. The `dev->enable` field has already been updated and is always `0` at this point. Change-Id: I5b3560dcea2f226c841f4823526db2fdab149d22 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/pci_device.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44078/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index f3cced9..3623c3b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1297,10 +1297,6 @@ /* Unlink it from list. */ *prev = dev->sibling; - /* If disabled in devicetree, do not print any messages. */ - if (!dev->enabled) - continue; - if (!once++) printk(BIOS_WARNING, "PCI: Leftover static devices:\n"); printk(BIOS_WARNING, "%s\n", dev_path(dev)); -- To view, visit https://review.coreboot.org/c/coreboot/+/44078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3560dcea2f226c841f4823526db2fdab149d22 Gerrit-Change-Number: 44078 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Add RMRRs after all DRHDs
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44112 ) Change subject: soc/intel/skylake: Add RMRRs after all DRHDs ...................................................................... soc/intel/skylake: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi.c 1 file changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44112/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 1beff3d..ae9d784 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -425,22 +425,19 @@ const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ - if (igfx_dev && igfx_dev->enabled && gfxvten && - gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfx_vtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4); + + /* First, add DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; @@ -461,6 +458,16 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Gerrit-Change-Number: 44112 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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