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Change in coreboot[master]: soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup
by Duan Huayang (Code Review) 06 Aug '20

06 Aug '20

Duan Huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41949 ) Change subject: soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup ...................................................................... soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup Current the DRAM control only support 4GB DDR, add more large size DDR support to meet the market requirement. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_configs.c M src/soc/mediatek/mt8183/dramc_param.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/emi.h 7 files changed, 175 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41949/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 73bd2f8..649ab10 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -30,3 +30,8 @@ return &params; } + +u32 get_rom_code(void) +{ + return ram_code(); +} diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c index 54d2209..546ad3a 100644 --- a/src/soc/mediatek/mt8183/dramc_param.c +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -31,12 +31,37 @@ return validate_dramc_param(blob) == DRAMC_SUCCESS; } +static void set_ddr_size_type(struct dramc_param *param) +{ + u32 ramcode = get_rom_code(); + u16 ddr_size_type = DDR_TYPE_2CH_2RK_4GB_2_2; + + switch (ramcode) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + ddr_size_type = DDR_TYPE_2CH_2RK_4GB_2_2; + break; + default: + break; + } + + param->header.ddr_size_type = ddr_size_type; +} + int initialize_dramc_param(void *blob, u16 config) { struct dramc_param *param = blob; struct dramc_param_header *hdr = &param->header; memset(blob, 0, sizeof(*param)); + + set_ddr_size_type(param); hdr->magic = DRAMC_PARAM_HEADER_MAGIC; hdr->size = sizeof(*param); hdr->version = DRAMC_PARAM_HEADER_VERSION; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b557550..6d5db3a 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -131,6 +131,19 @@ dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u16 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -2678,6 +2691,54 @@ } } +u8 get_dram_infor_after_cal(void) +{ + u8 vendor_id, density, max_density = 0; + u64 dram_size, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + dram_size = 0x20000000; + break; + case 0x1: + dram_size = 0x30000000; + break; + case 0x2: + dram_size = 0x40000000; + break; + case 0x3: + dram_size = 0x60000000; + break; + case 0x4: + dram_size = 0x80000000; + break; + case 0x5: + dram_size = 0xc0000000; + break; + case 0x6: + dram_size = 0x100000000L; + break; + default: + dram_size = 0; + } + if (dram_size > max_size) { + max_size = dram_size; + max_density = density; + } + dramc_show("RK%d size %dGb, density:%d\n", rk, (u32)(dram_size >> 27), max_density); + } + + return max_density; +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index c03f945..6a465e3 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -50,10 +50,10 @@ }; struct optimize_ac_time { - u8 rfc; - u8 rfc_05t; - u8 rfc_pb; - u8 rfrc_pb05t; + u8 trfc; + u8 trfrc_05t; + u8 trfc_pb; + u8 trfrc_pb_05t; u16 tx_ref_cnt; }; @@ -320,30 +320,79 @@ setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(u8 freq_group) +static void dramc_ac_timing_optimize(u8 freq_group, u8 density) { - struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, - .rfrc_pb05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, - .rfrc_pb05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, - .rfrc_pb05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, - .rfrc_pb05t = 1, .tx_ref_cnt = 138}, + u8 rfcab_grp = 0; + u8 trfc = 101, trfrc_05t = 0, trfc_pb = 44, trfrc_pb_05t = 0, tx_ref_cnt = 118; + enum tRFCAB{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM}; + + struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = { + /* LP4X_DDR1600 */ + {{.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0, .trfrc_pb_05t = 0, .tx_ref_cnt = 32}, + {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6, .trfrc_pb_05t = 0, .tx_ref_cnt = 42}, + {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16, .trfrc_pb_05t = 0, .tx_ref_cnt = 62}, + {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26, .trfrc_pb_05t = 0, .tx_ref_cnt = 82}}, + /* LP4X_DDR2400 */ + {{.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6, .trfrc_pb_05t = 0, .tx_ref_cnt = 46}, + {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15, .trfrc_pb_05t = 0, .tx_ref_cnt = 61}, + {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, .trfrc_pb_05t = 0, .tx_ref_cnt = 91}, + {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45, .trfrc_pb_05t = 0, .tx_ref_cnt = 121}}, + /* LP4X_DDR3200 */ + {{.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12, .trfrc_pb_05t = 0, .tx_ref_cnt = 59}, + {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24, .trfrc_pb_05t = 0, .tx_ref_cnt = 79}, + {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44, .trfrc_pb_05t = 0, .tx_ref_cnt = 119}, + {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64, .trfrc_pb_05t = 0, .tx_ref_cnt = 159}}, + /* LP4X_DDR3600 */ + {{.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16, .trfrc_pb_05t = 0, .tx_ref_cnt = 68}, + {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, .trfrc_pb_05t = 0, .tx_ref_cnt = 92}, + {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53, .trfrc_pb_05t = 1, .tx_ref_cnt = 138}, + {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76, .trfrc_pb_05t = 1, .tx_ref_cnt = 185}}, }; + switch (density) { + /* 4Gb per die (2Gb per channel) */ + case 0x0: + rfcab_grp = tRFCAB_130; + break; + /* 6Gb per die (3Gb per channel) or 8Gb per die (4Gb per channel) */ + case 0x1: + case 0x2: + rfcab_grp = tRFCAB_180; + break; + /* 12Gb per die (6Gb per channel) or 16Gb per die (8Gb per channel) */ + case 0x3: + case 0x4: + rfcab_grp = tRFCAB_280; + break; + /* 24Gb per die (12Gb per channel) or 32Gb per die (16Gb per channel) */ + case 0x5: + case 0x6: + rfcab_grp = tRFCAB_380; + break; + default: + dramc_dbg("density err!\n"); + break; + } + + trfc = rf_cab_opt[freq_group][rfcab_grp].trfc; + trfrc_05t = rf_cab_opt[freq_group][rfcab_grp].trfrc_05t; + trfc_pb = rf_cab_opt[freq_group][rfcab_grp].trfc_pb; + trfrc_pb_05t = rf_cab_opt[freq_group][rfcab_grp].trfrc_pb_05t; + tx_ref_cnt = rf_cab_opt[freq_group][rfcab_grp].tx_ref_cnt; + dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb_05t %d\n", + density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb_05t); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + 0xff << 16, trfc << 16); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + 0x1 << 2, trfrc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + 0x3ff << 0, tx_ref_cnt << 0); clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + 0xff << 0, trfc_pb << 0); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); + 0x1 << 1, trfrc_pb_05t << 1); } } @@ -495,6 +544,7 @@ struct dram_shared_data *shared, const int shuffle, bool *first_run) { + u8 density = 0; const u8 *freq_tbl; if (CONFIG(MT8183_DRAM_EMCP)) @@ -519,7 +569,9 @@ dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; - dramc_ac_timing_optimize(freq_group); + + density = get_dram_infor_after_cal(); + dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index 7b3ba7e..8cadb28 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -11,7 +11,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 2, + DRAMC_PARAM_HEADER_VERSION = 3, }; enum DRAMC_PARAM_STATUS_CODES { @@ -38,11 +38,18 @@ DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, }; +enum DRAMC_PARAM_DDR_SIZE_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + struct dramc_param_header { u32 status; /* DRAMC_PARAM_STATUS_CODES */ u32 magic; - u32 version; - u32 size; /* size of whole dramc_param */ + u32 version; /* DRAMC_PARAM_HEADER_VERSION */ + u32 size; /* size of whole dramc_param */ + u16 ddr_size_type; /* DRAMC_PARAM_DDR_SIZE_TYPE */ u16 config; /* DRAMC_PARAM_CONFIG */ u16 flags; /* DRAMC_PARAM_FLAGS */ u32 checksum; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 0de86f6..6aa8f0b 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -107,5 +107,6 @@ u32 get_shu_freq(u8 shu); void dramc_hw_dqsosc(u8 chn); void dramc_dqs_precalculation_preset(void); +u8 get_dram_infor_after_cal(void); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 3862d54..46921fe 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -86,6 +86,7 @@ extern const u8 phy_mapping[CHANNEL_MAX][16]; +u32 get_rom_code(void); int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/41949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Gerrit-Change-Number: 41949 Gerrit-PatchSet: 1 Gerrit-Owner: Duan Huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42194 ) Change subject: soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value ...................................................................... soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value Different density should correspond to different tRFCab and tRFCpb timing. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 157 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42194/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0f91d18..531be8b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -131,6 +131,19 @@ dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -2695,6 +2708,55 @@ } } +void get_dram_info_after_cal(u8 *density_result) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5); + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8); + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + *density_result = max_density; +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index c03f945..54891b5 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -50,10 +50,10 @@ }; struct optimize_ac_time { - u8 rfc; - u8 rfc_05t; - u8 rfc_pb; - u8 rfrc_pb05t; + u8 trfc; + u8 trfrc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; u16 tx_ref_cnt; }; @@ -320,30 +320,102 @@ setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(u8 freq_group) +static void dramc_ac_timing_optimize(u8 freq_group, u8 density) { - struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, - .rfrc_pb05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, - .rfrc_pb05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, - .rfrc_pb05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, - .rfrc_pb05t = 1, .tx_ref_cnt = 138}, + u8 rfcab_grp = 0; + u8 trfc, trfrc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + enum tRFCAB { + tRFCAB_130 = 0, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM }; + const struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = { + [LP4X_DDR1600] = { + [tRFCAB_130] = {.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 32}, + [tRFCAB_180] = {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 42}, + [tRFCAB_280] = {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 62}, + [tRFCAB_380] = {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 82} + }, + [LP4X_DDR2400] = { + [tRFCAB_130] = {.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 46}, + [tRFCAB_180] = {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15, + .trfrc_pb05t = 0, .tx_ref_cnt = 61}, + [tRFCAB_280] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 91}, + [tRFCAB_380] = {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45, + .trfrc_pb05t = 0, .tx_ref_cnt = 121} + }, + [LP4X_DDR3200] = { + [tRFCAB_130] = {.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12, + .trfrc_pb05t = 0, .tx_ref_cnt = 59}, + [tRFCAB_180] = {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24, + .trfrc_pb05t = 0, .tx_ref_cnt = 79}, + [tRFCAB_280] = {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44, + .trfrc_pb05t = 0, .tx_ref_cnt = 119}, + [tRFCAB_380] = {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64, + .trfrc_pb05t = 0, .tx_ref_cnt = 159} + }, + [LP4X_DDR3600] = { + [tRFCAB_130] = {.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + [tRFCAB_180] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 92}, + [tRFCAB_280] = {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53, + .trfrc_pb05t = 1, .tx_ref_cnt = 138}, + [tRFCAB_380] = {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76, + .trfrc_pb05t = 1, .tx_ref_cnt = 185} + }, + }; + + switch (density) { + case 0x0: + rfcab_grp = tRFCAB_130; + break; + case 0x1: + case 0x2: + rfcab_grp = tRFCAB_180; + break; + case 0x3: + case 0x4: + rfcab_grp = tRFCAB_280; + break; + case 0x5: + case 0x6: + rfcab_grp = tRFCAB_380; + break; + default: + dramc_err("density err!\n"); + break; + } + + const struct optimize_ac_time *ac_tim = &rf_cab_opt[freq_group][rfcab_grp]; + trfc = ac_tim->trfc; + trfrc_05t = ac_tim->trfrc_05t; + trfc_pb = ac_tim->trfc_pb; + trfrc_pb05t = ac_tim->trfrc_pb05t; + tx_ref_cnt = ac_tim->tx_ref_cnt; + dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb05t %d\n", + density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + 0xff << 16, trfc << 16); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + 0x1 << 2, trfrc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + 0x3ff << 0, tx_ref_cnt << 0); clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + 0xff << 0, trfc_pb << 0); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); + 0x1 << 1, trfrc_pb05t << 1); } } @@ -495,6 +567,7 @@ struct dram_shared_data *shared, const int shuffle, bool *first_run) { + u8 density; const u8 *freq_tbl; if (CONFIG(MT8183_DRAM_EMCP)) @@ -519,7 +592,8 @@ dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; - dramc_ac_timing_optimize(freq_group); + get_dram_info_after_cal(&density); + dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 0de86f6..daaa14f 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -107,5 +107,6 @@ u32 get_shu_freq(u8 shu); void dramc_hw_dqsosc(u8 chn); void dramc_dqs_precalculation_preset(void); +void get_dram_info_after_cal(u8 *density); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545 Gerrit-Change-Number: 42194 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42193 ) Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ...................................................................... soc/mediatek/mt8183: Fix some programming errors of DRAMC setting Fix some programming errors. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 56 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index cb64e50..082f6bb 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -57,9 +57,9 @@ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle); - setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } @@ -890,12 +890,11 @@ clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -949,11 +948,11 @@ clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { @@ -1057,7 +1056,7 @@ clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); - clrbits32(&ch[0].phy.pll3, 0x1 < 0); + clrbits32(&ch[0].phy.pll3, 0x1 << 0); setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3); @@ -1088,7 +1087,11 @@ for (size_t b = 0; b < 2; b++) setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 5bffc42..580d435 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -48,10 +48,12 @@ broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + } impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -92,7 +94,7 @@ if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4 ); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -151,9 +153,6 @@ sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -203,7 +202,10 @@ SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); } static void transfer_pll_to_spm_control(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b557550..0f91d18 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -366,12 +366,30 @@ clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); } -static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) { + u8 dvs_delay; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0]; - clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + switch (freq_group) { + case LP4X_DDR1600: + dvs_delay = 5; + break; + case LP4X_DDR2400: + dvs_delay = 4; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + dvs_delay = 3; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20); clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } @@ -409,7 +427,13 @@ dramc_hw_gating_onoff(chn, false); clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30); + } + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits32(&ch[chn].ao.mrs, 0x3 << 24); setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -417,21 +441,14 @@ clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); - dramc_rx_input_delay_tracking_init_by_freq(chn); + dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group); setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); else - setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - } - - for (size_t r = 0; r < 2; r++) { - for (size_t b = 0; b < 2; b++) - clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], - (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Gerrit-Change-Number: 42193 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Nathaniel L Desimone (Code Review) 06 Aug '20

06 Aug '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 00:42:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/44244/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44244/2//COMMIT_MSG@24 PS2, Line 24: Note: if someone has a better idea, comment please ;) > Yes, fix the native init code. […] the native init code itself isn't the problem, but FSP is ;) see Nate's answer https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: /amd/fsp/picasso Fix type 17 smbios misalignment
by Jason Glenesk (Code Review) 05 Aug '20

05 Aug '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44086 to review the following change. Change subject: /amd/fsp/picasso Fix type 17 smbios misalignment ...................................................................... /amd/fsp/picasso Fix type 17 smbios misalignment Add __packed to TYPE17_DMI_INFO structure to remove padding. Remove reserved fields that are no longer required. Corresponding change will also be made within fsp to pack the structure. BUG=b:154046847 TEST=Boot a trembyle with and without the reserved fields and confirm type 17 table is unchanged. Change-Id: I9ba7e2a4fb82c7b0b77ee7c6c075e6211d4f6adf Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/vendorcode/amd/fsp/picasso/dmi_info.h 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44086/1 diff --git a/src/vendorcode/amd/fsp/picasso/dmi_info.h b/src/vendorcode/amd/fsp/picasso/dmi_info.h index adab2f9..36ca719 100644 --- a/src/vendorcode/amd/fsp/picasso/dmi_info.h +++ b/src/vendorcode/amd/fsp/picasso/dmi_info.h @@ -178,7 +178,6 @@ OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT32 _Reserved1_; OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT CHAR8 SerialNumber[9]; ///< Serial Number. OUT CHAR8 PartNumber[21]; ///< Part Number. @@ -188,8 +187,7 @@ OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts - OUT UINT32 _Reserved2_; -} TYPE17_DMI_INFO; +}__packed TYPE17_DMI_INFO; /// Collection of pointers to the DMI records typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/44086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba7e2a4fb82c7b0b77ee7c6c075e6211d4f6adf Gerrit-Change-Number: 44086 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/44244/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44244/2//COMMIT_MSG@24 PS2, Line 24: Note: if someone has a better idea, comment please ;) Yes, fix the native init code. 😜 -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:05:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: set LT_LOCK_MEMORY only when using native MP init
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44243 ) Change subject: soc/intel/skylake: set LT_LOCK_MEMORY only when using native MP init ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78 Gerrit-Change-Number: 44243 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:04:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common,skl: lock LT_LOCK_MEMORY once, not per-thread
by Angel Pons (Code Review) 05 Aug '20

05 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44242 ) Change subject: soc/intel/common,skl: lock LT_LOCK_MEMORY once, not per-thread ...................................................................... Patch Set 2: Code-Review+1 Waiting for Jenkins to underp -- To view, visit https://review.coreboot.org/c/coreboot/+/44242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Gerrit-Change-Number: 44242 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:03:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 05 Aug '20

05 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 19:57:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020