coreboot-gerrit August 2020

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Change in coreboot[master]: nb/intel/sandybridge: Deduplicate PCIEXBAR decoding
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/44122 ) Change subject: nb/intel/sandybridge: Deduplicate PCIEXBAR decoding ...................................................................... Removed Verified+1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/44122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Gerrit-Change-Number: 44122 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: nb/intel/sandybridge: Refactor `get_pcie_bar`
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44121 ) Change subject: nb/intel/sandybridge: Refactor `get_pcie_bar` ...................................................................... nb/intel/sandybridge: Refactor `get_pcie_bar` Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 17 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 1d20a4b..8f1db97 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <acpi/acpi.h> +#include <commonlib/helpers.h> #include <device/pci_ops.h> #include <stdint.h> #include <delay.h> @@ -39,18 +40,16 @@ static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base) +static int decode_pcie_bar(u32 *const base, u32 *const len) { - struct device *dev; - u32 pciexbar_reg; - *base = 0; + *len = 0; - dev = pcidev_on_root(0, 0); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) @@ -58,14 +57,17 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - *base = pciexbar_reg & (0xffffffffULL << 28); - return 256; + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; case 1: /* 128M */ - *base = pciexbar_reg & (0xffffffffULL << 27); - return 128; + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; case 2: /* 64M */ - *base = pciexbar_reg & (0xffffffffULL << 26); - return 64; + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } return 0; @@ -129,8 +131,7 @@ static void mc_read_resources(struct device *dev) { - u32 pcie_config_base; - int buses; + u32 pcie_config_base, pcie_config_len; uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; uint16_t ggc; @@ -139,8 +140,8 @@ pci_dev_read_resources(dev); - buses = get_pcie_bar(&pcie_config_base); - if (buses) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { + const int buses = pcie_config_len / MiB; struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Gerrit-Change-Number: 44121 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge: Refactor `get_pcie_bar`
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44121 ) Change subject: nb/intel/sandybridge: Refactor `get_pcie_bar` ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/44121/4/src/northbridge/intel/sand… File src/northbridge/intel/sandybridge/northbridge.c: https://review.coreboot.org/c/coreboot/+/44121/4/src/northbridge/intel/sand… PS4, Line 50: return 0; > The other instances of `decode_pcie_bar` return 0 on failure. […] Marking comment as resolved given the non-response https://review.coreboot.org/c/coreboot/+/44121/4/src/northbridge/intel/sand… PS4, Line 143: decode_pcie_bar > I agree. It shouldn't error out because we're programming MMCONF in the bootblock. […] Marking comment as resolved given the non-response -- To view, visit https://review.coreboot.org/c/coreboot/+/44121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Gerrit-Change-Number: 44121 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 07:24:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock
by Subrata Banik (Code Review) 06 Aug '20

06 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44163 ) Change subject: soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock ...................................................................... soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include all ADL-S and P related DID, BDF Change-Id: I42a7f8914f4fc23f97182f212a7662d3ab971561 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/alderlake/bootblock/bootblock.c A src/soc/intel/alderlake/bootblock/cpu.c A src/soc/intel/alderlake/bootblock/pch.c A src/soc/intel/alderlake/bootblock/report_platform.c A src/soc/intel/alderlake/include/soc/bootblock.h A src/soc/intel/alderlake/include/soc/espi.h A src/soc/intel/alderlake/include/soc/iomap.h A src/soc/intel/alderlake/include/soc/p2sb.h A src/soc/intel/alderlake/include/soc/pch.h A src/soc/intel/alderlake/include/soc/pci_devs.h A src/soc/intel/alderlake/include/soc/pcr_ids.h A src/soc/intel/alderlake/include/soc/pm.h A src/soc/intel/alderlake/include/soc/smbus.h 13 files changed, 1,159 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/44163/1 diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c new file mode 100644 index 0000000..e7d97c5 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <intelblocks/systemagent.h> +#include <intelblocks/tco.h> +#include <intelblocks/uart.h> +#include <soc/bootblock.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/alderlake/bootblock/cpu.c b/src/soc/intel/alderlake/bootblock/cpu.c new file mode 100644 index 0000000..9e52b7d --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/cpu.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 7 + */ + +#include <intelblocks/fast_spi.h> +#include <soc/bootblock.h> + +void bootblock_cpu_init(void) +{ + /* + * Alderlake platform doesn't support booting from any other media + * (like eMMC on APL/GLK platform) than only booting from SPI device + * and on IA platform SPI is memory mapped hence enabling temporarily + * cacheing on memory-mapped spi boot media. + * + * This assumption will not hold good for APL/GLK platform where boot + * from eMMC is also possible options. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c new file mode 100644 index 0000000..99b40b9 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2, 3, 4, 27, 28 + */ + +#include <console/console.h> +#include <console/post_codes.h> +#include <device/mmio.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <soc/bootblock.h> +#include <soc/espi.h> +#include <soc/iomap.h> +#include <soc/p2sb.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void soc_config_pwrmbase(void) +{ + uint32_t reg32; + uint16_t reg16; + + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Enable PWRM in PMC */ + reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); + write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c new file mode 100644 index 0000000..7840db3 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Platform Stepping and IDs + * Document number: 619362, 619501 + * Chapter number: 2, 14 + */ + +#include <arch/cpu.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/mp_init.h> +#include <soc/bootblock.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <string.h> + +#define BIOS_SIGN_ID 0x8B + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_ALDERLAKE_S_A0, "Alderlake-S A0" }, + { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_2, "Alderlake-S (8+6+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_4, "Alderlake-S (8+2+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_5, "Alderlake-S (8+0+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_6, "Alderlake-S (6+8+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_7, "Alderlake-S (6+6+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_8, "Alderlake-S (6+4+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_9, "Alderlake-S (6+2+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_10, "Alderlake-S (6+0+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_11, "Alderlake-S (4+0+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_13, "Alderlake-S (8+6+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_14, "Alderlake-S (8+6+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_S_ID_15, "Alderlake-S (8+8+1)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P (2+8+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_2, "Alderlake-P (2+4+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P (6+8+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P (6+4+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P (4+8+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P (2+4+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P (2+8+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P (2+0+2)" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P (2+0+2)" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P-Super SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P Premium SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P Mainstream SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P Super SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P Premium SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, "Alderlake-S-Super SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, "Alderlake-S Premium SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, "Alderlake-S Mainstream SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, "Alderlake-S Super SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, "Alderlake-S Premium SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, "Alderlake-S-Base SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, "Alderlake-S-Base SKU" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_S_GT1, "Alderlake S GT1" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index, cpu_id, cpu_feature_flag; + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + u32 p[13]; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax >= 0x80000004) { + int j = 0; + + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + p[j++] = cpuidr.eax; + p[j++] = cpuidr.ebx; + p[j++] = cpuidr.ecx; + p[j++] = cpuidr.edx; + } + p[12] = 0; + cpu_name = (char *)p; + + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) + cpu_name++; + } + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, microcode_ver.hi); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; + txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; + vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h new file mode 100644 index 0000000..9816b31 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_ +#define _SOC_ALDERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/alderlake/include/soc/espi.h b/src/soc/intel/alderlake/include/soc/espi.h new file mode 100644 index 0000000..d754f1d --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/espi.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2 + */ + +#ifndef _SOC_ALDERLAKE_ESPI_H_ +#define _SOC_ALDERLAKE_ESPI_H_ + +#include <stdint.h> + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h new file mode 100644 index 0000000..927506c --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Firmware Architecture Specification + * Document number: 626540 + * Chapter number: 4 + */ + +#ifndef _SOC_ALDERLAKE_IOMAP_H_ +#define _SOC_ALDERLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define UART_BASE_SIZE 0x1000 + +#define UART_BASE_0_ADDRESS 0xfe03e000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define REG_BASE_ADDRESS 0xfb000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xfed90000 +#define VTD_BASE_SIZE 0x00004000 + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/p2sb.h b/src/soc/intel/alderlake/include/soc/p2sb.h new file mode 100644 index 0000000..b25b001 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/p2sb.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 3 + */ + +#ifndef _SOC_ALDERLAKE_P2SB_H_ +#define _SOC_ALDERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pch.h b/src/soc/intel/alderlake/include/soc/pch.h new file mode 100644 index 0000000..e5ec3f7 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pch.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_PCH_H_ +#define _SOC_ALDERLAKE_PCH_H_ + + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h new file mode 100644 index 0000000..ab39895 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_PCI_DEVS_H_ +#define _SOC_ALDERLAKE_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_CPU_PCIE 0x06 +#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) +#define NUM_TBT_FUNCTIONS 4 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) + +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) + +#define SA_DEV_SLOT_VMD 0x0e +#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) +#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_SIO0 0x10 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO0, 1) +#define PCH_DEVFN_IEH _PCH_DEVFN(SIO0, 5) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_I2C6 _PCH_DEV(SIO0, 0) +#define PCH_DEV_I2C7 _PCH_DEV(SIO0, 1) +#define PCH_DEV_IEH _PCH_DEV(SIO0, 5) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#else +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 0) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 1) +#endif + +#define PCH_DEV_SLOT_SIO1 0x11 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_UART4 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_UART5 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_UART6 _PCH_DEVFN(SIO1, 3) +#define PCH_DEVFN_GSPI5 _PCH_DEVFN(SIO1, 4) +#define PCH_DEVFN_GSPI6 _PCH_DEVFN(SIO1, 5) +#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) +#define PCH_DEV_UART4 _PCH_DEV(SIO1, 1) +#define PCH_DEV_UART5 _PCH_DEV(SIO1, 2) +#define PCH_DEV_UART6 _PCH_DEV(SIO1, 3) +#define PCH_DEV_GSPI5 _PCH_DEV(SIO1, 4) +#define PCH_DEV_GSPI6 _PCH_DEV(SIO1, 5) +#endif + +#define PCH_DEV_SLOT_ISH 0x12 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_GSPI4 _PCH_DEVFN(SIO2, 1) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_GSPI4 _PCH_DEV(SIO2, 1) +#endif + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) +#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) +#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) +#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) + +#define PCH_DEV_SLOT_PCIE_2 0x1b +#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) +#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) +#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) +#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) +#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) +#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) +#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) +#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) +#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) +#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) +#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) +#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) +#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) +#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) +#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) +#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) + +#define PCH_DEV_SLOT_PCIE_3 0x1a +#define PCH_DEVFN_PCIE25 _PCH_DEVFN(PCIE_3, 0) +#define PCH_DEVFN_PCIE26 _PCH_DEVFN(PCIE_3, 1) +#define PCH_DEVFN_PCIE27 _PCH_DEVFN(PCIE_3, 2) +#define PCH_DEVFN_PCIE28 _PCH_DEVFN(PCIE_3, 3) +#define PCH_DEV_PCIE25 _PCH_DEV(PCIE_3, 0) +#define PCH_DEV_PCIE26 _PCH_DEV(PCIE_3, 1) +#define PCH_DEV_PCIE27 _PCH_DEV(PCIE_3, 2) +#define PCH_DEV_PCIE28 _PCH_DEV(PCIE_3, 3) +#endif + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h new file mode 100644 index 0000000..02f8b87 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 31-35 + */ + +#ifndef SOC_ALDERLAKE_PCR_H +#define SOC_ALDERLAKE_PCR_H +/* + * Port ids + */ + +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM3 0x6b +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_ESPI 0x72 +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h new file mode 100644 index 0000000..b65b24d --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4 + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/alderlake/include/soc/smbus.h b/src/soc/intel/alderlake/include/soc/smbus.h new file mode 100644 index 0000000..ab4994a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/smbus.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 6 + */ + +#ifndef _SOC_ALDERLAKE_SMBUS_H_ +#define _SOC_ALDERLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a7f8914f4fc23f97182f212a7662d3ab971561 Gerrit-Change-Number: 44163 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_I...
by Subrata Banik (Code Review) 06 Aug '20

06 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44077 ) Change subject: drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable ...................................................................... drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable This patch ensures to take control of APs back by doing the full AP re-initialization after FSP-S is done and control has been transferred back to coreboot. TEST=Able to see all cores available after booting to OS using below command when coreboot is built with CONFIG_USE_INTEL_FSP_MP_INIT enable. > cat /proc/cpuinfo Without this CL : shows only 1 core (only BSP) With this CL : shows all possible cores available (BSP + APs) Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44077/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 663b1d7..7b77590 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/mp_init.h> #include <program_loading.h> #include <soc/intel/common/vbt.h> #include <stage_cache.h> @@ -127,6 +128,14 @@ fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); + /* + * As per FSP integration guide: + * If bootloader needs to take control of APs back the full AP re-initialization + * required after FSP-S completed and control has been transferred back to bootloader + */ + if (CONFIG(USE_INTEL_FSP_MP_INIT)) + init_cpus(); + if (!CONFIG(PLATFORM_USES_FSP2_2)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/44077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666 Gerrit-Change-Number: 44077 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: soc/intel/common/block/cpu: Refactor init_cpus function
by Subrata Banik (Code Review) 06 Aug '20

06 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44076 ) Change subject: soc/intel/common/block/cpu: Refactor init_cpus function ...................................................................... soc/intel/common/block/cpu: Refactor init_cpus function This patch makes init_cpus function external so that it can be used in below scenarios: 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude this call if user has selected CONFIG_USE_INTEL_FSP_MP_INIT) 2. coreboot would like to take APs control back after FSP-S has done with MP initialization based on user select CONFIG_USE_INTEL_FSP_MP_INIT Also make sure post_cpus_init function is getting executed unconditionally to update MTTR snapshot on all cores. Change-Id: Idc03090360f34df074b33ba0fced2d192edf068a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 2 files changed, 29 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/44076/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 90bae16..4f27e52 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -125,14 +125,19 @@ *parallel = 1; } -static void init_cpus(void *unused) +/* + * Perform BSP and AP initialization + * This function can be called in below cases + * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude + * this call if user has selected CONFIG_USE_INTEL_FSP_MP_INIT) + * 2. coreboot would like to take APs control back after FSP-S has done with MP + * initialization based on user select CONFIG_USE_INTEL_FSP_MP_INIT + */ +void init_cpus(void) { struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); - if (CONFIG(USE_INTEL_FSP_MP_INIT)) - return; - microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); @@ -140,6 +145,15 @@ soc_init_cpus(dev->link_list); } +static void coreboot_init_cpus(void *unused) +{ + if (CONFIG(USE_INTEL_FSP_MP_INIT)) + return; + + init_cpus(); +} + + static void wrapper_x86_setup_mtrrs(void *unused) { x86_setup_mtrrs_with_detect(); @@ -148,9 +162,6 @@ /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { - if (CONFIG(USE_INTEL_FSP_MP_INIT)) - return; - if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); @@ -158,6 +169,6 @@ } /* Do CPU MP Init before FSP Silicon Init */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_cpus, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL); BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e03d8bd..615449f 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -69,6 +69,16 @@ void get_microcode_info(const void **microcode, int *parallel); /* + * Perform BSP and AP initialization + * This function can be called in below cases + * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude + * this call if user has selected CONFIG_USE_INTEL_FSP_MP_INIT) + * 2. coreboot would like to take APs control back after FSP-S has done with MP + * initialization based on user select CONFIG_USE_INTEL_FSP_MP_INIT + */ +void init_cpus(void); + +/* * SoC Overrides * * All new SoC must implement below functionality for ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/44076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc03090360f34df074b33ba0fced2d192edf068a Gerrit-Change-Number: 44076 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: device/pci_rom: Fix rom_header structure
by Benjamin Doron (Code Review) 06 Aug '20

06 Aug '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43071 to look at the new patch set (#4). Change subject: device/pci_rom: Fix rom_header structure ...................................................................... device/pci_rom: Fix rom_header structure According to the specification[1] (page 33), these are the correct sizes for the "init" and "reserved" elements. 1. https://www.scs.stanford.edu/nyu/04fa/lab/specsbbs101.pdf Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/include/device/pci_rom.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/43071/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/43071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584 Gerrit-Change-Number: 43071 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer/variant/lindar: Update gpio settings and overridetr...
by Julia Tsai (Code Review) 06 Aug '20

06 Aug '20

Julia Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44080 ) Change subject: mb/google/volteer/variant/lindar: Update gpio settings and overridetree.cb ...................................................................... mb/google/volteer/variant/lindar: Update gpio settings and overridetree.cb Based on schematic and gpio table of lindar, generate gpio settings and overridetree.cb for lindar. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Julia Tsai <julia.tsai(a)lcfc.corp-partner.google.com> Change-Id: Id08ea6270b53806214b0e49af826453b37c02a42 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/lindar/overridetree.cb 2 files changed, 117 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/44080/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 05ad93f..baa71cb 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -107,7 +107,7 @@ default "delbin" if BOARD_GOOGLE_DELBIN default "eldrid" if BOARD_GOOGLE_ELDRID default "halvor" if BOARD_GOOGLE_HALVOR - default "lindar" if BOARD_GOOGLE_LINDAR + default "lindar" if BOARD_GOOGLE_LINDAR default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR default "todor" if BOARD_GOOGLE_TODOR diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 32204c5..c84ed83 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -1,6 +1,120 @@ chip soc/intel/tigerlake - device domain 0 on - end + # USB Port Config + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + + register "SaGv" = "SaGv_Disabled" + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + device domain 0 on + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end # I2C1 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HD audio + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id08ea6270b53806214b0e49af826453b37c02a42 Gerrit-Change-Number: 44080 Gerrit-PatchSet: 1 Gerrit-Owner: Julia Tsai <julia.tsai(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43795 ) Change subject: soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init ...................................................................... soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I072745933fe141cac26afd044836a564e345d036 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/common/mmu_operations.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43795/1 diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 9550ba8..960d742 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -12,11 +12,11 @@ mmu_init(); /* - * Set 0x0 to 4GB address as device memory. We want to config IO_PHYS + * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS * address to DEV_MEM, and map a proper range of dram for the memory * test during calibration. */ - mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/43795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I072745933fe141cac26afd044836a564e345d036 Gerrit-Change-Number: 43795 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42035 ) Change subject: google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup ...................................................................... google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup Current the DRAM control only support 4GB DDR, add more large size DDR support to meet the market requirement. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c 8 files changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42035/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index 6b53bcc..c339d54 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 74b642d..e8dcb82 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 5617ff9..65a54da 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index fc31a18f..0f5003a 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index df37f1a..b44bba3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index a5764d2..06ec402 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 97a8e2d..3c16325 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 2de4be0..606d7c8 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } -- To view, visit https://review.coreboot.org/c/coreboot/+/42035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Gerrit-Change-Number: 42035 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020