coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/zork: Add kconfigs to check schematic version 3.6
by Josie Nordrum (Code Review) 06 Aug '20

06 Aug '20

Josie Nordrum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44156 ) Change subject: mb/google/zork: Add kconfigs to check schematic version 3.6 ...................................................................... mb/google/zork: Add kconfigs to check schematic version 3.6 Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. BUG=b:161938476 BRANCH=None TEST=None Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Signed-off-by: Josie Nordrum <josienordrum(a)google.com> --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 3 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/44156/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 6160021..c854e54 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -169,6 +169,32 @@ longer has to support pre-v3 schematics, `default y` entry for it can be dropped. +config VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + bool + default y if BOARD_GOOGLE_TREMBYLE + default y if BOARD_GOOGLE_EZKINIL + default y if BOARD_GOOGLE_MORPHIUS + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_DALBOZ + default y if BOARD_GOOGLE_WOOMAX + default y if BOARD_GOOGLE_VILBOZ + default n + +config VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS + int + depends on VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + default 4 if BOARD_GOOGLE_TREMBYLE + default 3 if BOARD_GOOGLE_EZKINIL + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 3 if BOARD_GOOGLE_DALBOZ + default 2 if BOARD_GOOGLE_WOOMAX + default 2 if BOARD_GOOGLE_VILBOZ + default 256 + help + Minimum board versions which switched to using non-CODEC_GPI pin for + HP_INT_ODL. + config VARIANT_MIN_BOARD_ID_V3_SCHEMATICS int depends on VARIANT_SUPPORTS_PRE_V3_SCHEMATICS diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 0a1cf5c..ec393d3 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -130,6 +130,29 @@ return true; } +bool variant_uses_v3_6_schematics(void) +{ + uint32_t board_version; + + if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS)) + return true; + + if (google_chromeec_cbi_get_board_version(&board_version)) + return false; + + if ((int)board_version < VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS) + return false; + + return true; +} + +/* pre-v3.6, CODEC_GPI was used as headphone jack interrupt. + Starting v3.6 this was changed to a separate GPIO.*/ +bool variant_uses_codec_gpi(void) +{ + return !variant_uses_v3_6_schematics(); +} + bool variant_has_active_low_wifi_power(void) { uint32_t board_version; diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 6b9bbfd..5ea6b87 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -66,6 +66,10 @@ /* Return true if variant uses v3 version of reference schematics. */ bool variant_uses_v3_schematics(void); +/* Return true if variant uses v3.6 version of reference schematics. */ +bool variant_uses_v3_6_schematics(void); +/* Return true if variant does NOT use v3.6 version of reference schematics. */ +bool variant_uses_codec_gpi(void); /* Return true if variant has active low power enable fow WiFi. */ bool variant_has_active_low_wifi_power(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Gerrit-Change-Number: 44156 Gerrit-PatchSet: 1 Gerrit-Owner: Josie Nordrum <josienordrum(a)google.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
by Aamir Bohra (Code Review) 06 Aug '20

06 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > does this mean that the enhanced mode never worked correctly in the first place? IOW, we were writin […] I am checking on this, on the SKL, CNL, ICL it still maps to LSB. In my CML testing I am seeing a hang with this implementation. Need to confirm on the offset mapping. https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: PS3: > Ok, I see. […] yes, we configure the mask2 with the RW data mapped ways configured for eviction and start filling in the cache lines i.e access one DWORD from each cache line of the dataStack region to map all dataStack into the cache. and then toggle the mask to protect the data from eviction so that the RW data does not get evicted out. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Thu, 06 Aug 2020 18:02:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork: Add Bluetooth reset gpios to devicetree
by Rob Barnes (Code Review) 06 Aug '20

06 Aug '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42832 ) Change subject: mb/google/zork: Add Bluetooth reset gpios to devicetree ...................................................................... mb/google/zork: Add Bluetooth reset gpios to devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Add bluetooth reset gpio 143 to dalboz baseboard devicetree BUG=b:157580724 TEST=Boot Ezkinil, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42832/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index d541529..d20115f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -161,6 +161,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" device usb 2.5 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 47ff8ba..c1d8288 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -189,6 +189,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.5 on end end end @@ -208,6 +209,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/42832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Gerrit-Change-Number: 42832 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

6 27

Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Aaron Durbin (Code Review) 06 Aug '20

06 Aug '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 17:46:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: add support for ddr4 memory
by Nick Vaccaro (Code Review) 06 Aug '20

06 Aug '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44250 ) Change subject: mb/google/volteer: add support for ddr4 memory ...................................................................... mb/google/volteer: add support for ddr4 memory Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x memory types. Change existing variant code to use the new meminit_ddr() call instead of calling meminit_lpddr4x() directly. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation as I do not have a DDR4 board to test this on. Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c 8 files changed, 45 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44250/1 diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 10c424e..8893785 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -15,7 +15,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct ddr_memory_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, @@ -27,7 +27,7 @@ if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) mem_cfg->PchHdaEnable = 0; - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); + meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } bool mainboard_get_dram_part_num(const char **part_num, size_t *len) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 2f90a42..8408198 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct ddr_memory_cfg *variant_memory_params(void); int variant_memory_sku(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index 2da395a..dafeb3b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <gpio.h> -static const struct lpddr4x_cfg baseboard_memcfg = { +static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { /* DQ CPU<>DRAM map */ .dq_map = { [0] = { @@ -56,7 +56,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &baseboard_lpddr4x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 788ba51..e7429ca 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -54,7 +54,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &delbin_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { - return &delbin_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 5444c6f..2e730a4 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -54,7 +54,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &malefor_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { - return &malefor_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 773e885..c61287d 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -54,7 +54,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &terrador_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { - return &terrador_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index 5adf80c..129cd10 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -54,7 +54,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &todor_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { - return &todor_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 455b180..0c7310e 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -54,7 +54,12 @@ .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &voxel_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { - return &voxel_memcfg; + return &board_memcfg; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6 Gerrit-Change-Number: 44250 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: add common routine for DDR init
by Nick Vaccaro (Code Review) 06 Aug '20

06 Aug '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44249 ) Change subject: soc/intel/tigerlake: add common routine for DDR init ...................................................................... soc/intel/tigerlake: add common routine for DDR init Add a common routine meminit_ddr() that calls the appropriate meminit routine based on whether the memory type requested is LPDDR4x or DDR4. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation. I do not have a DDR4 board to test this on. Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 2 files changed, 40 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44249/1 diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 2cef561..4a52298 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -21,8 +21,13 @@ MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ }; +enum ddr_memtype { + MEMTYPE_DDR4, /* Uses DDR4 memory */ + MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +}; + enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ + /* Read SPD from pointer provided to memory location. */ SPD_MEMPTR, /* Read SPD using index into spd.bin in CBFS. */ SPD_CBFS, @@ -127,9 +132,24 @@ uint8_t ect; }; +/* DDR Memory Information - Supports DDR4 and LPDDR4x */ +struct ddr_memory_cfg { + enum ddr_memtype mem_type; + union { + const struct mb_ddr4_cfg *ddr4_cfg; + const struct lpddr4x_cfg *lpddr4_cfg; + }; +}; + +/* Initialize LPDDR4x memory configurations */ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); + const struct spd_info *spd, bool half_populated); + /* Initialize DDR4 memory configurations */ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); + const struct spd_info *spd, const bool half_populated); + +/* Determine which DDR memory is used and call appropriate init routine */ +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 790e2e0..0c6f0b0 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -435,3 +435,20 @@ } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Gerrit-Change-Number: 44249 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Raul Rangel (Code Review) 06 Aug '20

06 Aug '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... Patch Set 1: Code-Review+2 Thanks for testing. I'm wondering if we should hold off on merging this one until S3 has stabilized. This will turn off the serial console while suspending, I guess we can update the care and feeding guide to add the no_console_suspend command line. -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Aug 2020 14:49:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 06 Aug '20

06 Aug '20

Hello Varshit B Pandya, build bot (Jenkins), Pratik Prajapati, Nico Huber, Patrick Georgi, Subrata Banik, Varun Joshi, Arthur Heymans, Patrick Rudolph, Nathaniel L Desimone, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36356 to look at the new patch set (#5). Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST FSP does not set LT_LOCK_MEMORY when SkipMpInit=1. Therefore, set LT_LOCK_MEMORY at end of POST, when native MP init is used, to protect SMM in accordance to Intel BWG. Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/finalize.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/36356/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/google/puff: Remove second temp sensor
by Andrew McRae (Code Review) 06 Aug '20

06 Aug '20

Hello Andrew McRae, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44206 to review the following change. Change subject: mainboard/google/puff: Remove second temp sensor ...................................................................... mainboard/google/puff: Remove second temp sensor Newer boards have removed the second temperature sensor and relocated the remaining sensor. Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43 Signed-off-by: Andrew McRae <amcrae(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl 2 files changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44206/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl index 86bd8fc..e0df9ba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl @@ -19,16 +19,6 @@ #define DPTF_TSR0_ACTIVE_AC3 42 #define DPTF_TSR0_ACTIVE_AC4 39 -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 - #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -74,10 +64,6 @@ Package () { \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 } }) @@ -87,9 +73,6 @@ /* CPU Throttle Effect on Ambient (TSR0) */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl index 2a94f94..40bc664 100644 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl @@ -8,11 +8,6 @@ #define DPTF_TSR0_PASSIVE 60 #define DPTF_TSR0_CRITICAL 85 -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 85 - #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -58,10 +53,6 @@ Package () { \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 } }) @@ -71,9 +62,6 @@ /* CPU Throttle Effect on Ambient (TSR0) */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () -- To view, visit https://review.coreboot.org/c/coreboot/+/44206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43 Gerrit-Change-Number: 44206 Gerrit-PatchSet: 1 Gerrit-Owner: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Avoid shifting by a negative value
by John Zhao (Code Review) 06 Aug '20

06 Aug '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44186 ) Change subject: security/intel/txt: Avoid shifting by a negative value ...................................................................... security/intel/txt: Avoid shifting by a negative value Coverity detects an integer handling issue with BAD_SHIFT. The inline function log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } could return -1, which causes shifting by a negative amount value and has undefined behavior. Add sanity check for the acm_header->size to avoid shifting negative value. Found-by: Coverity CID 1431124 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ic687349b14917e39d2a8186968037ca2521c7cdc --- M src/security/intel/txt/common.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44186/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index d3e18376..d641585 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -138,6 +138,7 @@ { const struct acm_header_v0 *acm_header = (struct acm_header_v0 *)ptr; uint32_t max_size_acm_area = 0; + const size_t acm_len = 0; if (acm_header->module_type != CHIPSET_ACM) return ACM_E_TYPE_NOT_MATCH; @@ -163,7 +164,8 @@ * SAFER MODE EXTENSIONS REFERENCE. * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D */ - const size_t acm_len = 1UL << log2_ceil((acm_header->size & 0xffffff) << 2); + if (acm_header->size != 0) + acm_len = 1UL << log2_ceil((acm_header->size & 0xffffff) << 2); if (max_size_acm_area < acm_len) { printk(BIOS_ERR, "TEE-TXT: BIOS ACM doesn't fit into AC execution region\n"); return ACM_E_NOT_FIT_INTO_CPU_ACM_MEM; -- To view, visit https://review.coreboot.org/c/coreboot/+/44186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic687349b14917e39d2a8186968037ca2521c7cdc Gerrit-Change-Number: 44186 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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