coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/skylake: Enable SDXC depending on devicetree configuration
by Felix Singer (Code Review) 08 Aug '20

08 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44028 ) Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration ...................................................................... soc/intel/skylake: Enable SDXC depending on devicetree configuration Currently SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SDXC controller. I checked all corresponding mainboards if the devicetree configuration matches the ScsSdCardEnabled setting. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6423cf4..cb0d2fc 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -257,7 +257,9 @@ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); params->ScsEmmcEnabled = dev ? dev->enabled : 0; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + params->ScsSdCardEnabled = dev && dev->enabled; if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { params->PchScsEmmcHs400DllDataValid = diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e332a6b..404a9f4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -306,7 +306,6 @@ /* eMMC and SD */ u8 ScsEmmcHs400Enabled; - u8 ScsSdCardEnabled; u8 EmmcHs400DllNeed; u8 ScsEmmcHs400RxStrobeDll1; u8 ScsEmmcHs400TxDataDll; -- To view, visit https://review.coreboot.org/c/coreboot/+/44028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Gerrit-Change-Number: 44028 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: Revert "soc/intel/skylake: Enable thermal subsystem depending on devi...
by Angel Pons (Code Review) 08 Aug '20

08 Aug '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Michał Żygowski, Frans Hendriks, Paul Menzel, Michael Niewöhner, Patrick Rudolph, Wim Vervoorn, Piotr Król, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43079 to review the following change. Change subject: Revert "soc/intel/skylake: Enable thermal subsystem depending on devicetree" ...................................................................... Revert "soc/intel/skylake: Enable thermal subsystem depending on devicetree" This reverts commit 9c1c00968c943659bab2a817892e5a9be9dfb7c0. Reason for revert: Breaks building master. Change-Id: I957b91de55fc82fd9a8f7574ac6622e9131088f9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 23 files changed, 25 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/43079/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index d6ad862..d4ab530 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -54,6 +54,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -122,7 +123,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index f6c42f1..8621663 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -38,6 +38,7 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "SaImguEnable" = "0" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8a459f7..5e927b4 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -47,6 +47,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -246,7 +247,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 651f174..ac3ee8b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -78,6 +78,7 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -321,7 +322,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index f2d7c64..1e1b8e8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,6 +49,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -101,7 +102,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index eae9835..432ef99 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -54,6 +54,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -247,7 +248,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ea6267f..2dc0703 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -44,6 +44,7 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -267,7 +268,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 98568f8..bf3b7bd 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -43,6 +43,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -282,7 +283,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 43d6509..d64bd8a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -44,6 +44,7 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -288,7 +289,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2bd82a9..26207f5 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -49,6 +49,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -267,7 +268,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem + device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ef5cd1b..54faf47 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -54,6 +54,7 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -246,7 +247,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index e5307c2..777c521 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -44,6 +44,7 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -268,7 +269,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 318986e..231fbad 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -28,6 +28,7 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PchHdaVcType" = "Vc1" @@ -120,7 +121,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index ae372ec..ad9dd36 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,6 +4,7 @@ register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" + register "Device4Enable" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -116,7 +117,6 @@ }" device domain 0 on - device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA device pci 19.1 on end # I2C #5 device pci 1e.1 on end # UART #1 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ae637ca..aebda85 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -29,6 +29,7 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" @@ -174,7 +175,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 87d3fc0..2a0558e 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -23,6 +23,7 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" @@ -210,7 +211,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index a355ee4..a58e169 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -54,6 +54,7 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -173,7 +174,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 1640011..9071a7b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -43,6 +43,7 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" @@ -218,7 +219,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA thermal subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 18e02e7..5aa51d3 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -60,6 +60,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -170,7 +171,6 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 4306da6..01aec8b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -40,6 +40,7 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -188,7 +189,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # Thermal Subsystem + device pci 04.0 off end # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 435015b..51c3cec 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -10,6 +10,7 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" # SATA configuration diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6423cf4..562d791 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -278,9 +278,7 @@ params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; - - dev = pcidev_path_on_root(SA_DEVFN_TS); - params->Device4Enable = dev && dev->enabled; + params->Device4Enable = config->Device4Enable; params->EnableTcoTimer = !config->PmTimerDisabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e332a6b..fc86cfd 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -336,6 +336,7 @@ u32 LogoPtr; u32 LogoSize; u32 GraphicsConfigPtr; + u8 Device4Enable; u8 RtcLock; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; -- To view, visit https://review.coreboot.org/c/coreboot/+/43079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957b91de55fc82fd9a8f7574ac6622e9131088f9 Gerrit-Change-Number: 43079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: nb/intel/pineview/raminit.c: Fix dead assignments
by HAOUAS Elyes (Code Review) 08 Aug '20

08 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44289 ) Change subject: nb/intel/pineview/raminit.c: Fix dead assignments ...................................................................... nb/intel/pineview/raminit.c: Fix dead assignments Change-Id: Idf864299fbf120cb56030a9c166476d03e72ff32 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44289/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be..7906d7b 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2497,18 +2497,11 @@ dqdqs_out = 4382; dqdqs_outdelay = 5083; dqdqs_delay = 4692; - coretomcp = 0; - txdelay = 0; - halfclk = 0; - tmaxunmask = 0; - tmaxpi = 0; repeat = 2; feature = 0; cwb = 0; pimdclk = 0; - reg32 = 0; push = 0; - reg8 = 0; mdclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500; refclk = 3000 - mdclk; -- To view, visit https://review.coreboot.org/c/coreboot/+/44289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf864299fbf120cb56030a9c166476d03e72ff32 Gerrit-Change-Number: 44289 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/mediatek/mt8192: Initial commit
by CK HU (Code Review) 08 Aug '20

08 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43957 ) Change subject: soc/mediatek/mt8192: Initial commit ...................................................................... soc/mediatek/mt8192: Initial commit Add MT8192 address map, memlayout and first Kconfig. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d --- A src/soc/mediatek/mt8192/Kconfig A src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/memlayout.ld 3 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43957/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig new file mode 100644 index 0000000..2412204 --- /dev/null +++ b/src/soc/mediatek/mt8192/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8192 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8192 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h new file mode 100755 index 0000000..c4b3047 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, + UART0_BASE = IO_PHYS + 0x01002000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, + SFLASH_REG_BASE = IO_PHYS + 0x01234000, + IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + IOCFG_BM_BASE = IO_PHYS + 0x01D10000, + IOCFG_BL_BASE = IO_PHYS + 0x01D30000, + IOCFG_BR_BASE = IO_PHYS + 0x01D40000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + IOCFG_LB_BASE = IO_PHYS + 0x01E70000, + IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, + IOCFG_LT_BASE = IO_PHYS + 0x01F20000, + IOCFG_TL_BASE = IO_PHYS + 0x01F30000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + MSDC0_BASE = IO_PHYS + 0x01F60000, +}; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld new file mode 100644 index 0000000..df9d376 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) + SRAM_END(0x00120000) + + SRAM_L2C_START(0x00200000) + BOOTBLOCK(0x00201000, 64K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40000000, 2M) + RAMSTAGE(0x40200000, 256K) + + BL31(0x54600000, 0x60000) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d Gerrit-Change-Number: 43957 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: mb/asrock/h110m: Fix devicetree and unwanted rebase
by Felix Singer (Code Review) 08 Aug '20

08 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44297 ) Change subject: mb/asrock/h110m: Fix devicetree and unwanted rebase ...................................................................... mb/asrock/h110m: Fix devicetree and unwanted rebase Unfortunately it came to an unwanted rebase while changing the commit message with gerrit at CB:44026, which breaks building the Asrock H110M on master. Therefore remove Device4Enable from devicetree, since it doesn't exist anymore. It looks like with changing the commit message at CB:44026, gerrit rebased all previous commits on master. In this case, this is CB:44027. The rebase is not mentioned in the log, but the diff between patchset 1 and patchset 2 (which is new and not made by me) shows that the parent changed. CB:43919 relocated several devicetree options, including the option Device4Enable, and to me it looks like with the rebase this line just disappeared for gerrit and thus it just removed it from CB:44026. Change-Id: I848b6442a16f392b71b80bf82c8337bf46d7d771 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44297/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 68ef2a4..6de2a63 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -152,9 +152,7 @@ device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end - device pci 04.0 on # Thermal Subsystem - register "Device4Enable" = "1" - end + device pci 04.0 on end # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 -- To view, visit https://review.coreboot.org/c/coreboot/+/44297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I848b6442a16f392b71b80bf82c8337bf46d7d771 Gerrit-Change-Number: 44297 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 08 Aug '20

08 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > > Patch Set 2: > > > > > > > > > Patch Set 2: > > > > > > > > > > > Patch Set 2: > > > > > > > > > > > > > Patch Set 2: > > > > > > > > > > > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > > > > > > > > > > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > > > > > > > > > > > > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > > > > > > > > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > > > > > > > > > > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. > > > > > > > > > > "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. > > > > > > > > > > @Nate: is this* valid for SKL/KBL as well? > > > > > > > > > > Yes, this is valid and exactly the point, why native SGX init can't be used. LT_MEMORY_LOCK must be set, *before* native SGX init (well, more specifically before microcode reload). That conflicts with the requirement of FSP-S to be able to write registers. > > > > > > > At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected > > > > > > Yes, SGX works. No, not in a secure way with native SGX init without LT_MEMORY_LOCK. > > > > in my original code i.e. native sgx init, i was doing exactly that. > > lock LT mem, reload ucode and so on. (my original code below - commit 418535e222ccd9f688facbb7d9663ca4cacc2739) which was working. No, it was not working, because FSP-S can't lock TSEGMB and PAVPC. See the relation chain of this CB, please. > > > > void sgx_configure(void) > > { > > const void *microcode_patch = intel_mp_current_microcode(); > > > > if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { > > printk(BIOS_ERR, "SGX: pre-conditions not met\n"); > > return; > > } > > > > /* Enable the SGX feature */ > > enable_sgx(); > > > > /* Update the owner epoch value */ > > if (owner_epoch_update() < 0) > > return; > > > > /* Ensure to lock memory before reload microcode patch */ > > cpu_lock_sgx_memory(); > > > > /* Reload the microcode patch */ > > intel_microcode_load_unlocked(microcode_patch); > > > > /* Lock the SGX feature */ > > lock_sgx(); > > > > /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */ > > if (is_prmrr_approved()) > > activate_sgx(); > > } > > I'll let Nate comment on "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* That was already discussed and ack'ed by him. -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 23:44:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Enable HDA depending on devicetree configuration
by Felix Singer (Code Review) 08 Aug '20

08 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44026 ) Change subject: soc/intel/skylake: Enable HDA depending on devicetree configuration ...................................................................... soc/intel/skylake: Enable HDA depending on devicetree configuration Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SA thermal subsystem controller. I checked all corresponding mainboards if the devicetree configuration matches the Device4Enable setting. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 22 files changed, 19 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44026/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index d4ab530..d6ad862 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -54,7 +54,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -123,6 +122,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index fae925f..35e85f5 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -33,7 +33,6 @@ register "HeciEnabled" = "0" register "SkipExtGfxScan" = "0" register "PrimaryDisplay" = "Display_PEG" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 8621663..f6c42f1 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -38,7 +38,6 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "SaImguEnable" = "0" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 5e927b4..8a459f7 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -47,7 +47,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -247,6 +246,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ac3ee8b..651f174 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -78,7 +78,6 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -322,6 +321,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1e1b8e8..f2d7c64 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,7 +49,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -102,6 +101,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 432ef99..eae9835 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -54,7 +54,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -248,6 +247,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 2dc0703..ea6267f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -44,7 +44,6 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -268,6 +267,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 8e1f954..b8c503f 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -43,7 +43,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -283,6 +282,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 0a67d4d..1be6337 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -44,7 +44,6 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -289,6 +288,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 8959a29..a297544 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -49,7 +49,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -268,7 +267,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 54faf47..ef5cd1b 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -54,7 +54,6 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -247,6 +246,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 777c521..e5307c2 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -44,7 +44,6 @@ register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -269,6 +268,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 0b1ba1d..327b1dd 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -26,7 +26,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PchHdaVcType" = "Vc1" @@ -119,6 +118,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index cfb50e3..318f067 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -5,7 +5,6 @@ register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "Device4Enable" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -118,6 +117,7 @@ }" device domain 0 on + device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA device pci 19.1 on end # I2C #5 device pci 1e.1 on end # UART #1 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index aebda85..ae637ca 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -29,7 +29,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" @@ -175,6 +174,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2a0558e..87d3fc0 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -23,7 +23,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" @@ -211,6 +210,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index a58e169..a355ee4 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -54,7 +54,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -174,6 +173,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9071a7b..1640011 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -43,7 +43,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" @@ -219,6 +218,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5aa51d3..18e02e7 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -60,7 +60,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -171,6 +170,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 01aec8b..4306da6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -40,7 +40,6 @@ register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -189,7 +188,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # Thermal Subsystem + device pci 04.0 on end # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 51c3cec..435015b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -10,7 +10,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" # SATA configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/44026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Gerrit-Change-Number: 44026 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Pratikkumar V Prajapati (Code Review) 08 Aug '20

08 Aug '20

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > > Patch Set 2: > > > > > > > > > Patch Set 2: > > > > > > > > > > > Patch Set 2: > > > > > > > > > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > > > > > > > > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > > > > > > > > > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > > > > > > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > > > > > > > > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. > > > > > > > > "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. > > > > > > > > @Nate: is this* valid for SKL/KBL as well? > > > > > > > Yes, this is valid and exactly the point, why native SGX init can't be used. LT_MEMORY_LOCK must be set, *before* native SGX init (well, more specifically before microcode reload). That conflicts with the requirement of FSP-S to be able to write registers. > > > > > At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected > > > > Yes, SGX works. No, not in a secure way with native SGX init without LT_MEMORY_LOCK. > > in my original code i.e. native sgx init, i was doing exactly that. > lock LT mem, reload ucode and so on. (my original code below - commit 418535e222ccd9f688facbb7d9663ca4cacc2739) which was working. > > void sgx_configure(void) > { > const void *microcode_patch = intel_mp_current_microcode(); > > if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { > printk(BIOS_ERR, "SGX: pre-conditions not met\n"); > return; > } > > /* Enable the SGX feature */ > enable_sgx(); > > /* Update the owner epoch value */ > if (owner_epoch_update() < 0) > return; > > /* Ensure to lock memory before reload microcode patch */ > cpu_lock_sgx_memory(); > > /* Reload the microcode patch */ > intel_microcode_load_unlocked(microcode_patch); > > /* Lock the SGX feature */ > lock_sgx(); > > /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */ > if (is_prmrr_approved()) > activate_sgx(); > } I'll let Nate comment on "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 22:56:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Pratikkumar V Prajapati (Code Review) 08 Aug '20

08 Aug '20

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44244 ) Change subject: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > > Patch Set 2: > > > > > > > > > Patch Set 2: > > > > > > > > > > if i remember correctly, this programming sequence requirement was from cannon-lake onwards. skylake/kabylake can still use native (coreboot) sgx init flow. > > > > > > > > On SKL LT_MEMORY_LOCK has to be set, too, and FSP does this with SkipMpInit=0. AFAICT native SGX init can't be used on SKL for the same reasons we can't use it on CNL. > > > > > > > > > > > > > > From cannon-lake onwards, sgx init needs fsp for the reasons mentioned in https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f…. i guess mp-ppi may also be used for cannon-lake onwards. Please follow Nate's recommendation for that. > > > > > > > > > > PS: I see my gmail was added earlier and that notification was in spam. Thanks for adding my @intel email. I am off next week, I’ll respond the following week if there are follow-up questions. > > > > > > > > See CB:36356. Native SGX init is not used in CNL, so there is nothing more to do. > > > > > > "FSP-S must be able to write and lock some registers that would be immutable after setting LT_LOCK_MEMORY."* I dont think i got into this issue when i wrote native sgx init flow. At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected. > > > > > > @Nate: is this* valid for SKL/KBL as well? > > > > Yes, this is valid and exactly the point, why native SGX init can't be used. LT_MEMORY_LOCK must be set, *before* native SGX init (well, more specifically before microcode reload). That conflicts with the requirement of FSP-S to be able to write registers. > > > At that time i was able to activate the SGX and lock it correctly by using native code only. i created enclaves also from the application and checked it was encrypted and working as expected > > Yes, SGX works. No, not in a secure way with native SGX init without LT_MEMORY_LOCK. in my original code i.e. native sgx init, i was doing exactly that. lock LT mem, reload ucode and so on. (my original code below - commit 418535e222ccd9f688facbb7d9663ca4cacc2739) which was working. void sgx_configure(void) { const void *microcode_patch = intel_mp_current_microcode(); if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; } /* Enable the SGX feature */ enable_sgx(); /* Update the owner epoch value */ if (owner_epoch_update() < 0) return; /* Ensure to lock memory before reload microcode patch */ cpu_lock_sgx_memory(); /* Reload the microcode patch */ intel_microcode_load_unlocked(microcode_patch); /* Lock the SGX feature */ lock_sgx(); /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */ if (is_prmrr_approved()) activate_sgx(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4251c6f1155ae7d1f0cd9064af55cd346ec88845 Gerrit-Change-Number: 44244 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratik Prajapati <pratik.prajapati(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Aug 2020 22:54:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC|WIP] soc/intel/skylake: replace native SGX initialization by FSP
by Michael Niewöhner (Code Review) 08 Aug '20

08 Aug '20

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