August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Arthur Heymans (Code Review) Aug. 8, 2020

Aug. 8, 2020

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44137 ) Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Gerrit-Change-Number: 44137 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Aug 2020 23:03:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Michael Niewöhner (Code Review) Aug. 8, 2020

Aug. 8, 2020

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44137 to look at the new patch set (#5). Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST ...................................................................... soc/intel/skylake: acpi: drop HWP's dependency on EIST Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift Technology (ISST) - also know as HWP - are two independent mechanisms for controlling voltage and frequency based on performance hints. When HWP is enabled, it overrides the software-based EIST. It does not depend on EIST, though, but can be enabled on its own. Break up that currently existing dependency in ACPI generation code. It was tested that HWP can be enabled and gets used by the Linux pstate cpufreq driver. With HWP disabled, the frequency does not decrease, even not in powersave mode. After enabling HWP the frequency changed in relation to the current workload. (Test device: Acer ES1-572) Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44137/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/44137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Gerrit-Change-Number: 44137 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: 3rdparty/intel-microcode: Update submodule to 20200616 release
by Angel Pons (Code Review) Aug. 8, 2020

Aug. 8, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43758 ) Change subject: 3rdparty/intel-microcode: Update submodule to 20200616 release ...................................................................... 3rdparty/intel-microcode: Update submodule to 20200616 release Change-Id: Ia250765e2cb81d6a39ad00ebbab20e7b87fa42d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/43758/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 33b7b2f..0e4288f 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 33b7b2f3817e362111cd91910026ab8907f21710 +Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 -- To view, visit https://review.coreboot.org/c/coreboot/+/43758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia250765e2cb81d6a39ad00ebbab20e7b87fa42d1 Gerrit-Change-Number: 43758 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc
by Jonathan Zhang (Code Review) Aug. 8, 2020

Aug. 8, 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44257 ) Change subject: soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc ...................................................................... soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc CPX-SP ww32 has a number of new features and bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the PCIe NIC device not working. ww32 release added two UDP parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to vt-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable vt-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. A separate PR will be submitted to enable it in coreboot. There is a change in IIO UDS Hob. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44257/1 diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 7093ec9..96949fd 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -57,5 +57,9 @@ /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ m_cfg->PchAdrEn = 0x02; + /* Make all IIO PCIe ports and port menus visible */ + m_cfg->PEXPHIDE = 0x0; + m_cfg->HidePEXPMenu = 0x0; + mainboard_memory_init_params(mupd); } diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 144db07..3517522 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -326,43 +326,45 @@ **/ UINT8 TorThresLoctoremEmpty; -/** Offset 0x008D - TSC Sync in Sockets +/** Offset 0x008D - MBA BW Calibration + MBA BW Calibration setting + 0:Linear, 1:Biased, 2:Legacy, 3:Auto +**/ + UINT8 MbeBwCal; + +/** Offset 0x008E - TSC Sync in Sockets Enable or Disable TSC Sync in Sockets **/ UINT8 TscSyncEn; -/** Offset 0x008E - HA A to S directory optimization +/** Offset 0x008F - HA A to S directory optimization Enable or Disable HA A to S directory optimization **/ UINT8 StaleAtoSOptEn; -/** Offset 0x008F - LLC Deadline Allocation +/** Offset 0x0090 - LLC Deadline Allocation Enable or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; -/** Offset 0x0090 - Split Lock +/** Offset 0x0091 - Split Lock Enable or Disable Split Lock **/ UINT8 SplitLock; -/** Offset 0x0091 - MMCFG Base Address +/** Offset 0x0092 - MMCFG Base Address Setup MMCFG Base Address 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto **/ UINT8 mmCfgBase; -/** Offset 0x0092 - MMCFG Size +/** Offset 0x0093 - MMCFG Size Select MMCFG Size 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto **/ UINT8 mmCfgSize; -/** Offset 0x0093 -**/ - UINT8 UnusedUpdSpace0; - /** Offset 0x0094 - MMIO High Base Address MMIO High Base Address, a hex number for Bit[51:32] **/ @@ -376,7 +378,7 @@ /** Offset 0x0099 **/ - UINT8 UnusedUpdSpace1; + UINT8 UnusedUpdSpace0; /** Offset 0x009A - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space @@ -398,7 +400,7 @@ /** Offset 0x009E **/ - UINT8 UnusedUpdSpace2[2]; + UINT8 UnusedUpdSpace1[2]; /** Offset 0x00A0 - } TYPE:{Combo Enable or Disable @@ -466,39 +468,44 @@ **/ UINT8 VmxEnable; -/** Offset 0x00BD - IIO ConfigIOU0 +/** Offset 0x00BD - Usage type for Processor X2apic Function + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 X2apic; + +/** Offset 0x00BE - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8]; -/** Offset 0x00C5 - IIO ConfigIOU1 +/** Offset 0x00C6 - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8]; -/** Offset 0x00CD - IIO ConfigIOU2 +/** Offset 0x00CE - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8]; -/** Offset 0x00D5 - IIO ConfigIOU3 +/** Offset 0x00D6 - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8]; -/** Offset 0x00DD - IIO ConfigIOU4 +/** Offset 0x00DE - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00E5 +/** Offset 0x00E6 **/ - UINT8 UnusedUpdSpace3[3]; + UINT8 UnusedUpdSpace2[2]; /** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr @@ -616,58 +623,77 @@ **/ UINT8 VtdSupport; -/** Offset 0x0105 - PchSirqMode +/** Offset 0x0105 - Usage type for IIO Pcie Port Hide + Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible +**/ + UINT8 PEXPHIDE; + +/** Offset 0x0106 - Usage type for IIO Pcie Port Menu Hide + Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +**/ + UINT8 HidePEXPMenu; + +/** Offset 0x0107 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; -/** Offset 0x0106 - PchAdrEn +/** Offset 0x0108 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x0107 - } TYPE:{Combo +/** Offset 0x0109 - ThermalDeviceEnable + Enable or Disable ThermalDeviceEnable with PCI or ACPI mode +**/ + UINT8 ThermalDeviceEnable; + +/** Offset 0x010A - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x0108 - PCH PCIE PLL Ssc +/** Offset 0x010B - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0109 - Usage type for PCH PCIE Root Port Index +/** Offset 0x010C - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x011D - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0120 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0131 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x0134 - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0145 - SerialIoUartDebugEnable +/** Offset 0x0148 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x0146 - ISA Serial Base selection +/** Offset 0x0149 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x014A - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0148 +/** Offset 0x014C **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -688,9 +714,9 @@ **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0158 +/** Offset 0x015C **/ - UINT8 UnusedUpdSpace4[6]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x015E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 8dcac42..a9465e1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -155,7 +155,6 @@ uint8_t PcieSegment; UINT64_STRUCT SegMmcfgBase; uint16_t stackPresentBitmap; - uint16_t CxlPresentBitmap; uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha; -- To view, visit https://review.coreboot.org/c/coreboot/+/44257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Gerrit-Change-Number: 44257 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/google/zork/trembyle: comment why USB OC pin mapping is different
by Felix Held (Code Review) Aug. 8, 2020

Aug. 8, 2020

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44291 ) Change subject: mb/google/zork/trembyle: comment why USB OC pin mapping is different ...................................................................... mb/google/zork/trembyle: comment why USB OC pin mapping is different Change-Id: I68b7529733e604ac45919a54e094be7eeb044458 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/variants/trembyle/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44291/1 diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 26d9a3e..4ceaeb3 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -22,7 +22,7 @@ # End : OPN Performance Configuration - # USB OC pin mapping + # USB OC pin mapping: existing trembyle boards are based on old schematics version register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0 register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b7529733e604ac45919a54e094be7eeb044458 Gerrit-Change-Number: 44291 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/asrock/h110m: remove unused Device4Enable from devtree
by Maxim Polyakov (Code Review) Aug. 8, 2020

Aug. 8, 2020

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44300 ) Change subject: mb/asrock/h110m: remove unused Device4Enable from devtree ...................................................................... mb/asrock/h110m: remove unused Device4Enable from devtree This option has been removed from the parameters structure for intel skylake CPU. Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44300/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 68ef2a4..f75fdc8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -152,9 +152,7 @@ device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end - device pci 04.0 on # Thermal Subsystem - register "Device4Enable" = "1" - end + device pci 04.0 on and # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 -- To view, visit https://review.coreboot.org/c/coreboot/+/44300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf Gerrit-Change-Number: 44300 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/intel/xeon_sp/cpx: add GUID and name for more HOBs
by Jonathan Zhang (Code Review) Aug. 8, 2020

Aug. 8, 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43337 ) Change subject: soc/intel/xeon_sp/cpx: add GUID and name for more HOBs ...................................................................... soc/intel/xeon_sp/cpx: add GUID and name for more HOBs Change-Id: I46637839452d6f7fba7453c19f18efef338f2ad6 --- M src/soc/intel/xeon_sp/cpx/hob_display.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/43337/1 diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index 3d61a82..2865fa2 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -8,8 +8,14 @@ #include <lib.h> #include <soc/soc_util.h> +#define FSP_PREV_BOOT_ERR_HOB_GUID { \ + 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, \ + 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ +} + static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; +static const uint8_t fsp_prev_boot_err_hob_guid[16] = FSP_PREV_BOOT_ERR_HOB_GUID; struct guid_name_map { const void *guid; @@ -19,6 +25,7 @@ static const struct guid_name_map guid_names[] = { { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, + { fsp_prev_boot_err_hob_guid, "FSP_PREV_BOOT_ERR_HOB_GUID" }, }; const char *soc_get_guid_name(const uint8_t *guid) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 51aa051..cbb81a6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -96,7 +96,7 @@ UINT32 memSize; // Total physical memory size UINT16 memFreq; // Mem Frequency - UINT8 reserved2[61]; + UINT8 reserved2[62]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements -- To view, visit https://review.coreboot.org/c/coreboot/+/43337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46637839452d6f7fba7453c19f18efef338f2ad6 Gerrit-Change-Number: 43337 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS"
by Jonathan Zhang (Code Review) Aug. 8, 2020

Aug. 8, 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43325 ) Change subject: temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS" ...................................................................... temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS" This reverts commit 7454005a4fd611cc2ad4b490442834e50272fd1b. CPX-SP FSP ww28 release has a regression that boot hangs at FSP-M execution when boot mode is BOOT_ASSUMING_NO_CONFIGURATION_CHANGES. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I495b4242a0c6a8796fab21a8057053744739df04 --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43325/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 9c6450e..59ccc6f 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -66,6 +66,4 @@ config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y -select CACHE_MRC_SETTINGS - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I495b4242a0c6a8796fab21a8057053744739df04 Gerrit-Change-Number: 43325 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[4.11_branch]: mainboard/ocp/monolake: If memory is locked down, clear TPM and reset
by Jonathan Zhang (Code Review) Aug. 8, 2020

Aug. 8, 2020

Hello Andrey Petrov, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42711 to review the following change. Change subject: mainboard/ocp/monolake: If memory is locked down, clear TPM and reset ...................................................................... mainboard/ocp/monolake: If memory is locked down, clear TPM and reset Under certain conditions TXT can force system to come out of reset with "locked" memory configuration. This manifests itself in IMC's SMBus controller not being able to read and SPD. FSP does not seem to detect this condition and simply fails with "no memory found" error. It turned out IBB measurements are stored in PCR-0 on TPM and that is what TXT fw seems to be using to determine if locking needs to be enforced. This patch detects the locked condition and tries to clear TPM and reboot the system. TEST=take an OCP monolake running vendor BIOS that uses TXT. Ungracefully shut down the system and reflash with coreboot image. With this patch system manages to get out of bricked state. Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42711/1 diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index ef41b77..d4cd0ad 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,7 @@ #include <stddef.h> #include <soc/romstage.h> +#include <soc/memory.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <drivers/vpd/vpd.h> #include <cpu/x86/msr.h> @@ -26,6 +27,9 @@ #include <soc/pci_devs.h> #include <soc/lpc.h> #include <soc/gpio.h> +#include <security/tpm/tspi.h> +#include <security/tpm/tis.h> + /* Define the strings for UPD variables that could be customized */ @@ -207,6 +211,23 @@ printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); full_reset(); } + + /* + * If system have been using TXT and has been ungracefully shutdown and reflashed, + * on next boot TXT fw compares IBB hash against PCR0 in TPM. On mismatch memory + * configuration is locked as a security measure. If we detect this condition we + * can try resetting and clearing TPM, which makes system usable again. + */ + if (memory_config_is_locked()) { + console_init(); + printk(BIOS_EMERG, "Memory configuration is locked! Clearing TPM.\n"); + tpm_setup(false); + if (tpm_clear_and_reenable() != TPM_SUCCESS) { + printk(BIOS_EMERG, "TPM clear success, resetting\n"); + full_reset(); + } + die("TPM reset failed. Giving up\n"); + } } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/42711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe Gerrit-Change-Number: 42711 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/skylake: Enable CIO depending on devicetree configuration
by Felix Singer (Code Review) Aug. 8, 2020

Aug. 8, 2020

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44032 ) Change subject: soc/intel/skylake: Enable CIO depending on devicetree configuration ...................................................................... soc/intel/skylake: Enable CIO depending on devicetree configuration Currently CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the CIO controller. I checked all corresponding mainboards if the devicetree configuration matches the Cio2Enable setting. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 19 files changed, 18 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44032/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b3d9929..294ae44 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -49,7 +49,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -125,6 +124,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index bede4e3..6078741 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -39,7 +39,6 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "Cio2Enable" = "0" register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" @@ -243,6 +242,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8d15e8e..b42d917 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -42,7 +42,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -295,6 +294,7 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e8412d5..5faf760 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -73,7 +73,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -376,6 +375,7 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2 diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 108470b..98b678a 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -104,6 +103,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 9486147..ce725f6 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -48,7 +48,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "1" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -274,6 +273,7 @@ end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index e672940..3197288 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "1" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -270,6 +269,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 2e1c68a..f318998 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -37,7 +37,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -285,6 +284,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 9dcdde4..8a980ca 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "1" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -291,6 +290,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""SYTS7813"" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 43a7754..3aaeae3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -43,7 +43,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "1" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -298,6 +297,7 @@ end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index d21f984..3587cda 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -48,7 +48,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -282,6 +281,7 @@ end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 64ef501..2bddae2 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" - register "Cio2Enable" = "1" register "ScsEmmcHs400Enabled" = "1" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -271,6 +270,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOMCOHO"" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 8afbb92..b555525 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -11,7 +11,6 @@ register "IoBufferOwnership" = "0" register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" - register "Cio2Enable" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -123,6 +122,7 @@ device domain 0 on device pci 05.0 on end # SA IMGU + device pci 14.3 on end # Camera device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 91552a2..d47eca8 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -50,7 +50,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" @@ -176,6 +175,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index f0759ef..a5b3638 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -39,7 +39,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 60f69c8..23c5712 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -55,7 +55,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -173,6 +172,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 6217de5..edf1333 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -35,7 +35,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -192,6 +191,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C Controller #0 device pci 15.1 on chip drivers/i2c/hid diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 80e89f6..9239fd2 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -229,7 +229,8 @@ memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); - params->PchCio2Enable = config->Cio2Enable; + dev = pcidev_path_on_root(PCH_DEVFN_CIO); + params->PchCio2Enable = dev && dev->enabled; dev = pcidev_path_on_root(SA_DEVFN_IMGU); params->SaImguEnable = dev && dev->enabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 33fe52c..b1cf4dc 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -300,9 +300,6 @@ /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* Camera */ - u8 Cio2Enable; - /* eMMC and SD */ u8 ScsEmmcHs400Enabled; u8 EmmcHs400DllNeed; -- To view, visit https://review.coreboot.org/c/coreboot/+/44032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Gerrit-Change-Number: 44032 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 7