Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44137
to look at the new patch set (#5).
Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST
......................................................................
soc/intel/skylake: acpi: drop HWP's dependency on EIST
Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift
Technology (ISST) - also know as HWP - are two independent mechanisms
for controlling voltage and frequency based on performance hints.
When HWP is enabled, it overrides the software-based EIST. It does not
depend on EIST, though, but can be enabled on its own.
Break up that currently existing dependency in ACPI generation code.
It was tested that HWP can be enabled and gets used by the Linux pstate
cpufreq driver. With HWP disabled, the frequency does not decrease, even
not in powersave mode. After enabling HWP the frequency changed in
relation to the current workload. (Test device: Acer ES1-572)
Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/skylake/acpi.c
1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44137/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda
Gerrit-Change-Number: 44137
Gerrit-PatchSet: 5
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Matt Delco <delco(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44291 )
Change subject: mb/google/zork/trembyle: comment why USB OC pin mapping is different
......................................................................
mb/google/zork/trembyle: comment why USB OC pin mapping is different
Change-Id: I68b7529733e604ac45919a54e094be7eeb044458
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/google/zork/variants/trembyle/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44291/1
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
index 26d9a3e..4ceaeb3 100644
--- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -22,7 +22,7 @@
# End : OPN Performance Configuration
- # USB OC pin mapping
+ # USB OC pin mapping: existing trembyle boards are based on old schematics version
register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0
register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0
register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I68b7529733e604ac45919a54e094be7eeb044458
Gerrit-Change-Number: 44291
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Hello Andrey Petrov,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42711
to review the following change.
Change subject: mainboard/ocp/monolake: If memory is locked down, clear TPM and reset
......................................................................
mainboard/ocp/monolake: If memory is locked down, clear TPM and reset
Under certain conditions TXT can force system to come out of reset with
"locked" memory configuration. This manifests itself in IMC's SMBus
controller not being able to read and SPD. FSP does not seem to detect
this condition and simply fails with "no memory found" error. It turned
out IBB measurements are stored in PCR-0 on TPM and that is what TXT fw
seems to be using to determine if locking needs to be enforced.
This patch detects the locked condition and tries to clear TPM and
reboot the system.
TEST=take an OCP monolake running vendor BIOS that uses TXT.
Ungracefully shut down the system and reflash with coreboot image.
With this patch system manages to get out of bricked state.
Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe
Signed-off-by: Andrey Petrov <anpetrov(a)fb.com>
---
M src/mainboard/ocp/monolake/romstage.c
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42711/1
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index ef41b77..d4cd0ad 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -17,6 +17,7 @@
#include <stddef.h>
#include <soc/romstage.h>
+#include <soc/memory.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <drivers/vpd/vpd.h>
#include <cpu/x86/msr.h>
@@ -26,6 +27,9 @@
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/gpio.h>
+#include <security/tpm/tspi.h>
+#include <security/tpm/tis.h>
+
/* Define the strings for UPD variables that could be customized */
@@ -207,6 +211,23 @@
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset();
}
+
+ /*
+ * If system have been using TXT and has been ungracefully shutdown and reflashed,
+ * on next boot TXT fw compares IBB hash against PCR0 in TPM. On mismatch memory
+ * configuration is locked as a security measure. If we detect this condition we
+ * can try resetting and clearing TPM, which makes system usable again.
+ */
+ if (memory_config_is_locked()) {
+ console_init();
+ printk(BIOS_EMERG, "Memory configuration is locked! Clearing TPM.\n");
+ tpm_setup(false);
+ if (tpm_clear_and_reenable() != TPM_SUCCESS) {
+ printk(BIOS_EMERG, "TPM clear success, resetting\n");
+ full_reset();
+ }
+ die("TPM reset failed. Giving up\n");
+ }
}
/**
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe
Gerrit-Change-Number: 42711
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-MessageType: newchange