August 2020 - coreboot-gerrit - mail.coreboot.org

Change in libgfxinit[master]: Add Bay Trail support
by Name of user not set (Code Review) Aug. 9, 2020

Aug. 9, 2020

Name of user not set #1002789 has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/42359 ) Change subject: Add Bay Trail support ...................................................................... Patch Set 36: Noticed when using this on a Minnowboard Max (also WIP) I get the following error when I resume from S3 that I do not get with the VBIOS: primary A assertion failure (expected off, current on) WARNING: CPU: 0 PID: 1458 at drivers/gpu/drm/i915/display/intel_display.c:1278 assert_plane+0xbf/0xd0 [i915] -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Gerrit-Change-Number: 42359 Gerrit-PatchSet: 36 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Name of user not set #1002789 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 09 Aug 2020 16:50:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth (late 2019) [ICL]
by Paul Menzel (Code Review) Aug. 9, 2020

Aug. 9, 2020

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 ) Change subject: mb/razer: Add initial support for the Blade Stealth (late 2019) [ICL] ...................................................................... Patch Set 16: Code-Review+1 Would be nice to get this in. But the weather is too good I guess. ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 16 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Sun, 09 Aug 2020 15:47:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/model_106cx: Factor out common Kconfig options
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44246 ) Change subject: cpu/intel/model_106cx: Factor out common Kconfig options ...................................................................... cpu/intel/model_106cx: Factor out common Kconfig options Note that selecting SSE2 implicitly selects SSE as well. Change-Id: Ia7b34d19325b7c060ea5d02b49cae890629ccbcc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig 3 files changed, 5 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44246/1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 29e7a6c..dbe9b0a 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -5,6 +5,11 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CPU_X86_CACHE + select CPU_X86_LAPIC + select CPU_X86_MTRR + select CPU_X86_SMM + select CPU_X86_TSC + select MMX select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 8b4fdd1..0095c77 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -6,12 +6,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_MODEL_106CX - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select MMX - select SSE select SETUP_XIP_CACHE config C_ENV_BOOTBLOCK_SIZE diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 71796ce..a1598220 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -8,12 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select MMX - select SSE select CPU_HAS_L2_ENABLE_MSR config DCACHE_RAM_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/44246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b34d19325b7c060ea5d02b49cae890629ccbcc Gerrit-Change-Number: 44246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel: Remove broken URLs
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44235 ) Change subject: cpu/intel: Remove broken URLs ...................................................................... cpu/intel: Remove broken URLs These links no longer work. Drop them. They still exist in git history. Change-Id: I1083dbde1c9199a56f711b0230a1bfe6d3174be9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c 5 files changed, 0 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44235/1 diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index cf1394a..8989eec 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -28,16 +28,6 @@ .init = model_65x_init, }; -/* - * Intel Pentium II Processor Specification Update - * http://download.intel.com/design/PentiumII/specupdt/24333749.pdf - * - * Mobile Intel Pentium II Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24388757.pdf - * - * Intel Pentium II Xeon Processor Specification Update - * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf - */ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 427d658..6cfa96c 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -31,13 +31,6 @@ .init = model_67x_init, }; -/* - * Intel Pentium III Processor Identification and Package Information - * http://www.intel.com/design/pentiumiii/qit/update.pdf - * - * Intel Pentium III Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24445358.pdf - */ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0671 }, { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3402c60..22ce332 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -35,19 +35,6 @@ .init = model_68x_init, }; -/* - * Intel Celeron Processor Identification Information - * http://www.intel.com/design/celeron/qit/update.pdf - * - * Intel Pentium III Processor Identification and Package Information - * http://www.intel.com/design/pentiumiii/qit/update.pdf - * - * Intel Pentium III Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24445358.pdf - * - * Mobile Intel Pentium III/III-M Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24530663.pdf - */ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0680 }, { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */ diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 2e7069c..3d633bf 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -35,13 +35,6 @@ .init = model_6bx_init, }; -/* - * Pentium III Processor Identification and Package Information. - * http://www.intel.com/design/pentiumiii/qit/update.pdf - * - * Intel Pentium III Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24445358.pdf - */ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 2e93507b..a6944d3 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -25,31 +25,6 @@ .init = model_6xx_init, }; -/* - * Intel Pentium Pro Processor Specification Update - * http://download.intel.com/design/archives/processors/pro/docs/24268935.pdf - * - * Intel Pentium II Processor Specification Update - * http://download.intel.com/design/PentiumII/specupdt/24333749.pdf - * - * Mobile Intel Pentium II Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24388757.pdf - * - * Intel Celeron Processor Identification Information - * http://www.intel.com/design/celeron/qit/update.pdf - * - * Intel Pentium II Xeon Processor Specification Update - * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf - * - * Intel Pentium III Processor Identification and Package Information - * http://www.intel.com/design/pentiumiii/qit/update.pdf - * - * Intel Pentium III Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24445358.pdf - * - * Mobile Intel Pentium III/III-M Processor Specification Update - * http://download.intel.com/design/intarch/specupdt/24530663.pdf - */ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0611 }, /* Pentium Pro, B0 */ { X86_VENDOR_INTEL, 0x0612 }, /* Pentium Pro, C0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1083dbde1c9199a56f711b0230a1bfe6d3174be9 Gerrit-Change-Number: 44235 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_6xx: Unify all Slot 1 CPUs
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44241 ) Change subject: cpu/intel/model_6xx: Unify all Slot 1 CPUs ...................................................................... cpu/intel/model_6xx: Unify all Slot 1 CPUs Also remove duplicated CPU IDs across two files. This shaves off 64 bytes from the resulting coreboot image for the Asus P2B-DS. Change-Id: I22092d97c244263eec7e65abbfe2bbeb58680fc8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/cpu/intel/model_65x_67x/Makefile.inc D src/cpu/intel/model_65x_67x/model_65x_67x_init.c D src/cpu/intel/model_68x_6bx/Makefile.inc D src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c M src/cpu/intel/model_6xx/Makefile.inc M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/slot_1/Makefile.inc 7 files changed, 34 insertions(+), 118 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44241/1 diff --git a/src/cpu/intel/model_65x_67x/Makefile.inc b/src/cpu/intel/model_65x_67x/Makefile.inc deleted file mode 100644 index 3b78c4e..0000000 --- a/src/cpu/intel/model_65x_67x/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ramstage-y += model_65x_67x_init.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_65x_67x/model_65x_67x_init.c b/src/cpu/intel/model_65x_67x/model_65x_67x_init.c deleted file mode 100644 index 86950e4..0000000 --- a/src/cpu/intel/model_65x_67x/model_65x_67x_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> -#include <cpu/intel/l2_cache.h> - -static void model_65x_67x_init(struct device *cpu) -{ - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Initialize L2 cache */ - p6_configure_l2_cache(); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_65x_67x_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ - { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ - { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ - { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ - - { X86_VENDOR_INTEL, 0x0671 }, - { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ - { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/model_68x_6bx/Makefile.inc b/src/cpu/intel/model_68x_6bx/Makefile.inc deleted file mode 100644 index b12f4d0..0000000 --- a/src/cpu/intel/model_68x_6bx/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ramstage-y += model_68x_6bx_init.c -subdirs-y += ../../x86/name - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c b/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c deleted file mode 100644 index 06ac099..0000000 --- a/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/name.h> - -static void model_68x_6bx_init(struct device *cpu) -{ - char processor_name[49]; - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_68x_6bx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0680 }, - { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */ - { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/ - { X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */ - { X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */ - - { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ - { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ - - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index b2f87ab..83d3dc0 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1,3 +1,9 @@ ramstage-y += model_6xx_init.c +subdirs-y += ../../x86/name + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-06-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 8ebc7ee..b3019c3 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -1,20 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> +#include <cpu/intel/l2_cache.h> +#include <cpu/x86/name.h> static void model_6xx_init(struct device *dev) { /* Update the microcode */ intel_update_microcode_from_cbfs(); + /* Initialize off-die L2 cache */ + if ((dev->device & 0x0ff0) == 0x0650 || (dev->device & 0x0ff0) == 0x0670) + p6_configure_l2_cache(); + /* Turn on caching if we haven't already */ x86_enable_cache(); + /* Print processor name */ + if ((dev->device & 0x0ff0) == 0x0680 || (dev->device & 0x0ff0) == 0x06b0) { + char processor_name[49]; + + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + } + /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -37,10 +52,19 @@ { X86_VENDOR_INTEL, 0x0633 }, /* PII, C0 */ { X86_VENDOR_INTEL, 0x0634 }, /* PII, C1 */ + { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ + { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ + { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ + { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ + { X86_VENDOR_INTEL, 0x0660 }, /* Celeron, A0 */ { X86_VENDOR_INTEL, 0x0665 }, /* Celeron, B0 */ { X86_VENDOR_INTEL, 0x066a }, /* PII, mdxA0/dmmA0 + others */ + { X86_VENDOR_INTEL, 0x0671 }, + { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ + { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */ + { X86_VENDOR_INTEL, 0x0680 }, { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */ { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/ @@ -50,6 +74,10 @@ { X86_VENDOR_INTEL, 0x06a0 }, /* PIII, A0 */ { X86_VENDOR_INTEL, 0x06a1 }, /* PIII, A1 */ { X86_VENDOR_INTEL, 0x06a4 }, /* PIII, B0 */ + + { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ + { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ + { 0, 0 }, }; diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 593e585..dbdb7c3 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -3,8 +3,6 @@ ramstage-y += slot_1.c ramstage-y += l2_cache.c subdirs-y += ../model_6xx -subdirs-y += ../model_65x_67x -subdirs-y += ../model_68x_6bx subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S -- To view, visit https://review.coreboot.org/c/coreboot/+/44241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22092d97c244263eec7e65abbfe2bbeb58680fc8 Gerrit-Change-Number: 44241 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: cpu/intel/model_6xx: Align cosmetics
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44240 ) Change subject: cpu/intel/model_6xx: Align cosmetics ...................................................................... cpu/intel/model_6xx: Align cosmetics Add a comment and remove some spaces to align with similar CPUs. Change-Id: I825766a638581b247281df9d16bcfb9c02a43dad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/44240/1 diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index f394b5f..8ebc7ee 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -14,6 +14,8 @@ /* Turn on caching if we haven't already */ x86_enable_cache(); + + /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -22,7 +24,7 @@ }; static struct device_operations cpu_dev_ops = { - .init = model_6xx_init, + .init = model_6xx_init, }; static const struct cpu_device_id cpu_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/44240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I825766a638581b247281df9d16bcfb9c02a43dad Gerrit-Change-Number: 44240 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_6xx: Update ucode before enabling cache
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44239 ) Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ...................................................................... cpu/intel/model_6xx: Update ucode before enabling cache Other similar CPUs update the microcode first, so do the same here. Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/1 diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index a6944d3..f394b5f 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -9,14 +9,14 @@ static void model_6xx_init(struct device *dev) { + /* Update the microcode */ + intel_update_microcode_from_cbfs(); + /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - /* Enable the local CPU APICs */ setup_lapic(); }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_68x_6bx: Update ucode before enabling cache
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44238 ) Change subject: cpu/intel/model_68x_6bx: Update ucode before enabling cache ...................................................................... cpu/intel/model_68x_6bx: Update ucode before enabling cache Other similar CPUs update the microcode first, so do the same here. Change-Id: I9dda712043e1d17c3cc860d38b5daf8adfa882fa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44238/1 diff --git a/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c b/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c index dc23a7be..06ac099 100644 --- a/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c +++ b/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c @@ -13,12 +13,12 @@ { char processor_name[49]; - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Update the microcode */ intel_update_microcode_from_cbfs(); + /* Turn on caching if we haven't already */ + x86_enable_cache(); + /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); -- To view, visit https://review.coreboot.org/c/coreboot/+/44238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dda712043e1d17c3cc860d38b5daf8adfa882fa Gerrit-Change-Number: 44238 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/intel/model_{68x,6bx}: Unify CPU code
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44237 ) Change subject: cpu/intel/model_{68x,6bx}: Unify CPU code ...................................................................... cpu/intel/model_{68x,6bx}: Unify CPU code Both CPU models have the same initialization sequence, so merge them. Apparently, this does not affect the remaining free space in CBFS. Change-Id: Ic7430e9c98741f4bd3dcf3fdd07ca80d307d2159 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/cpu/intel/model_68x/Makefile.inc A src/cpu/intel/model_68x_6bx/Makefile.inc R src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c D src/cpu/intel/model_6bx/Makefile.inc D src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/slot_1/Makefile.inc 6 files changed, 13 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44237/1 diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc deleted file mode 100644 index e9344b4..0000000 --- a/src/cpu/intel/model_68x/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ramstage-y += model_68x_init.c -subdirs-y += ../../x86/name - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) diff --git a/src/cpu/intel/model_68x_6bx/Makefile.inc b/src/cpu/intel/model_68x_6bx/Makefile.inc new file mode 100644 index 0000000..b12f4d0 --- /dev/null +++ b/src/cpu/intel/model_68x_6bx/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += model_68x_6bx_init.c +subdirs-y += ../../x86/name + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c similarity index 84% rename from src/cpu/intel/model_68x/model_68x_init.c rename to src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c index 22ce332..dc23a7be 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x_6bx/model_68x_6bx_init.c @@ -9,7 +9,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_68x_init(struct device *cpu) +static void model_68x_6bx_init(struct device *cpu) { char processor_name[49]; @@ -32,7 +32,7 @@ } static struct device_operations cpu_dev_ops = { - .init = model_68x_init, + .init = model_68x_6bx_init, }; static const struct cpu_device_id cpu_table[] = { @@ -42,6 +42,9 @@ { X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */ { X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */ + { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ + { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ + { 0, 0 }, }; diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc deleted file mode 100644 index 84f4ff0..0000000 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -ramstage-y += model_6bx_init.c -subdirs-y += ../../x86/name - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*) diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c deleted file mode 100644 index 3d633bf..0000000 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/name.h> - -static void model_6bx_init(struct device *cpu) -{ - char processor_name[49]; - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_6bx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ - { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 489a3c4..593e585 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -4,8 +4,7 @@ ramstage-y += l2_cache.c subdirs-y += ../model_6xx subdirs-y += ../model_65x_67x -subdirs-y += ../model_68x -subdirs-y += ../model_6bx +subdirs-y += ../model_68x_6bx subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S -- To view, visit https://review.coreboot.org/c/coreboot/+/44237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7430e9c98741f4bd3dcf3fdd07ca80d307d2159 Gerrit-Change-Number: 44237 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_{65x,67x}: Unify CPU code
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44236 ) Change subject: cpu/intel/model_{65x,67x}: Unify CPU code ...................................................................... cpu/intel/model_{65x,67x}: Unify CPU code Both CPU models have the same initialization sequence, so merge them. This shaves off 64 bytes when building for the Asus P2B-DS. Change-Id: I88680dc36f48b711ac982ec8091a87996bc78dee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/cpu/intel/model_65x/Makefile.inc A src/cpu/intel/model_65x_67x/Makefile.inc R src/cpu/intel/model_65x_67x/model_65x_67x_init.c D src/cpu/intel/model_67x/Makefile.inc D src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/slot_1/Makefile.inc 6 files changed, 17 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44236/1 diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc deleted file mode 100644 index 16ca902..0000000 --- a/src/cpu/intel/model_65x/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ramstage-y += model_65x_init.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) diff --git a/src/cpu/intel/model_65x_67x/Makefile.inc b/src/cpu/intel/model_65x_67x/Makefile.inc new file mode 100644 index 0000000..3b78c4e --- /dev/null +++ b/src/cpu/intel/model_65x_67x/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += model_65x_67x_init.c + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x_67x/model_65x_67x_init.c similarity index 80% rename from src/cpu/intel/model_65x/model_65x_init.c rename to src/cpu/intel/model_65x_67x/model_65x_67x_init.c index 8989eec..86950e4 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x_67x/model_65x_67x_init.c @@ -8,24 +8,27 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static void model_65x_init(struct device *dev) +static void model_65x_67x_init(struct device *cpu) { /* Update the microcode */ intel_update_microcode_from_cbfs(); + /* Initialize L2 cache */ p6_configure_l2_cache(); /* Turn on caching if we haven't already */ x86_enable_cache(); + + /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); /* Enable the local CPU APICs */ setup_lapic(); -}; +} static struct device_operations cpu_dev_ops = { - .init = model_65x_init, + .init = model_65x_67x_init, }; static const struct cpu_device_id cpu_table[] = { @@ -33,6 +36,10 @@ { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ + + { X86_VENDOR_INTEL, 0x0671 }, + { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ + { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */ { 0, 0 }, }; diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc deleted file mode 100644 index d9b0737..0000000 --- a/src/cpu/intel/model_67x/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ramstage-y += model_67x_init.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*) diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c deleted file mode 100644 index 6cfa96c..0000000 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> -#include <cpu/intel/l2_cache.h> - -static void model_67x_init(struct device *cpu) -{ - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Initialize L2 cache */ - p6_configure_l2_cache(); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); -} - -static struct device_operations cpu_dev_ops = { - .init = model_67x_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0671 }, - { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ - { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */ - - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 856ecf6..489a3c4 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -3,8 +3,7 @@ ramstage-y += slot_1.c ramstage-y += l2_cache.c subdirs-y += ../model_6xx -subdirs-y += ../model_65x -subdirs-y += ../model_67x +subdirs-y += ../model_65x_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../microcode -- To view, visit https://review.coreboot.org/c/coreboot/+/44236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88680dc36f48b711ac982ec8091a87996bc78dee Gerrit-Change-Number: 44236 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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