Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40946 )
Change subject: nb/intel/sandybridge/raminit: Add ECC debug code
......................................................................
nb/intel/sandybridge/raminit: Add ECC debug code
* Add ECC test code when DEBUG_RAM_SETUP is enabled
* Move ECC scrubbing after set_scrambling_seed() to be able to observe
what has been cleared in the test routine.
* ECC scrubbing must happen after dram_dimm_set_mapping()
* Move method out of try_init_dram_ddr3()
Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_native.c
2 files changed, 25 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40946/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 6c8145d..ff563e7 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -366,10 +366,35 @@
set_scrambling_seed(&ctrl);
+ if (!s3resume && ctrl.ecc_enabled)
+ channel_scrub(&ctrl);
+
set_normal_operation(&ctrl);
final_registers(&ctrl);
+ /* can't do this earlier because it needs to be done in normal operation */
+ if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) {
+ uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB);
+
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n",
+ tseg);
+
+ /* Skip first MB to avoid special case for A-seg and test up to TSEG */
+ for (i = 1; i < tseg >> 20; i++) {
+ for (int j = 0; j < 1 * MiB; j += 4096) {
+ uintptr_t addr = i * MiB + j;
+ if (read32((u32 *)addr) == 0)
+ continue;
+
+ printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at"
+ " addr 0x%lx\n", addr);
+ break;
+ }
+ }
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n");
+ }
+
/* Zone config */
dram_zones(&ctrl, 0);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 832391f..34299a3 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -685,9 +685,6 @@
err = channel_test(ctrl);
if (err)
return err;
-
- if (ctrl->ecc_enabled)
- channel_scrub(ctrl);
}
/* Set MAD-DIMM registers */
--
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Gerrit-Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Gerrit-Change-Number: 40946
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Julius Werner, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43604
to look at the new patch set (#9).
Change subject: lib: Add ASan support to romstage on x86 arch
......................................................................
lib: Add ASan support to romstage on x86 arch
This patch adds ASan support to romstage on x86 architecture.
A Kconfig option is added to enable ASan in romstage. Compiler
flags are updated. A memory space representing the shadow region
is reserved in linker section. And a function call to asan_init()
is added to initialize shadow region when romstage loads.
Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381
Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com>
---
M src/Kconfig
M src/arch/x86/assembly_entry.S
M src/arch/x86/car.ld
M src/include/symbols.h
M src/lib/Makefile.inc
M src/lib/asan.c
6 files changed, 66 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43604/9
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Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42794
to look at the new patch set (#18).
Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime
......................................................................
crossgcc: Allow GCC to get asan shadow offset at runtime
Unlike Linux kernel which has a static shadow region layout, we
have multiple stages in coreboot and thus require a different
shadow offset address. Unfortunately, GCC currently
only supports adding a static shadow offset at compile time using
-fasan-shadow-offset flag.
For this reason, we enable GCC to determine asan shadow offset
address at runtime using a callback function named
__asan_shadow_offset(). This supersedes the need to specify
this address at compile time. GCC then makes use of this shadow
offset to protect stack buffers by inserting red zones around
them.
Some other benefits of having this GCC patch are:
1. We can place the shadow region in a separate linker section with
all its advantages like automatic fit insurance. This ensures if
a platform doesn't have enough memory space to hold shadow region,
the build will fail. (However, if we use a fixed shadow offset on a
platform that actually doesn't have enough memory, it may still
build without any errors.)
2. We don't modify the memory layout compared to the current one, as
we are placing the shadow region at the end of the space already
occupied by the program.
3. We can be much more flexible later if needed (thinking of other
stages like bootblock).
4. Since we are appending the shadow buffer to the region already
occupied, we make efficient use of the limited memory available
which is highly beneficial when using cache as ram.
Further, we have made sure that if you compile you tree with ASan
enabled but missed this patch, it will end up in the following
compilation error:
"invalid --param name 'asan-use-shadow-offset-callback'"
So, you cannot accidentally enable the feature without having your
compiler patched.
Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com>
---
A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch
1 file changed, 97 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/18
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Gerrit-PatchSet: 18
Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com>
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 )
Change subject: mb/clevo/kbl-u: Add Clevo N130WU/N131WU
......................................................................
Patch Set 123:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/28640/104/src/mainboard/clevo/kbl-…
File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/28640/104/src/mainboard/clevo/kbl-…
PS104, Line 21: select SOC_INTEL_COMMON_BLOCK_HDA_VERB
> Done
uhm.... no idea what I smoked but this is obviously wrong... doesn't need to get selected
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44116 )
Change subject: mb/google/volteer: Pull up GPP_D16 instead of driving it
......................................................................
mb/google/volteer: Pull up GPP_D16 instead of driving it
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/volteer/variants/volteer/gpio.c
M src/mainboard/google/volteer/variants/volteer2/gpio.c
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c
index 9c36138..8bbc447 100644
--- a/src/mainboard/google/volteer/variants/volteer/gpio.c
+++ b/src/mainboard/google/volteer/variants/volteer/gpio.c
@@ -91,7 +91,7 @@
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
- PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ PAD_NC(GPP_D16, UP_20K),
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
PAD_CFG_GPO(GPP_D17, 1, DEEP),
/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c
index 2b99e52..96d940a 100644
--- a/src/mainboard/google/volteer/variants/volteer2/gpio.c
+++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c
@@ -91,7 +91,7 @@
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
- PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ PAD_NC(GPP_D16, UP_20K),
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
PAD_CFG_GPO(GPP_D17, 1, DEEP),
/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
--
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Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com>
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Gerrit-MessageType: merged
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44356 )
Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen
......................................................................
Patch Set 1:
This change is ready for review.
--
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Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b
Gerrit-Change-Number: 44356
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Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com>
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John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44347 )
Change subject: soc/intel/tigerlake: Add USB4 _DSM for retimer firmware upgrade support
......................................................................
soc/intel/tigerlake: Add USB4 _DSM for retimer firmware upgrade support
There is need to upgrade retimer firmware even if USB4 link is not up.
This change adds USB4 _DSM method to support retimer firmware upgrade.
The retimer force power GPIO state is queried and set accordingly.
BUG=b:162528868
TEST=Built and booted to kernel successfully on Volteer and TGLRVP.
TBD with kernel driver update to validate retimer firmware upgrade.
Signed-off-by: John Zhao <john.zhao(a)intel.com>
Change-Id: I34006972124fa7b04380410669b0cb5051c4f518
---
M src/soc/intel/tigerlake/acpi/tcss_dma.asl
1 file changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44347/1
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index da2e8fe..39d55e9 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -105,7 +105,81 @@
)
}
+/*
+ * Retimer Device Specific Method
+ *
+ * Arg0: UUID (set to 61788900-c470-42bb-80f0-23a313864593)
+ * Arg1: Revision ID (set to 1)
+ * Arg2: Function Index
+ * 0: Query command implemented
+ * 1: Query force power enable state
+ * 2: Set force power state
+ * 0x3 - 0xffff: Reserved
+ * Arg3: A package containing parameters for the function specified
+ * by the UUID, revsion ID and functon index.
+ */
Method (_DSM, 4, Serialized)
{
- Return (Buffer() { 0 })
+ Name (PWR, 0)
+ If (Arg0 == ToUUID("61788900-c470-42bb-80f0-23a313864593")) {
+ switch (ToInteger(Arg2)) {
+ /*
+ * Function Index: 0 - Standard query
+ * Return: Bitmask of supported functions
+ */
+ case (0) {
+ If (Arg1 == 1) {
+ /* Support all functions */
+ Return (Buffer() { 0x07 })
+ }
+
+ /* Only support query if unknown revision */
+ Return (Buffer() { 0x01 })
+ }
+
+ /*
+ * Function Index: 1 - Query force power state
+ * Arg3: Empty package
+ * Return: 0 - if force power is disabled
+ * 1 - if force power is enabled
+ */
+ case (1) {
+ Return (PWR)
+ }
+
+ /*
+ * Function Index: 2 - Set force power state
+ * Arg3: A package consisting a single integer
+ * 0: Turn off power
+ * 1: Turn on powe
+ * Return: 0
+ */
+ case (2) {
+ CreateDWordField (Arg3, 0, CDW1)
+ If (CDW1 == PWR) {
+ /* Already in the state */
+ Return (0)
+ }
+
+ If (CDW1 == 0) {
+ /* Turn off power to the retimer */
+ CTXS(RT_FORCE_PWR)
+ } ElseIf (CDW1 == 1) {
+ /* Turn on power to the retimer */
+ STXS(RT_FORCE_PWR)
+ } Else {
+ Return (0)
+ }
+
+ PWR = CDW1
+ Return (0)
+ }
+
+ Default {
+ Return (Buffer() { 0 })
+ }
+ }
+ } Else {
+ Return (Buffer() { 0 })
+ }
}
--
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