August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Werner Zeh (Code Review) Aug. 11, 2020

Aug. 11, 2020

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 11 Aug 2020 06:33:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix ECC scrub
by Patrick Rudolph (Code Review) Aug. 11, 2020

Aug. 11, 2020

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40721 ) Change subject: nb/intel/sandybridge/raminit: Fix ECC scrub ...................................................................... nb/intel/sandybridge/raminit: Fix ECC scrub The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. * Add ECC test code when DEBUG_RAM_SETUP * Move ECC srubbing after set_scrambling_seed() to be able to observe what has been cleared. * ECC scrubbing must happen after dram_dimm_set_mapping() * Move method out of try_init_dram_ddr3() * Add comments with observations made while fixing the code Tested on HPZ220 with ECC memory and XeonE3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 82 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40721/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6c8145d..2b0cb5e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -366,10 +366,37 @@ set_scrambling_seed(&ctrl); + if (!s3resume && ctrl.ecc_enabled) + channel_scrub(&ctrl); + set_normal_operation(&ctrl); final_registers(&ctrl); + if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { + /* Test ECC in normal mode! */ + + uint32_t tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); + int i; + + printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", + tseg); + + /* Skip A-seg and test up to TSEG */ + for (i = 1; i < tseg >> 20; i++) { + for (int j = 0; j < 1 * MiB; j += 4096) { + uintptr_t addr = (i * MiB) + j; + if (read32((u32 *)addr) == 0) + continue; + + printk(BIOS_ERR, "RAMINIT: DRAM not clear at addr 0x%lx\n", + addr); + break; + } + } + printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); + } + /* Zone config */ dram_zones(&ctrl, 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 087ba2b..9cbc769 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,8 +18,9 @@ /* FIXME: no support for 3-channel chipsets */ -/* length: [1..4] */ -#define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) +/* length: [1..4], repeat: [1..255] */ +#define IOSAV_RUN_MULTIPLE(length, repeat) ((((length) - 1) << 18) | (repeat)) +#define IOSAV_RUN_ONCE(length) IOSAV_RUN_MULTIPLE(length, 1) static void sfence(void) { @@ -297,8 +298,14 @@ reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* Rank interleave */ - reg |= 1 << 22; /* Enhanced interleave */ + /* + * Rank interleave: Bit 16 of the physical address space sets + * the rank to use in a dual single rank DIMM configuration. + * That results in every 64KiB being interleaved between two ranks. + */ + reg |= 1 << 21; + /* Enhanced interleave */ + reg |= 1 << 22; if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { ctrl->mad_dimm[channel] = reg; @@ -322,7 +329,7 @@ MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; } - //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ + udelay(10); } void dram_zones(ramctr_timing *ctrl, int training) @@ -2948,39 +2955,56 @@ void channel_scrub(ramctr_timing *ctrl) { int channel, slotrank, row, rowsize; + u8 bank; + + + FOR_ALL_POPULATED_CHANNELS { + wait_for_iosav(channel); + fill_pattern0(ctrl, channel, 0, 0); + MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; + } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; - for (row = 0; row < rowsize; row += 16) { + rowsize = 1 << ctrl->info.dimm[channel][!!(slotrank & 0xC)].row_bits; + /* Guessed based on oberservation: + * Writes 128 * 8 bytes + * Bank bits are located at 13:15 + * Rowbits start at bit 20 + */ + for (bank = 0; bank < 8; bank ++) { + for (row = 0; row < rowsize; row += 16) { - wait_for_iosav(channel); + /* DRAM command ACT */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = + (ctrl->tRCD << 16) | + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + | 1; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = + row | 0x60000 | (slotrank << 24) | (bank << 20); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; - /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 1 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - row | 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; + /* DRAM command WR */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08000000 | + ((ctrl->tWTR + ctrl->CWL + 8) << 16) | (4 << 10) | 0x81; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | + (slotrank << 24) | (bank << 20); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000122; - /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281081; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; + /* DRAM command PRE */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00000000 | + (ctrl->tRP << 16) | (4 << 10) | 1; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = 0x60000 | + (slotrank << 24) | (bank << 20) | 0x400; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; - /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00280c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; + /* execute command queue */ + MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_MULTIPLE(3, 16); - /* execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); - - wait_for_iosav(channel); + wait_for_iosav(channel); + } } } } diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 832391f..34299a3 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -685,9 +685,6 @@ err = channel_test(ctrl); if (err) return err; - - if (ctrl->ecc_enabled) - channel_scrub(ctrl); } /* Set MAD-DIMM registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Gerrit-Change-Number: 40721 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC debug code
by Patrick Rudolph (Code Review) Aug. 11, 2020

Aug. 11, 2020

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40946 ) Change subject: nb/intel/sandybridge/raminit: Add ECC debug code ...................................................................... nb/intel/sandybridge/raminit: Add ECC debug code * Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. * ECC scrubbing must happen after dram_dimm_set_mapping() * Move method out of try_init_dram_ddr3() Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_native.c 2 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40946/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6c8145d..ff563e7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -366,10 +366,35 @@ set_scrambling_seed(&ctrl); + if (!s3resume && ctrl.ecc_enabled) + channel_scrub(&ctrl); + set_normal_operation(&ctrl); final_registers(&ctrl); + /* can't do this earlier because it needs to be done in normal operation */ + if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { + uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); + + printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", + tseg); + + /* Skip first MB to avoid special case for A-seg and test up to TSEG */ + for (i = 1; i < tseg >> 20; i++) { + for (int j = 0; j < 1 * MiB; j += 4096) { + uintptr_t addr = i * MiB + j; + if (read32((u32 *)addr) == 0) + continue; + + printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at" + " addr 0x%lx\n", addr); + break; + } + } + printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); + } + /* Zone config */ dram_zones(&ctrl, 0); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 832391f..34299a3 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -685,9 +685,6 @@ err = channel_test(ctrl); if (err) return err; - - if (ctrl->ecc_enabled) - channel_scrub(ctrl); } /* Set MAD-DIMM registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Gerrit-Change-Number: 40946 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add ASan support to romstage on x86 arch
by Harshit Sharma (Code Review) Aug. 10, 2020

Aug. 10, 2020

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Julius Werner, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43604 to look at the new patch set (#9). Change subject: lib: Add ASan support to romstage on x86 arch ...................................................................... lib: Add ASan support to romstage on x86 arch This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M src/Kconfig M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/symbols.h M src/lib/Makefile.inc M src/lib/asan.c 6 files changed, 66 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43604/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/43604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Gerrit-Change-Number: 43604 Gerrit-PatchSet: 9 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) Aug. 10, 2020

Aug. 10, 2020

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 18: (5 comments) https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@11 PS17, Line 11: , > Not needed. Done https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@11 PS17, Line 11: at each stage > By "thus" a few words earlier you already mean "multiple stages". […] Done https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@16 PS17, Line 16: a callback function > Maybe better "... […] Done https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@26 PS17, Line 26: the build fails > "the build will fail. […] Done https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@34 PS17, Line 34: , > Not needed here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 10 Aug 2020 22:33:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) Aug. 10, 2020

Aug. 10, 2020

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42794 to look at the new patch set (#18). Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... crossgcc: Allow GCC to get asan shadow offset at runtime Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address. Unfortunately, GCC currently only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function named __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then makes use of this shadow offset to protect stack buffers by inserting red zones around them. Some other benefits of having this GCC patch are: 1. We can place the shadow region in a separate linker section with all its advantages like automatic fit insurance. This ensures if a platform doesn't have enough memory space to hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a platform that actually doesn't have enough memory, it may still build without any errors.) 2. We don't modify the memory layout compared to the current one, as we are placing the shadow region at the end of the space already occupied by the program. 3. We can be much more flexible later if needed (thinking of other stages like bootblock). 4. Since we are appending the shadow buffer to the region already occupied, we make efficient use of the limited memory available which is highly beneficial when using cache as ram. Further, we have made sure that if you compile you tree with ASan enabled but missed this patch, it will end up in the following compilation error: "invalid --param name 'asan-use-shadow-offset-callback'" So, you cannot accidentally enable the feature without having your compiler patched. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/kbl-u: Add Clevo N130WU/N131WU
by Michael Niewöhner (Code Review) Aug. 10, 2020

Aug. 10, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/kbl-u: Add Clevo N130WU/N131WU ...................................................................... Patch Set 123: (1 comment) This change is ready for review. https://review.coreboot.org/c/coreboot/+/28640/104/src/mainboard/clevo/kbl-… File src/mainboard/clevo/kbl-u/Kconfig: https://review.coreboot.org/c/coreboot/+/28640/104/src/mainboard/clevo/kbl-… PS104, Line 21: select SOC_INTEL_COMMON_BLOCK_HDA_VERB > Done uhm.... no idea what I smoked but this is obviously wrong... doesn't need to get selected -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 123 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michael Niewöhner Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Mon, 10 Aug 2020 22:18:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Pull up GPP_D16 instead of driving it
by Nick Vaccaro (Code Review) Aug. 10, 2020

Aug. 10, 2020

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44116 ) Change subject: mb/google/volteer: Pull up GPP_D16 instead of driving it ...................................................................... mb/google/volteer: Pull up GPP_D16 instead of driving it The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to GPP_D16 but there is a RTS5261 requirement to pull up this pin and not drive it at power on. We can meet this requirement without breaking other boards by changing GPP_D16 to be a no-connect with an internal pull up. Other boards use this signal as an enable input, so changing this to pull up is OK. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/volteer/gpio.c M src/mainboard/google/volteer/variants/volteer2/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 9c36138..8bbc447 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -91,7 +91,7 @@ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_D17, 1, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 2b99e52..96d940a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -91,7 +91,7 @@ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_D17, 1, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Gerrit-Change-Number: 44116 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Define stop_gpio for goodix touch screen
by Caveh Jalali (Code Review) Aug. 10, 2020

Aug. 10, 2020

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44356 ) Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Gerrit-Change-Number: 44356 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 10 Aug 2020 21:11:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/terrador: Update gpio settings for Proto2
by David Wu (Code Review) Aug. 10, 2020

Aug. 10, 2020

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44164 ) Change subject: mb/google/volteer/var/terrador: Update gpio settings for Proto2 ...................................................................... mb/google/volteer/var/terrador: Update gpio settings for Proto2 Based on latest schematic and gpio table of terrador, update gpio settings for terrador Proto2. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 --- M src/mainboard/google/volteer/variants/terrador/gpio.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/44164/1 diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index e49e2dc..1a49766 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -20,17 +20,13 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ @@ -54,10 +50,6 @@ PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), - /* C3 : SML0CLK ==> USB4_SMB_SCL */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : SML0DATA ==> USB4_SMB_SDA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ PAD_NC(GPP_C5, DN_20K), /* C7 : SML1DATA ==> EN_USI_CHARGE */ @@ -200,6 +192,8 @@ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 Gerrit-Change-Number: 44164 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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