coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Ravi Kumar Bokka (Code Review) 11 Aug '20

11 Aug '20

Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 88: (6 comments) https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@7 PS87, Line 7: trogdor: SoC makefile BLOB support > Please make it a statement by using a verb (in imperative mood). Done https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@7 PS87, Line 7: BLOB > blob Done https://review.coreboot.org/c/coreboot/+/35508/87//COMMIT_MSG@8 PS87, Line 8: > Please elaborate what blobs are added, and what they are. Done https://review.coreboot.org/c/coreboot/+/35508/84/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/84/src/soc/qualcomm/sc7180/M… PS84, Line 78: none > All of these others should be okay using $(CBFS_COMPRESS_FLAG), not $(CBFS_PRERAM_COMPRESS_FLAG). […] Done https://review.coreboot.org/c/coreboot/+/35508/84/src/soc/qualcomm/sc7180/M… PS84, Line 95: none > $(CBFS_COMPRESS_FLAG) again Done https://review.coreboot.org/c/coreboot/+/35508/84/src/soc/qualcomm/sc7180/M… PS84, Line 103: none > $(CBFS_COMPRESS_FLAG) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 88 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. > > Thanks for checking Tim :-) > TGL can select USE_CAR_NEM_ENHANCED_V2. Oops, yeah that was a typo in Gerrit not in the code, I did use V2 in my Kconfig 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:56:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

1 0

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:49:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… PS3, Line 394: mov %ebx, %ecx > sorry for juggling the regs, I'll try and reduce the re-assignments. […] I had added a comment in PS#4. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Add variant.c to align with dalboz reference board
by Kevin Chiu (Code Review) 11 Aug '20

11 Aug '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44343 ) Change subject: mb/google/zork: Add variant.c to align with dalboz reference board ...................................................................... mb/google/zork: Add variant.c to align with dalboz reference board BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I9dffdf5654680e3c2c0b259ee82a471f8ff14f56 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/Makefile.inc A src/mainboard/google/zork/variants/dirinboz/variant.c 2 files changed, 214 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/44343/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc index 57e7136..51d19fe 100644 --- a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dirinboz/variant.c b/src/mainboard/google/zork/variants/dirinboz/variant.c new file mode 100644 index 0000000..de4338e --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/variant.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/device.h> +#include <drivers/i2c/generic/chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/i2c_tunnel/chip.h> +#include <string.h> + +#define EC_PNP_ID 0x0c09 + +/* Look for an EC device of type PNP with id 0x0c09 */ +static bool match_ec_dev(DEVTREE_CONST struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + return false; + + if (dev->path.pnp.port != EC_PNP_ID) + return false; + + return true; +} + +extern struct chip_operations drivers_i2c_generic_ops; + +/* Look for an I2C device with HID "10EC5682" */ +static bool match_audio_dev(DEVTREE_CONST struct device *dev) +{ + struct drivers_i2c_generic_config *cfg; + + if (dev->chip_ops != &drivers_i2c_generic_ops) + return false; + + cfg = dev->chip_info; + + return !strcmp(cfg->hid, "10EC5682"); +} + +extern struct chip_operations ec_google_chromeec_i2c_tunnel_ops; + +/* Look for Cros EC tunnel device which has audio device under it. */ +static bool match_audio_tunnel(DEVTREE_CONST struct device *dev) +{ + const struct device *audio_dev; + + if (dev->chip_ops != &ec_google_chromeec_i2c_tunnel_ops) + return false; + + audio_dev = dev_find_matching_device_on_bus(dev->link_list, match_audio_dev); + + if (!audio_dev) + return false; + + return true; +} + +/* + * This is to allow support for audio on older board versions (< 2). [b/153458561]. This + * should be removed once these boards are phased out. + */ +static void update_audio_configuration(void) +{ + uint32_t board_version; + const struct device *lpc_controller; + const struct device *ec_dev; + const struct device *i2c_tunnel_dev; + struct ec_google_chromeec_i2c_tunnel_config *cfg; + + /* If CBI board version cannot be read, assume this is an older revision of hardware. */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version >= 2) + return; + + lpc_controller = SOC_LPC_DEV; + if (lpc_controller == NULL) { + printk(BIOS_ERR, "%s: LPC controller device not found!\n", __func__); + return; + } + + ec_dev = dev_find_matching_device_on_bus(lpc_controller->link_list, match_ec_dev); + + if (ec_dev == NULL) { + printk(BIOS_ERR, "%s: EC device not found!\n", __func__); + return; + } + + i2c_tunnel_dev = dev_find_matching_device_on_bus(ec_dev->link_list, match_audio_tunnel); + + if (i2c_tunnel_dev == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device not found!\n", __func__); + return; + } + + cfg = i2c_tunnel_dev->chip_info; + if (cfg == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device config not found!\n", __func__); + return; + } + + cfg->remote_bus = 5; +} + +static int sku_has_emmc(void) +{ + uint32_t board_sku = sku_id(); + + /* Factory flow requires all OS boot media to be enabled. */ + if (boot_is_factory_unprovisioned()) + return 1; + + /* FIXME: This needs to be fw_config controlled. */ + /* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */ + if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN) + return 1; + + return 0; +} + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + if (sku_has_emmc()) { + if ((sku_id() == 0x5A800003) || (sku_id() == 0x5A80000C)) { + /* + * rev0 and rev1 boards have issues with HS400 + * + * There is a tuning fix with ES which shows promise + * for some boards, and a HW fix with stitching vias. + * There were also concerns that these boards did not + * have good margins for certain skus. + * + * But these original boards have none of these fixes. + * So we keep the speed low here, with the intent that + * other variants implement these corrections. + */ + cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + } + } else { + cfg->sd_emmc_config = SD_EMMC_DISABLE; + } + + update_audio_configuration(); +} + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + // DP2 pins not connected on Dali + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + uint32_t board_sku = sku_id(); + + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + + /* SKU 1, A, and D DB have HDMI, as well as unknown */ + /* FIXME: this needs to be fw_config controlled. */ + if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001) + || (board_sku == CROS_SKU_UNKNOWN)) { + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); + } else { + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dffdf5654680e3c2c0b259ee82a471f8ff14f56 Gerrit-Change-Number: 44343 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > Ah ok, I think my confusion was the layout of the register being different between SoCs. […] yes, MSR definition is not documented for TGL, CML, KBL. We can get it revised. https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… PS3, Line 394: mov %ebx, %ecx > maybe comment %ecx is now way size? took me some tracing back to find it sorry for juggling the regs, I'll try and reduce the re-assignments. ecx now holds the number of ways. we need to calculate the and mask for mask register and only configure the mask bit for the number of ways supported. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:45:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: fix incorrect DRAM SPD table load for dirinboz
by Kevin Chiu (Code Review) 11 Aug '20

11 Aug '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44341 ) Change subject: mb/google/zork: fix incorrect DRAM SPD table load for dirinboz ...................................................................... mb/google/zork: fix incorrect DRAM SPD table load for dirinboz BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Ia736b0f25824eebe4ef25a11646f82963611e3b3 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44341/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc index 9dc5159..295acd2 100644 --- a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd -- To view, visit https://review.coreboot.org/c/coreboot/+/44341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia736b0f25824eebe4ef25a11646f82963611e3b3 Gerrit-Change-Number: 44341 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: move USB OC pin mapping to trembyle base board
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44269 ) Change subject: mb/google/zork: move USB OC pin mapping to trembyle base board ...................................................................... mb/google/zork: move USB OC pin mapping to trembyle base board The USB OC pin mapping is similar enough to move it to the base board and just have one override for woomax. Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb 6 files changed, 5 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44269/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1b43cc8..b2bd713 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -139,7 +139,11 @@ .read_mode = SPI_READ_MODE_DUAL122, }" - # common USB OC pin mapping + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 45b80a2..d250311 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -22,12 +22,6 @@ # End : OPN Performance Configuration - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 - # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 1808a0f..246a82b 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -22,12 +22,6 @@ # End : OPN Performance Configuration - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 - register "xhci0_force_gen1" = "1" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index caaddb8..bc98bee 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -22,12 +22,6 @@ # End : OPN Performance Configuration - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 - # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 8b5c14f..bead293 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -22,12 +22,6 @@ # End : OPN Performance Configuration - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 - # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index bdcc9bb..f51bf0c 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -24,10 +24,7 @@ # End : OPN Performance Configuration # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 register "usb_port_overcurrent_pin[2]" = "USB_OC_NONE" # NC - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/44269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2 Gerrit-Change-Number: 44269 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020