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Change in coreboot[master]: mb/intel: Add dh67bl board
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43564 ) Change subject: mb/intel: Add dh67bl board ...................................................................... mb/intel: Add dh67bl board Port not tested. Change-Id: I9dfc4d739ce4bfba83ebba6d9f056168137b88b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/mainboard/intel/dh67bl/Kconfig A src/mainboard/intel/dh67bl/Kconfig.name A src/mainboard/intel/dh67bl/Makefile.inc A src/mainboard/intel/dh67bl/acpi/ec.asl A src/mainboard/intel/dh67bl/acpi/platform.asl A src/mainboard/intel/dh67bl/acpi/superio.asl A src/mainboard/intel/dh67bl/acpi_tables.c A src/mainboard/intel/dh67bl/board_info.txt A src/mainboard/intel/dh67bl/devicetree.cb A src/mainboard/intel/dh67bl/dsdt.asl A src/mainboard/intel/dh67bl/early_init.c A src/mainboard/intel/dh67bl/gma-mainboard.ads A src/mainboard/intel/dh67bl/gpio.c A src/mainboard/intel/dh67bl/hda_verb.c A src/mainboard/intel/dh67bl/mainboard.c 15 files changed, 455 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/43564/1 diff --git a/src/mainboard/intel/dh67bl/Kconfig b/src/mainboard/intel/dh67bl/Kconfig new file mode 100644 index 0000000..fd23585 --- /dev/null +++ b/src/mainboard/intel/dh67bl/Kconfig @@ -0,0 +1,38 @@ +if BOARD_INTEL_DH67BL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "inetl/dh67bl" + +config MAINBOARD_PART_NUMBER + string + default "Intel DH67BL" + +config VGA_BIOS_FILE + string + default "pci8086,0102.rom" + +config VGA_BIOS_ID + string + default "8086,0102" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/intel/dh67bl/Kconfig.name b/src/mainboard/intel/dh67bl/Kconfig.name new file mode 100644 index 0000000..b907186 --- /dev/null +++ b/src/mainboard/intel/dh67bl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DH67BL + bool "Intel DH67BL" diff --git a/src/mainboard/intel/dh67bl/Makefile.inc b/src/mainboard/intel/dh67bl/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/intel/dh67bl/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dh67bl/acpi/ec.asl b/src/mainboard/intel/dh67bl/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/intel/dh67bl/acpi/ec.asl diff --git a/src/mainboard/intel/dh67bl/acpi/platform.asl b/src/mainboard/intel/dh67bl/acpi/platform.asl new file mode 100644 index 0000000..146be65 --- /dev/null +++ b/src/mainboard/intel/dh67bl/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/intel/dh67bl/acpi/superio.asl b/src/mainboard/intel/dh67bl/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/intel/dh67bl/acpi/superio.asl diff --git a/src/mainboard/intel/dh67bl/acpi_tables.c b/src/mainboard/intel/dh67bl/acpi_tables.c new file mode 100644 index 0000000..251673e --- /dev/null +++ b/src/mainboard/intel/dh67bl/acpi_tables.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/intel/dh67bl/board_info.txt b/src/mainboard/intel/dh67bl/board_info.txt new file mode 100644 index 0000000..6e54abb --- /dev/null +++ b/src/mainboard/intel/dh67bl/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: n? diff --git a/src/mainboard/intel/dh67bl/devicetree.cb b/src/mainboard/intel/dh67bl/devicetree.cb new file mode 100644 index 0000000..4c594a2 --- /dev/null +++ b/src/mainboard/intel/dh67bl/devicetree.cb @@ -0,0 +1,57 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x8086 0x2002 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0241" + register "gen2_dec" = "0x00fc0291" + register "gen3_dec" = "0x00fc0251" + register "gen4_dec" = "0x00fc02a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + end +end diff --git a/src/mainboard/intel/dh67bl/dsdt.asl b/src/mainboard/intel/dh67bl/dsdt.asl new file mode 100644 index 0000000..dcbc592 --- /dev/null +++ b/src/mainboard/intel/dh67bl/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/intel/dh67bl/early_init.c b/src/mainboard/intel/dh67bl/early_init.c new file mode 100644 index 0000000..3080863 --- /dev/null +++ b/src/mainboard/intel/dh67bl/early_init.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ +// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); +// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* DH67BL board has 4 DIMM slots */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/intel/dh67bl/gma-mainboard.ads b/src/mainboard/intel/dh67bl/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/intel/dh67bl/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/intel/dh67bl/gpio.c b/src/mainboard/intel/dh67bl/gpio.c new file mode 100644 index 0000000..2be1da4 --- /dev/null +++ b/src/mainboard/intel/dh67bl/gpio.c @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/intel/dh67bl/hda_verb.c b/src/mainboard/intel/dh67bl/hda_verb.c new file mode 100644 index 0000000..07ed3ec --- /dev/null +++ b/src/mainboard/intel/dh67bl/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x80862002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x80862002), + AZALIA_PIN_CFG(0, 0x11, 0x01446130), + AZALIA_PIN_CFG(0, 0x12, 0x4013c040), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19050), + AZALIA_PIN_CFG(0, 0x19, 0x02a19060), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4046f601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80862805, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80862805), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/dh67bl/mainboard.c b/src/mainboard/intel/dh67bl/mainboard.c new file mode 100644 index 0000000..f4a5175 --- /dev/null +++ b/src/mainboard/intel/dh67bl/mainboard.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfc4d739ce4bfba83ebba6d9f056168137b88b5 Gerrit-Change-Number: 43564 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: (test) -Werror=unused-variable
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40614 ) Change subject: (test) -Werror=unused-variable ...................................................................... (test) -Werror=unused-variable Change-Id: I3ee9b577fbd9ba2443fbbd22380e0b3fd368b633 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40614/1 diff --git a/Makefile.inc b/Makefile.inc index e315732..0ce6c4d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -421,7 +421,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla -CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else +CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else -unused-variable CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/40614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ee9b577fbd9ba2443fbbd22380e0b3fd368b633 Gerrit-Change-Number: 40614 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 15

Change in coreboot[master]: Makefile.inc: Remove '-Wstrict-aliasing'
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41764 ) Change subject: Makefile.inc: Remove '-Wstrict-aliasing' ...................................................................... Makefile.inc: Remove '-Wstrict-aliasing' '-Wstrict-aliasing' warning flag is already turned on with '-Wall'. Change-Id: I8212cfa5d67fba854ee84dd9d560cd7f8a27632e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41764/1 diff --git a/Makefile.inc b/Makefile.inc index 210e9cf..c401b54 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -407,7 +407,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -- To view, visit https://review.coreboot.org/c/coreboot/+/41764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8212cfa5d67fba854ee84dd9d560cd7f8a27632e Gerrit-Change-Number: 41764 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: [test] extent of damage
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43280 ) Change subject: [test] extent of damage ...................................................................... [test] extent of damage Change-Id: I38bf5a33f989c99e3fe720df93cc4741aa4df732 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43280/1 diff --git a/Makefile.inc b/Makefile.inc index 89bb3e4..428ca35 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -255,20 +255,20 @@ # possibly true in many cases. In other cases it seems that an empty # ResourceTemplate is the correct code. # As it's valid ASL, disable the warning. -EMPTY_RESOURCE_TEMPLATE_WARNING = 3150 +# EMPTY_RESOURCE_TEMPLATE_WARNING = 3150 # Redundant offset remarks are not useful in any way and are masking useful # ones that might indicate an issue so it is better to hide them. -REDUNDANT_OFFSET_REMARK = 2158 +# REDUNDANT_OFFSET_REMARK = 2158 # Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code. # See cb:38803 & cb:38802 # "Multiple types (Device object requires either a _HID or _ADR, but not both)" -MULTIPLE_TYPES_WARNING = 3073 +# MULTIPLE_TYPES_WARNING = 3073 -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) -else -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -endif +#ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) +#IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) +#else +#IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) +#endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml -- To view, visit https://review.coreboot.org/c/coreboot/+/43280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38bf5a33f989c99e3fe720df93cc4741aa4df732 Gerrit-Change-Number: 43280 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: payloads/libpayload/libc: uppgrade qsort.c to v1.15
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43717 ) Change subject: payloads/libpayload/libc: uppgrade qsort.c to v1.15 ...................................................................... payloads/libpayload/libc: uppgrade qsort.c to v1.15 Change-Id: I3ab8d4b2c5ac782b949e244749ca285ed4700283 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/libpayload/libc/qsort.c 1 file changed, 42 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43717/1 diff --git a/payloads/libpayload/libc/qsort.c b/payloads/libpayload/libc/qsort.c index aad2aa3..51d67bc 100644 --- a/payloads/libpayload/libc/qsort.c +++ b/payloads/libpayload/libc/qsort.c @@ -1,4 +1,4 @@ -/* $OpenBSD: qsort.c,v 1.11 2010/02/08 11:04:07 otto Exp $ */ +/* $OpenBSD: qsort.c,v 1.15 2017/05/17 16:58:20 millert Exp $ */ /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. @@ -39,11 +39,11 @@ /* * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". */ -#define swapcode(TYPE, parmi, parmj, n) { \ - size_t i = (n) / sizeof (TYPE); \ - TYPE *pi = (TYPE *) (parmi); \ - TYPE *pj = (TYPE *) (parmj); \ - do { \ +#define swapcode(TYPE, parmi, parmj, n) { \ + size_t i = (n) / sizeof(TYPE); \ + TYPE *pi = (TYPE *) (parmi); \ + TYPE *pj = (TYPE *) (parmj); \ + do { \ TYPE t = *pi; \ *pi++ = *pj; \ *pj++ = t; \ @@ -70,7 +70,7 @@ } else \ swapfunc(a, b, es, swaptype) -#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) +#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) static __inline char * med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *)) @@ -84,23 +84,22 @@ qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)) { char *pa, *pb, *pc, *pd, *pl, *pm, *pn; - int cmp_result, swaptype, swap_cnt; - size_t d, r; + int cmp_result, swaptype; + size_t d, r, s; char *a = aa; loop: SWAPINIT(a, es); - swap_cnt = 0; if (n < 7) { - for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es) - for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; + for (pm = a + es; pm < a + n * es; pm += es) + for (pl = pm; pl > a && cmp(pl - es, pl) > 0; pl -= es) swap(pl, pl - es); return; } - pm = (char *)a + (n / 2) * es; + pm = a + (n / 2) * es; if (n > 7) { - pl = (char *)a; - pn = (char *)a + (n - 1) * es; + pl = a; + pn = a + (n - 1) * es; if (n > 40) { d = (n / 8) * es; pl = med3(pl, pl + d, pl + 2 * d, cmp); @@ -110,13 +109,12 @@ pm = med3(pl, pm, pn, cmp); } swap(a, pm); - pa = pb = (char *)a + es; + pa = pb = a + es; - pc = pd = (char *)a + (n - 1) * es; + pc = pd = a + (n - 1) * es; for (;;) { while (pb <= pc && (cmp_result = cmp(pb, a)) <= 0) { if (cmp_result == 0) { - swap_cnt = 1; swap(pa, pb); pa += es; } @@ -124,7 +122,6 @@ } while (pb <= pc && (cmp_result = cmp(pc, a)) >= 0) { if (cmp_result == 0) { - swap_cnt = 1; swap(pc, pd); pd -= es; } @@ -133,30 +130,38 @@ if (pb > pc) break; swap(pb, pc); - swap_cnt = 1; pb += es; pc -= es; } - if (swap_cnt == 0) { /* Switch to insertion sort */ - for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es) - for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; - pl -= es) - swap(pl, pl - es); - return; - } - pn = (char *)a + n * es; - r = min(pa - (char *)a, pb - pa); + pn = a + n * es; + r = min(pa - a, pb - pa); vecswap(a, pb - r, r); r = min(pd - pc, pn - pd - es); vecswap(pb, pn - r, r); - if ((r = pb - pa) > es) - qsort(a, r / es, es, cmp); - if ((r = pd - pc) > es) { - /* Iterate rather than recurse to save stack space */ - a = pn - r; - n = r / es; - goto loop; + /* + * To save stack space we sort the smaller side of the partition first + * using recursion and eliminate tail recursion for the larger side. + */ + r = pb - pa; + s = pd - pc; + if (r < s) { + /* Recurse for 1st side, iterate for 2nd side. */ + if (s > es) { + if (r > es) + qsort(a, r / es, es, cmp); + a = pn - s; + n = s / es; + goto loop; + } + } else { + /* Recurse for 2nd side, iterate for 1st side. */ + if (r > es) { + if (s > es) + qsort(pn - s, s / es, es, cmp); + n = r / es; + goto loop; + } } -/* qsort(pn - r, r / es, es, cmp);*/ } +DEF_STRONG(qsort); -- To view, visit https://review.coreboot.org/c/coreboot/+/43717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ab8d4b2c5ac782b949e244749ca285ed4700283 Gerrit-Change-Number: 43717 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: src/acpi/acpi.c: Convert to 96 characters line length
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43009 ) Change subject: src/acpi/acpi.c: Convert to 96 characters line length ...................................................................... src/acpi/acpi.c: Convert to 96 characters line length Change-Id: I8ea21ba3b36f90dc9ea0eca5de0bd9f964d47957 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c 1 file changed, 64 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43009/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 781e398..ae8ee9f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + /* * coreboot ACPI Table support */ @@ -9,8 +10,7 @@ * write_acpi_tables() * acpi_dump_apics() * - * See Kontron 986LCD-M port for a good example of an ACPI implementation - * in coreboot. + * See Kontron 986LCD-M port for a good example of an ACPI implementation in coreboot. */ #include <console/console.h> @@ -39,8 +39,7 @@ } /** - * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length - * and checksum. + * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length and checksum. */ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) { @@ -64,8 +63,7 @@ } if (i >= entries_num) { - printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, " - "too many tables.\n"); + printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, too many tables.\n"); return; } @@ -88,21 +86,19 @@ xsdt->entry[i] = (u64)(uintptr_t)table; /* Fix XSDT length. */ - xsdt->header.length = sizeof(acpi_header_t) + - (sizeof(u64) * (i + 1)); + xsdt->header.length = sizeof(acpi_header_t) + (sizeof(u64) * (i + 1)); /* Re-calculate checksum. */ xsdt->header.checksum = 0; - xsdt->header.checksum = acpi_checksum((u8 *)xsdt, - xsdt->header.length); + xsdt->header.checksum = acpi_checksum((u8 *)xsdt, xsdt->header.length); } printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n", i + 1, entries_num, rsdt->header.length); } -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) +int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, + u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; @@ -144,7 +140,7 @@ for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; } if (!cpu->enabled) @@ -167,8 +163,7 @@ return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base) +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base) { ioapic->type = IO_APIC; /* I/O APIC structure */ ioapic->length = sizeof(acpi_madt_ioapic_t); @@ -180,8 +175,8 @@ return ioapic->length; } -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags) +int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, + u32 gsirq, u16 flags) { irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ irqoverride->length = sizeof(acpi_madt_irqoverride_t); @@ -193,8 +188,7 @@ return irqoverride->length; } -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint) +int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t); @@ -205,8 +199,7 @@ return lapic_nmi->length; } -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint) +int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lx2apic_nmi_t); @@ -492,8 +485,7 @@ return lapic->length; } -int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, - u32 flags) +int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags) { mem->type = 1; /* Memory affinity structure */ mem->length = sizeof(acpi_srat_mem_t); @@ -508,8 +500,7 @@ } /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ -void acpi_create_srat(acpi_srat_t *srat, - unsigned long (*acpi_fill_srat)(unsigned long current)) +void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) { acpi_header_t *header = &(srat->header); unsigned long current = (unsigned long)srat + sizeof(acpi_srat_t); @@ -569,8 +560,7 @@ header->checksum = acpi_checksum((void *)dmar, header->length); } -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u64 bar) +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, u16 segment, u64 bar) { dmar_entry_t *drhd = (dmar_entry_t *)current; memset(drhd, 0, sizeof(*drhd)); @@ -583,8 +573,7 @@ return drhd->length; } -unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, - u64 bar, u64 limit) +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit) { dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)current; memset(rmrr, 0, sizeof(*rmrr)); @@ -597,8 +586,7 @@ return rmrr->length; } -unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, - u16 segment) +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment) { dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)current; memset(atsr, 0, sizeof(*atsr)); @@ -610,8 +598,7 @@ return atsr->length; } -unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, - u32 proximity_domain) +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, u32 proximity_domain) { dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)current; memset(rhsa, 0, sizeof(*rhsa)); @@ -624,7 +611,7 @@ } unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, - const char *device_name) + const char *device_name) { dmar_andd_entry_t *andd = (dmar_andd_entry_t *)current; int andd_len = sizeof(dmar_andd_entry_t) + strlen(device_name) + 1; @@ -655,8 +642,8 @@ atsr->length = current - base; } -static unsigned long acpi_create_dmar_ds(unsigned long current, - enum dev_scope_type type, u8 enumeration_id, u8 bus, u8 dev, u8 fn) +static unsigned long acpi_create_dmar_ds(unsigned long current, enum dev_scope_type type, + u8 enumeration_id, u8 bus, u8 dev, u8 fn) { /* we don't support longer paths yet */ const size_t dev_scope_length = sizeof(dev_scope_t) + 2; @@ -673,37 +660,30 @@ return ds->length; } -unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, - u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_PCI_SUB, 0, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_PCI_SUB, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, - u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_PCI_ENDPOINT, 0, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_PCI_ENDPOINT, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, - u8 enumeration_id, u8 bus, u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_IOAPIC, enumeration_id, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, - u8 enumeration_id, u8 bus, u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_MSI_HPET, enumeration_id, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_MSI_HPET, enumeration_id, bus, dev, fn); } /* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */ -void acpi_create_slit(acpi_slit_t *slit, - unsigned long (*acpi_fill_slit)(unsigned long current)) +void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)) { acpi_header_t *header = &(slit->header); unsigned long current = (unsigned long)slit + sizeof(acpi_slit_t); @@ -765,10 +745,9 @@ header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -void acpi_create_vfct(const struct device *device, - acpi_vfct_t *vfct, - unsigned long (*acpi_fill_vfct)(const struct device *device, - acpi_vfct_t *vfct_struct, unsigned long current)) +void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, + unsigned long (*acpi_fill_vfct)(const struct device *device, acpi_vfct_t *vfct_struct, + unsigned long current)) { acpi_header_t *header = &(vfct->header); unsigned long current = (unsigned long)vfct + sizeof(acpi_vfct_t); @@ -798,8 +777,7 @@ header->checksum = acpi_checksum((void *)vfct, header->length); } -void acpi_create_ipmi(const struct device *device, - struct acpi_spmi *spmi, +void acpi_create_ipmi(const struct device *device, struct acpi_spmi *spmi, const u16 ipmi_revision, const acpi_addr_t *addr, const enum acpi_ipmi_interface_type type, @@ -879,7 +857,7 @@ } unsigned long acpi_write_hpet(const struct device *device, unsigned long current, - acpi_rsdp_t *rsdp) + acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; @@ -897,10 +875,8 @@ return current; } -void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, - int port_type, int port_subtype, - acpi_addr_t *address, uint32_t address_size, - const char *device_path) +void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, int port_type, int port_subtype, + acpi_addr_t *address, uint32_t address_size, const char *device_path) { uintptr_t current; acpi_dbg2_device_t *device; @@ -984,8 +960,8 @@ } res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { - printk(BIOS_ERR, "%s: Unable to find resource for %s\n", - __func__, dev_path(dev)); + printk(BIOS_ERR, "%s: Unable to find resource for %s\n", __func__, + dev_path(dev)); return current; } @@ -1003,11 +979,8 @@ address.addrh = (uint32_t)((res->base >> 32) & 0xffffffff); address.access_size = access_size; - acpi_create_dbg2(dbg2, - ACPI_DBG2_PORT_SERIAL, - ACPI_DBG2_PORT_SERIAL_16550, - &address, res->size, - acpi_device_path(dev)); + acpi_create_dbg2(dbg2, ACPI_DBG2_PORT_SERIAL, ACPI_DBG2_PORT_SERIAL_16550, &address, + res->size, acpi_device_path(dev)); if (dbg2->header.length) { current += dbg2->header.length; @@ -1079,8 +1052,7 @@ header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } -static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, - acpi_xsdt_t *xsdt, char *oem_id) +static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt, char *oem_id) { memset(rsdp, 0, sizeof(acpi_rsdp_t)); @@ -1109,8 +1081,8 @@ rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } -unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, - acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, + void *data, u16 data_len) { acpi_header_t *header = &(hest->header); acpi_hest_hen_t *hen; @@ -1170,8 +1142,7 @@ } /* ACPI 4.0 */ -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) +void acpi_write_hest(acpi_hest_t *hest, unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) { acpi_header_t *header = &(hest->header); @@ -1251,11 +1222,9 @@ /* should be 0 ACPI 3.0 */ fadt->reserved = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) + if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || CONFIG(SYSTEM_TYPE_LAPTOP)) fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) + else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || CONFIG(SYSTEM_TYPE_TABLET)) fadt->preferred_pm_profile = PM_TABLET; else fadt->preferred_pm_profile = PM_DESKTOP; @@ -1265,8 +1234,7 @@ soc_fill_fadt(fadt); mainboard_fill_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } unsigned long __weak fw_cfg_acpi_tables(unsigned long start) @@ -1346,26 +1314,23 @@ } dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + CONFIG_CBFS_PREFIX "/dsdt.aml", CBFS_TYPE_RAW, &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; } - if (dsdt_file->length > dsdt_size - || dsdt_file->length < sizeof(acpi_header_t) - || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { + if (dsdt_file->length > dsdt_size || dsdt_file->length < sizeof(acpi_header_t) || + memcmp(dsdt_file->signature, "DSDT", 4) != 0) { printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); - if (slic_file - && (slic_file->length > slic_size - || slic_file->length < sizeof(acpi_header_t) - || memcmp(slic_file->signature, "SLIC", 4) != 0)) { + slic_file = cbfs_boot_map_with_leak( + CONFIG_CBFS_PREFIX "/slic", CBFS_TYPE_RAW, &slic_size); + if (slic_file && + (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) || + memcmp(slic_file->signature, "SLIC", 4) != 0)) { slic_file = 0; } @@ -1520,8 +1485,7 @@ return NULL; printk(BIOS_DEBUG, "Checksum 1 passed\n"); - if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp, - rsdp->length) != 0)) + if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp, rsdp->length) != 0)) return NULL; printk(BIOS_DEBUG, "Checksum 2 passed all OK\n"); @@ -1551,8 +1515,7 @@ } if (rsdp == NULL) { - printk(BIOS_ALERT, - "No RSDP found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No RSDP found, wake up from S3 not possible.\n"); return NULL; } @@ -1570,8 +1533,7 @@ } if (fadt == NULL) { - printk(BIOS_ALERT, - "No FADT found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No FADT found, wake up from S3 not possible.\n"); return NULL; } @@ -1579,8 +1541,7 @@ facs = (acpi_facs_t *)(uintptr_t)fadt->firmware_ctrl; if (facs == NULL) { - printk(BIOS_ALERT, - "No FACS found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No FACS found, wake up from S3 not possible.\n"); return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ea21ba3b36f90dc9ea0eca5de0bd9f964d47957 Gerrit-Change-Number: 43009 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: src: Write FADT minor version at 'acpi_create_fadt()'
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42249 ) Change subject: src: Write FADT minor version at 'acpi_create_fadt()' ...................................................................... src: Write FADT minor version at 'acpi_create_fadt()' Change-Id: I5eb12e298bc050c629c3184eb6bb8b6f046fee2b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c 6 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42249/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 47f03c8..a4ea24b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1239,6 +1239,8 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; + fadt->FADT_MinorVersion = 0; + fadt->firmware_ctrl = (unsigned long) facs; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index fe5879c..18626ff 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -149,7 +149,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..2898704 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -121,7 +121,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 719eb54..9fd3141 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -87,7 +87,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index ba277f9..2ecac2e 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -110,7 +110,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8ed0330..b61ec20 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -87,7 +87,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb12e298bc050c629c3184eb6bb8b6f046fee2b Gerrit-Change-Number: 42249 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: include/acpi/acpi.h: Convert to 96 characters line length
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43056 ) Change subject: include/acpi/acpi.h: Convert to 96 characters line length ...................................................................... include/acpi/acpi.h: Convert to 96 characters line length Change-Id: I087126579d253b7873ffdae87c9f14892166d1f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/acpi/acpi.h 1 file changed, 34 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43056/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 05d2197..cab656c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -916,38 +916,30 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table); int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base); -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base); +int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, + u32 gsirq, u16 flags); +int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, - u8 lint); +unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint); +int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, + u8 lint); int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); -int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, - u32 flags); +int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic); int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu); -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); +int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, + u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); -void acpi_create_srat(acpi_srat_t *srat, - unsigned long (*acpi_fill_srat)(unsigned long current)); +void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -void acpi_create_slit(acpi_slit_t *slit, - unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); -void acpi_create_vfct(const struct device *device, - acpi_vfct_t *vfct, +void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(const struct device *device, - acpi_vfct_t *vfct_struct, - unsigned long current)); + acpi_vfct_t *vfct_struct, unsigned long current)); void acpi_create_ipmi(const struct device *device, struct acpi_spmi *spmi, @@ -973,43 +965,32 @@ void acpi_create_facs(acpi_facs_t *facs); -void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, - int port_type, int port_subtype, - acpi_addr_t *address, uint32_t address_size, - const char *device_path); +void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, int port_type, int port_subtype, + acpi_addr_t *address, uint32_t address_size, const char *device_path); unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, const struct device *dev, uint8_t access_size); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u64 bar); -unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, - u64 bar, u64 limit); -unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, - u16 segment); -unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, - u32 proximity_domain); +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, u16 segment, u64 bar); +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, u32 proximity_domain); unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, const char *device_name); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); -unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_pci(unsigned long current, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, - u8 enumeration_id, - u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, - u8 enumeration_id, - u8 bus, u8 dev, u8 fn); -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn); +void acpi_write_hest(acpi_hest_t *hest, unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); -unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, - acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, + void *data, u16 len); /* For ACPI S3 support. */ void acpi_resume(void *wake_vec); @@ -1026,8 +1007,7 @@ ACPI_S5 = 5, }; -#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ - || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) /* Given the provided PM1 control register return the ACPI sleep type. */ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) { @@ -1084,10 +1064,10 @@ return ALIGN_UP(current, 16); } -/* ACPI table revisions should match the revision of the ACPI spec - * supported. This function keeps the table versions synced. This could - * be made into a weak function if there is ever a need to override the - * coreboot default ACPI spec version supported. */ +/* ACPI table revisions should match the revision of the ACPI spec supported. This function + * keeps the table versions synced. This could be made into a weak function if there is ever a + * need to override the coreboot default ACPI spec version supported. + */ int get_acpi_table_revision(enum acpi_tables table); #endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) -- To view, visit https://review.coreboot.org/c/coreboot/+/43056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087126579d253b7873ffdae87c9f14892166d1f7 Gerrit-Change-Number: 43056 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: acpi: Bump SRAT revision to 3
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43054 ) Change subject: acpi: Bump SRAT revision to 3 ...................................................................... acpi: Bump SRAT revision to 3 Regarding ACPI spec 6.3, current SRAT version is 3. Change-Id: I72b9ec3b0e1be4200417c95d5540606b776e1225 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43054/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index df733ce..6db72e8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1601,7 +1601,7 @@ case SSDT: /* ACPI 3.0 upto 6.3: 2 */ return 2; case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ - return 1; /* TODO Should probably be upgraded to 2 */ + return 3; case DMAR: return 1; case SLIT: /* ACPI 2.0 upto 6.3: 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b9ec3b0e1be4200417c95d5540606b776e1225 Gerrit-Change-Number: 43054 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 22

Change in coreboot[master]: acpi: Bump FADT Minor Version to 3
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42250 ) Change subject: acpi: Bump FADT Minor Version to 3 ...................................................................... acpi: Bump FADT Minor Version to 3 Change-Id: I3c7803bcab3a4054280e352fd154cc28bf62f723 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42250/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a4ea24b..15794f1 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1239,7 +1239,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; - fadt->FADT_MinorVersion = 0; + fadt->FADT_MinorVersion = 3; fadt->firmware_ctrl = (unsigned long) facs; fadt->x_firmware_ctl_l = (unsigned long)facs; -- To view, visit https://review.coreboot.org/c/coreboot/+/42250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c7803bcab3a4054280e352fd154cc28bf62f723 Gerrit-Change-Number: 42250 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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