coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

1 participants
2456 discussions

Change in coreboot[master]: CreateLindarvariant
by Julia Tsai (Code Review) 12 Aug '20

12 Aug '20

Julia Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44074 ) Change subject: CreateLindarvariant ...................................................................... CreateLindarvariant Signed-off-by: Julia Tsai <julia.tsai(a)lcfc.corp-partner.google.com> Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 --- A src/mainboard/google/volteer/variants/lindar/include/variant/ec.h A src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h A src/mainboard/google/volteer/variants/lindar/overridetree.cb 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44074/1 diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/44074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 Gerrit-Change-Number: 44074 Gerrit-PatchSet: 1 Gerrit-Owner: Julia Tsai <julia.tsai(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: soc/intel/common/block/sata: Add common sata driver
by Subrata Banik (Code Review) 12 Aug '20

12 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44299 ) Change subject: soc/intel/common/block/sata: Add common sata driver ...................................................................... soc/intel/common/block/sata: Add common sata driver Enable PCI_COMMAND_MASTER for SATA controller. BUG=b:154900210 TEST=Able to build and boot CML and TGL platform. Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/sata/Kconfig A src/soc/intel/common/block/sata/Makefile.inc A src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/pch/Kconfig 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/44299/1 diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig new file mode 100644 index 0000000..6b24f59 --- /dev/null +++ b/src/soc/intel/common/block/sata/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_SATA + bool + help + Intel Processor common SATA support diff --git a/src/soc/intel/common/block/sata/Makefile.inc b/src/soc/intel/common/block/sata/Makefile.inc new file mode 100644 index 0000000..623d151 --- /dev/null +++ b/src/soc/intel/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c new file mode 100644 index 0000000..5a93ece --- /dev/null +++ b/src/soc/intel/common/block/sata/sata.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void sata_final(struct device *dev) +{ + /* Set Bus Master */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_U_SATA, + PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST, + PCI_DEVICE_ID_INTEL_CNL_SATA, + PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_CNP_H_SATA, + PCI_DEVICE_ID_INTEL_CNP_LP_SATA, + PCI_DEVICE_ID_INTEL_ICP_U_SATA, + PCI_DEVICE_ID_INTEL_CMP_SATA, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_SATA, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA_1, + PCI_DEVICE_ID_INTEL_JSP_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_1, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_3, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_4, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_5, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_6, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_1, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_3, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_4, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_5, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_6, + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 6e7f2f6..cca65d6 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -32,6 +32,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO -- To view, visit https://review.coreboot.org/c/coreboot/+/44299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c Gerrit-Change-Number: 44299 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mb/prodrive/hermes: Add multifunction device for UART2
by Christian Walter (Code Review) 12 Aug '20

12 Aug '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43481 ) Change subject: mb/prodrive/hermes: Add multifunction device for UART2 ...................................................................... mb/prodrive/hermes: Add multifunction device for UART2 Multifunction device at 19.0 needs to be enabled such that 19.2 gets scanned. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43481/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 6c6fe2d..48ab0fe 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -177,7 +177,8 @@ device pci 14.3 on end # CNVi wifi end - device pci 19.2 on end # UART #2 + device pci 19.0 hidden end + device pci 19.2 on end # UART #2 device pci 1b.4 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" -- To view, visit https://review.coreboot.org/c/coreboot/+/43481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Gerrit-Change-Number: 43481 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/tigerlake: Add IRQs for LPSS uart
by Patrick Rudolph (Code Review) 12 Aug '20

12 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44260 ) Change subject: soc/intel/tigerlake: Add IRQs for LPSS uart ...................................................................... soc/intel/tigerlake: Add IRQs for LPSS uart Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "APCI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/tigerlake/include/soc/irq.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44260/1 diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index ad70290..f95f9f6 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -9,4 +9,8 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 + #endif /* _SOC_IRQ_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Gerrit-Change-Number: 44260 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB
by Furquan Shaikh (Code Review) 12 Aug '20

12 Aug '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44362 ) Change subject: mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB ...................................................................... mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 30 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44362/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 90cd2d7..ff48517 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,37 +1,36 @@ -FLASH@0xFF000000 0x1000000 { - SI_BIOS@0x0 0x1000000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RW_MRC_CACHE@0x0 0x10000 - MRC_CACHE_HOLE@0x10000 0x11000 +FLASH@0xFF000000 16M { + SI_BIOS@0x0 16M { + # Size is mentioned in decimal instead of 64K because of the + # rules in picasso/Makefile.inc to calculate size of APOB NV. + # Once fmaptool is updated to provide this information, this + # can be changed to `RW_MRC_CACHE 64K` like other entries. + RW_MRC_CACHE@0 65536 + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 } - RW_SECTION_A@0x21000 0x39E000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x38DFC0 - RW_FWID_A@0x39DFC0 0x40 + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 } - RW_SECTION_B@0x3BF000 0x39E000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x38DFC0 - RW_FWID_B@0x39DFC0 0x40 + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_ELOG(PRESERVE)@0x75D000 0x4000 - RW_SHARED@0x761000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x765000 0x2000 - RW_NVRAM(PRESERVE)@0x767000 0x5000 - RW_UNUSED@0x76C000 0x14000 - SMMSTORE(PRESERVE)@0x780000 0x20000 - RW_LEGACY(CBFS)@0x7A0000 0x460000 - WP_RO@0xC00000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3FC000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7C0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x38B000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Gerrit-Change-Number: 44362 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/zork/var: Add gpio change support to v3.61
by Lucas Chen (Code Review) 12 Aug '20

12 Aug '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43995 ) Change subject: mb/google/zork/var: Add gpio change support to v3.61 ...................................................................... mb/google/zork/var: Add gpio change support to v3.61 Add gpio change support to schematic v3.61 for trembyle variants. gpio90 EN_PWR_TOUCHSCREEN gpio29 HP_INT_ODL_R gpio89 NC BUG=b:161447996, b:162021274 TEST:none Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I74e0fd9139463961bb3fa99dc94684c147965f60 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/ezkinil/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c M src/mainboard/google/zork/variants/trembyle/gpio.c 5 files changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43995/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index c10c9f4..796840e 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -65,8 +65,8 @@ /* PCIE_RST1_L (unused) */ PAD_NC(GPIO_27), /* GPIO_28: Not available */ - /* GPIO_29: unused */ - PAD_NC(GPIO_29), + /* GPIO_29: HP_INT_ODL_R */ + PAD_GPI(GPIO_29, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ @@ -109,10 +109,10 @@ PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* EN_DEV_BEEP_L */ - PAD_GPO(GPIO_89, HIGH), - /* Testpoint */ - PAD_NC(GPIO_90), + /* GPIO89: NC */ + PAD_NC(GPIO_89), + /* GPIO90: EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, HIGH), /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), /* CLK_REQ0_L - WIFI */ diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index 08b1c4d..d1088d6 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -22,6 +22,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 053c3c8..0f161e4 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -22,6 +22,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { @@ -37,6 +39,11 @@ PAD_NC(GPIO_69), /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ PAD_NC(GPIO_86), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* Testpoint */ + PAD_NC(GPIO_90), + }; static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 074fe00..d2e54e0 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -24,6 +24,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = { @@ -41,6 +43,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index d8367e7..c2ad2f9 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -24,6 +24,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = { @@ -41,6 +43,8 @@ PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/43995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74e0fd9139463961bb3fa99dc94684c147965f60 Gerrit-Change-Number: 43995 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/kukui: revise per-device memory mapping table
by Hung-Te Lin (Code Review) 12 Aug '20

12 Aug '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43987 ) Change subject: mb/google/kukui: revise per-device memory mapping table ...................................................................... mb/google/kukui: revise per-device memory mapping table In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/boardid.c M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc 3 files changed, 36 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43987/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index c6865d1..2cd5648 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -110,7 +110,12 @@ { static uint32_t cached_ram_code = BOARD_ID_INIT; - if (cached_ram_code == BOARD_ID_INIT) + if (cached_ram_code == BOARD_ID_INIT) { cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + /* Model-specific offset - see sdram_configs.c for details. */ + if (CONFIG(BOARD_GOOGLE_BURNET) || + CONFIG(BOARD_GOOGLE_ESCHE)) + cached_ram_code += 0x10; + } return cached_ram_code; } diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 7638853..8f3968e 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -5,23 +5,28 @@ #include <console/console.h> #include <soc/emi.h> +/* + * The RAM_CODE ADC on Kukui can support only 12 different levels. Each model + * can create its own mapping if needed, with an offset (0x10, 0x20, ...) + * applied in ram_code(). + */ static const char *const sdram_configs[] = { -#if CONFIG(BOARD_GOOGLE_BURNET) - [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", - [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", - [3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", - [4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", -#else /* The default unified table */ - [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", - [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", - [3] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", - [4] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", - [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", - [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", - [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", - [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", - [10] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", -#endif + /* Standard table. */ + [0x01] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x02] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x03] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", + [0x04] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [0x05] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [0x06] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [0x07] = "sdram-lpddr4x-SDADA4CR-128G-4GB", + [0x08] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + + /* Table shared by Burnet and its variants, offset = 0x10 */ + [0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 2b43519..4d4784a 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,20 +1,13 @@ sdram-params := -ifeq ($(CONFIG_BOARD_GOOGLE_BURNET),y) - sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB - sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB - sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB - sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB -else - sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB - sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB - sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB - sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB - sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB - sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB - sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB - sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB - sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB -endif +sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB +sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB +sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB +sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB +sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/43987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Gerrit-Change-Number: 43987 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/mediatek/mt8192: Add PLL and clock init support
by CK HU (Code Review) 12 Aug '20

12 Aug '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43958 to review the following change. Change subject: soc/mediatek/mt8192: Add PLL and clock init support ...................................................................... soc/mediatek/mt8192: Add PLL and clock init support Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/common/pll.c A src/soc/mediatek/mt8192/include/soc/infracfg.h A src/soc/mediatek/mt8192/include/soc/mcucfg.h A src/soc/mediatek/mt8192/include/soc/pll.h A src/soc/mediatek/mt8192/pll.c 6 files changed, 2,235 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/43958/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 681b97c..a1bd96d 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -20,6 +20,8 @@ struct mux { void *reg; + void *set_reg; + void *clr_reg; void *upd_reg; u8 mux_shift; u8 mux_width; diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 35b03d8..539d82c 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -12,9 +12,15 @@ u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); + if (mux->set_reg && mux->clr_reg) { + write32(mux->clr_reg, mask << mux->mux_shift); + write32(mux->set_reg, sel << mux->mux_shift); + } else { + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + } + if (mux->upd_reg) write32(mux->upd_reg, 1 << mux->upd_shift); } diff --git a/src/soc/mediatek/mt8192/include/soc/infracfg.h b/src/soc/mediatek/mt8192/include/soc/infracfg.h new file mode 100755 index 0000000..032e6cd --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/infracfg.h @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_INFRACFG_H +#define SOC_MEDIATEK_MT8192_INFRACFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_infracfg_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; /* 0x0050 */ + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; /* 0x0070 */ + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; /* 0x00b4 */ + u32 reserved4[2]; + u32 module_sw_cg_3_set; /* 0x00c0 */ + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[5]; + u32 module_sw_cg_4_set; /* 0x00e0 */ + u32 module_sw_cg_4_clr; + u32 module_sw_cg_4_sta; + u32 reserved6[5]; + u32 i2c_dbtool_misc; /* 0x0100 */ + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved7[5]; + u32 infra_globalcon_rst0_set; /* 0x0120 */ + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst1_set; /* 0x0130 */ + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst2_set; /* 0x0140 */ + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved10[1]; + u32 infra_globalcon_rst3_set; /* 0x0150 */ + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved11[41]; + u32 infra_topaxi_si0_ctl; /* 0x0200 */ + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 reserved12[1]; + u32 infra_apb_async_sta; /* 0x0230 */ + u32 infra_topaxi_si2_ctl; + u32 infra_topaxi_fmem_mdhw_ctrl; + u32 infra_conn_gals_ctl; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved13[1]; + u32 infra_topaxi_aslice_ctrl; /* 0x0260 */ + u32 infra_topaxi_aslice_ctrl_1; + u32 infra_topaxi_aslice_ctrl_2; + u32 infra_topaxi_aslice_ctrl_3; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 infra_ssusb_dev; + u32 reserved14[1]; + u32 infra_topaxi_emi_gmc_l2c_ctrl; /* 0x0288 */ + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_cbip_slice_ctrl_2; + u32 reserved15[1]; + u32 infra_topaxi_aslice_ctrl_4; /* 0x02b8 */ + u32 reserved16[1]; + u32 infra_topaxi_protecten_mcu; /* 0x02c0 */ + u32 infra_topaxi_protecten_mcu_set; + u32 infra_topaxi_protecten_mcu_clr; + u32 reserved17[1]; + u32 infra_topaxi_protecten_mm; /* 0x02d0 */ + u32 infra_topaxi_protecten_mm_set; + u32 infra_topaxi_protecten_mm_clr; + u32 reserved18[1]; + u32 infra_topaxi_protecten_mcu_sta0; /* 0x02e0 */ + u32 infra_topaxi_protecten_mcu_sta1; + u32 infra_topaxi_protecten_mm_sta0; + u32 infra_topaxi_protecten_mm_sta1; + u32 reserved19[1]; + u32 infra_apu_master_m0_gals_ctl; /* 0x02f4 */ + u32 infra_apu_master_m1_gals_ctl; + u32 infra_topaxi_bus_dbg_con_ao; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved20[4]; + u32 md2_bank4_map0; /* 0x0350 */ + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved21[1]; + u32 ap2md_dummy; /* 0x0370 */ + u32 reserved22[3]; + u32 conn_map0; /* 0x0380 */ + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 conn_map2; + u32 conn_map3; + u32 conn_map4; + u32 module_clk_sel_set; + u32 module_clk_sel_clr; + u32 pmicw_clock_ctrl_set; + u32 pmicw_clock_ctrl_clr; + u32 dramc_wbr_set; + u32 dramc_wbr_clr; + u32 topaxi_si0_ctl_set; + u32 topaxi_si0_ctl_clr; + u32 topaxi_si1_ctl_set; + u32 topaxi_si1_ctl_clr; + u32 reserved23[14]; + u32 peri_cci_sideband_con; /* 0x0400 */ + u32 mfg_cci_sideband_con; + u32 reserved24[2]; + u32 infra_pwm_cksw_ctrl; /* 0x0410 */ + u32 reserved25[59]; + u32 infra_ao_dbg_con0; /* 0x0500 */ + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 infra_ao_dbg_sta; + u32 reserved26[58]; + u32 mfg_misc_con; /* 0x0600 */ + u32 reserved27[63]; + u32 infra_rsvd0; /* 0x0700 */ + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_set_2; + u32 infra_topaxi_protecten_clr_2; + u32 reserved28[1]; + u32 infra_topaxi_protecten_sta0_2; /* 0x0720 */ + u32 infra_topaxi_protecten_sta1_2; + u32 reserved29[2]; + u32 infra_globalcon_rst4_set; /* 0x0730 */ + u32 infra_globalcon_rst4_clr; + u32 infra_globalcon_rst4_sta; + u32 infra_ao_sec_rst_con4; + u32 reserved30[16]; + u32 mcu2emi_m0_parity; /* 0x0780 */ + u32 mcu2emi_m0_parity_dbg_aw_1; + u32 mcu2emi_m0_parity_dbg_aw_2; + u32 mcu2emi_m0_parity_dbg_ar_1; + u32 mcu2emi_m0_parity_dbg_ar_2; + u32 mcu2emi_m1_parity; + u32 mcu2emi_m1_parity_dbg_aw_1; + u32 mcu2emi_m1_parity_dbg_aw_2; + u32 mcu2emi_m1_parity_dbg_ar_1; + u32 mcu2emi_m1_parity_dbg_ar_2; + u32 mcu2ifr_reg_parity; + u32 mcu2ifr_reg_parity_dbg_aw_1; + u32 mcu2ifr_reg_parity_dbg_aw_2; + u32 mcu2ifr_reg_parity_dbg_ar_1; + u32 mcu2ifr_reg_parity_dbg_ar_2; + u32 ifr_l3c2mcu_parity; + u32 ifr_l3c2mcu_parity_dbg_r_1; + u32 reserved31[47]; + u32 md1_sbc_key0; /* 0x0880 */ + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved32[1]; + u32 md1_misc_lock; /* 0x08a8 */ + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved33[11]; + u32 infra_bonding; /* 0x0900 */ + u32 reserved34[63]; + u32 infra_ao_scpsys_apb_async_sta; /* 0x0a00 */ + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_mcu2apu_asl0_ctl; + u32 infra_mcu2reg_asl0_ctl; + u32 infra_mcu_decoder_infra_ctl; + u32 infra_mcu_decoder_sta0; + u32 infra_mcu_decoder_sta1; + u32 infra_idle_async_bit_en_0; + u32 infra_apu_slave_gals_ctrl; + u32 infra_aximem_idle_bit_en_0; + u32 infra_mcu_path_sync_ctl; + u32 infra_conn2ap_int_mask; + u32 infra_mcu_pwr_ctl_mask; + u32 infra_md_rsv; + u32 reserved35[7]; + u32 infra_mem_26m_cksel; /* 0x0a60 */ + u32 reserved36[39]; + u32 pll_ulposc_con0; /* 0x0b00 */ + u32 pll_ulposc_con1; + u32 reserved37[2]; + u32 pll_auxadc_con0; /* 0x0b10 */ + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 reserved38[24]; + u32 infra_topaxi_protecten_vdnr; /* 0x0b80 */ + u32 infra_topaxi_protecten_vdnr_set; + u32 infra_topaxi_protecten_vdnr_clr; + u32 infra_topaxi_protecten_vdnr_sta0; + u32 infra_topaxi_protecten_vdnr_sta1; + u32 reserved39[3]; + u32 infra_topaxi_protecten_vdnr_1; /* 0x0ba0 */ + u32 infra_topaxi_protecten_vdnr_set_1; + u32 infra_topaxi_protecten_vdnr_clr_1; + u32 infra_topaxi_protecten_vdnr_sta0_1; + u32 infra_topaxi_protecten_vdnr_sta1_1; + u32 reserved40[19]; + u32 cldma_ctrl; /* 0x0c00 */ + u32 reserved41[63]; + u32 infrabus_dbg0; /* 0x0d00 */ + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 infrabus_dbg17; + u32 infrabus_dbg18; + u32 infrabus_dbg19; + u32 infrabus_dbg20; + u32 infrabus_dbg21; + u32 infrabus_dbg22; + u32 infrabus_dbg23; + u32 infrabus_dbg24; + u32 infrabus_dbg25; + u32 infrabus_dbg26; + u32 infrabus_dbg27; + u32 infrabus_dbg28; + u32 infrabus_dbg29; + u32 infrabus_dbg30; + u32 infrabus_dbg31; + u32 infrabus_dbg32; + u32 infrabus_dbg33; + u32 infrabus_dbg34; + u32 infrabus_dbg35; + u32 infrabus_dbg36; + u32 infrabus_dbg37; + u32 infrabus_dbg38; + u32 infrabus_dbg39; + u32 infrabus_dbg40; + u32 infrabus_dbg41; + u32 infrabus_dbg42; + u32 infrabus_dbg43; + u32 infrabus_dbg44; + u32 infrabus_dbg45; + u32 reserved42[4]; + u32 infra_topaxi_protecten_mm_2; /* 0x0dc8 */ + u32 infra_topaxi_protecten_mm_set_2; + u32 infra_topaxi_protecten_mm_clr_2; + u32 infra_topaxi_protecten_mm_sta0_2; + u32 infra_topaxi_protecten_mm_sta1_2; + u32 reserved43[5]; + u32 infrabus_dbg_mask2; /* 0x0df0 */ + u32 reserved44[19]; + u32 infra_ao_sec_mm0; /* 0x0e40 */ + u32 infra_ao_sec_mm1; + u32 infra_ao_sec_mm2; + u32 infra_ao_sec_mm3; + u32 infra_ao_sec_mm4; + u32 infra_ao_sec_mm5; + u32 infra_ao_sec_mm6; + u32 infra_ao_sec_mm7; + u32 infra_ao_sec_mm8; + u32 infra_ao_sec_mm9; + u32 infra_ao_sec_mm10; + u32 infra_ao_sec_mm11; + u32 infra_ao_sec_mm12; + u32 infra_ao_sec_mm13; + u32 infra_ao_sec_mm14; + u32 infra_ao_sec_mm15; + u32 infra_ao_sec_mm16; + u32 reserved45[5]; + u32 infra_ao_mm_hang_free; /* 0x0e98 */ + u32 infra_ao_module_hang_free; + u32 reserved46[24]; + u32 infra_misc; /* 0x0f00 */ + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved47[27]; + u32 infra_ao_sec_con; /* 0x0f80 */ + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 reserved48[1]; + u32 infra_ao_sec_cg_con2; /* 0x0f9c */ + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved49[2]; + u32 infra_ao_sec_hyp; /* 0x0fb0 */ + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8192_infracfg_regs, infra_globalcon_dcmctl, 0x0050); +check_member(mt8192_infracfg_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mt8192_infracfg_regs, module_sw_cg_3_set, 0x00c0); +check_member(mt8192_infracfg_regs, module_sw_cg_4_set, 0x00e0); +check_member(mt8192_infracfg_regs, i2c_dbtool_misc, 0x0100); +check_member(mt8192_infracfg_regs, infra_globalcon_rst0_set, 0x0120); +check_member(mt8192_infracfg_regs, infra_topaxi_si0_ctl, 0x0200); +check_member(mt8192_infracfg_regs, md2_bank4_map0, 0x0350); +check_member(mt8192_infracfg_regs, conn_map0, 0x0380); +check_member(mt8192_infracfg_regs, peri_cci_sideband_con, 0x0400); +check_member(mt8192_infracfg_regs, infra_pwm_cksw_ctrl, 0x0410); +check_member(mt8192_infracfg_regs, infra_ao_dbg_con0, 0x0500); +check_member(mt8192_infracfg_regs, mfg_misc_con, 0x0600); +check_member(mt8192_infracfg_regs, infra_rsvd0, 0x0700); +check_member(mt8192_infracfg_regs, infra_globalcon_rst4_set, 0x0730); +check_member(mt8192_infracfg_regs, mcu2emi_m0_parity, 0x0780); +check_member(mt8192_infracfg_regs, md1_sbc_key0, 0x0880); +check_member(mt8192_infracfg_regs, infra_bonding, 0x0900); +check_member(mt8192_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00); +check_member(mt8192_infracfg_regs, infra_mem_26m_cksel, 0x0a60); +check_member(mt8192_infracfg_regs, pll_ulposc_con0, 0x0b00); +check_member(mt8192_infracfg_regs, pll_auxadc_con0, 0x0b10); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr, 0x0b80); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0); +check_member(mt8192_infracfg_regs, cldma_ctrl, 0x0c00); +check_member(mt8192_infracfg_regs, infrabus_dbg0, 0x0d00); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_mm_2, 0x0dc8); +check_member(mt8192_infracfg_regs, infrabus_dbg_mask2, 0x0df0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mm0, 0x0e40); +check_member(mt8192_infracfg_regs, infra_ao_mm_hang_free, 0x0e98); +check_member(mt8192_infracfg_regs, infra_misc, 0x0f00); +check_member(mt8192_infracfg_regs, infra_ao_sec_con, 0x0f80); +check_member(mt8192_infracfg_regs, infra_ao_sec_hyp, 0x0fb0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mfg_hyp, 0x0fb4); + +static struct mt8192_infracfg_regs *const mt8192_infracfg = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8192_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h new file mode 100755 index 0000000..1d270ec --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h @@ -0,0 +1,1038 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUCFG_H +#define SOC_MEDIATEK_MT8192_MCUCFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_mcucfg_regs { + u32 reserved1[2]; + u32 mbista_mcsi_sf1_con; /* 0x0008 */ + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved2[2]; + u32 mbist_trigger_mux_ctl; /* 0x0030 */ + u32 reserved3[3]; + u32 dfd_ctrl; /* 0x0040 */ + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 reserved4[5]; + u32 mp_top_dbg_mon_sel; /* 0x0060 */ + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u32 reserved5[28]; + u32 mp0_ptp_sensor_sel; /* 0x00e0 */ + u32 reserved6[5]; + u32 armpll_jit_clk_out_sel; /* 0x00f8 */ + u32 reserved7[1]; + u32 cci_tra_cfg0; /* 0x0100 */ + u32 reserved8[4]; + u32 cci_tra_cfg5; /* 0x0114 */ + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u32 reserved9[51]; + u32 cci_m0_tra; /* 0x0200 */ + u32 cci_m1_tra; + u32 cci_m2_tra; + u32 reserved10[5]; + u32 cci_s1_tra; /* 0x0220 */ + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u32 reserved11[4]; + u32 cci_m0_tra_latch; /* 0x0240 */ + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u32 reserved12[5]; + u32 cci_s1_tra_latch; /* 0x0260 */ + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u32 reserved13[20]; + u32 cci_m0_if; /* 0x02c0 */ + u32 cci_m1_if; + u32 cci_m2_if; + u32 reserved14[5]; + u32 cci_s1_if; /* 0x02e0 */ + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u32 reserved15[12]; + u32 cci_m0_if_latch; /* 0x0320 */ + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u32 reserved16[5]; + u32 cci_s1_if_latch; /* 0x0340 */ + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u32 reserved17[44]; + u32 l3c_share_status0; /* 0x0400 */ + u32 l3c_share_status1; + u32 l3c_share_status2; + u32 reserved18[1]; + u32 mp0_cpu0_dc_age; /* 0x0410 */ + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u32 reserved19[52]; + u32 mp0_cpu0_nonwfx_ctrl; /* 0x0500 */ + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u32 reserved20[48]; + u32 mp0_ses_apb_trig; /* 0x0600 */ + u32 mp0_ses_clk_en; + u32 reserved21[2]; + u32 wfx_ret_met_dbc_sel; /* 0x0610 */ + u32 reserved22[3]; + u32 adb_bist_cfg1; /* 0x0620 */ + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 adb_bist_done1; + u32 reserved23[1]; + u32 adb_bist_pass1; /* 0x063c */ + u32 reserved24[48]; + u32 axi2acp_cfg_ctrl; /* 0x0700 */ + u32 axi2acp_cfg_mask_id; + u32 reserved25[2]; + u32 axi2acp_ar_def_set; /* 0x0710 */ + u32 reserved26[1]; + u32 axi2acp_aw_def_set; /* 0x0718 */ + u32 reserved27[1]; + u32 axi2acp_err_addr0; /* 0x0720 */ + u32 axi2acp_err_addr1; + u32 axi2acp_err_st; + u32 axi2acp_err_id; + u32 axi2acp_err_irq; + u32 axi2acp_err_dbgout; + u32 reserved28[50]; + u32 mst_ccim0_inject_fault; /* 0x0800 */ + u32 mst_ccim0_rec_par; + u32 mst_ccim0_log_rid; + u32 reserved29[1]; + u32 mst_ccim0_log_rd0; /* 0x0810 */ + u32 mst_ccim0_log_rd1; + u32 mst_ccim0_log_rd2; + u32 mst_ccim0_log_rd3; + u32 mst_ccim1_inject_fault; + u32 mst_ccim1_rec_par; + u32 mst_ccim1_log_rid; + u32 reserved30[1]; + u32 mst_ccim1_log_rd0; /* 0x0830 */ + u32 mst_ccim1_log_rd1; + u32 mst_ccim1_log_rd2; + u32 mst_ccim1_log_rd3; + u32 mst_intaxi_inject_fault; + u32 mst_intaxi_rec_par; + u32 mst_intaxi_log_rid; + u32 reserved31[1]; + u32 mst_intaxi_log_rd0; /* 0x0850 */ + u32 mst_intaxi_log_rd1; + u32 reserved32[2]; + u32 slv_1to2_inject_fault; /* 0x0860 */ + u32 slv_1to2_rec_par; + u32 slv_1to2_log_awid; + u32 slv_1to2_log_arid; + u32 slv_1to2_log_awa0; + u32 slv_1to2_log_awa1; + u32 slv_1to2_log_ara0; + u32 slv_1to2_log_ara1; + u32 slv_1to2_log_wid; + u32 reserved33[3]; + u32 slv_1to2_log_wd0; /* 0x0890 */ + u32 slv_1to2_log_wd1; + u32 slv_1to2_log_wd2; + u32 slv_1to2_log_wd3; + u32 slv_l3c_inject_fault; + u32 slv_l3c_rec_par; + u32 slv_l3c_log_awid; + u32 slv_l3c_log_arid; + u32 slv_l3c_log_awa0; + u32 slv_l3c_log_awa1; + u32 slv_l3c_log_ara0; + u32 slv_l3c_log_ara1; + u32 slv_l3c_log_wid; + u32 reserved34[1]; + u32 slv_l3c_log_wd0; /* 0x08c8 */ + u32 slv_l3c_log_wd1; + u32 slv_gic_inject_fault; + u32 slv_gic_rec_par; + u32 slv_gic_log_awid; + u32 slv_gic_log_arid; + u32 slv_gic_log_awa0; + u32 slv_gic_log_awa1; + u32 slv_gic_log_ara0; + u32 slv_gic_log_ara1; + u32 slv_gic_log_wid; + u32 reserved35[1]; + u32 slv_gic_log_wd0; /* 0x08f8 */ + u32 slv_gic_log_wd1; + u32 reserved36[64]; + u32 ildo_vin_big0; /* 0x0a00 */ + u32 ildo_out_big0; + u32 ildo_ovstck_big0; + u32 ildo_vo2hck_big0; + u32 ildo_mhstck_big0; + u32 ildo_mlstck_big0; + u32 ilod_uvwin_big0; + u32 ilod_ovwin_big0; + u32 ildo_pd_cfg_big0; + u32 reserved37[3]; + u32 ildo_vin_big1; /* 0x0a30 */ + u32 ildo_out_big1; + u32 ildo_ovstck_big1; + u32 ildo_vo2hck_big1; + u32 ildo_mhstck_big1; + u32 ildo_mlstck_big1; + u32 ilod_uvwin_big1; + u32 ilod_ovwin_big1; + u32 ildo_pd_cfg_big1; + u32 reserved38[3]; + u32 ildo_vin_big2; /* 0x0a60 */ + u32 ildo_out_big2; + u32 ildo_ovstck_big2; + u32 ildo_vo2hck_big2; + u32 ildo_mhstck_big2; + u32 ildo_mlstck_big2; + u32 ilod_uvwin_big2; + u32 ilod_ovwin_big2; + u32 ildo_pd_cfg_big2; + u32 reserved39[3]; + u32 ildo_vin_big3; /* 0x0a90 */ + u32 ildo_out_big3; + u32 ildo_ovstck_big3; + u32 ildo_vo2hck_big3; + u32 ildo_mhstck_big3; + u32 ildo_mlstck_big3; + u32 ilod_uvwin_big3; + u32 ilod_ovwin_big3; + u32 ildo_pd_cfg_big3; + u32 reserved40[1495]; + u32 l3c_share_cfg0; /* 0x2210 */ + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u32 reserved41[1]; + u32 udi_cfg0; /* 0x2220 */ + u32 udi_cfg1; + u32 reserved42[2]; + u32 mcusys_core_status; /* 0x2230 */ + u32 reserved43[1]; + u32 cfg_sys_valid; /* 0x2238 */ + u32 cfg_sysbase_addr_0; + u32 cfg_sysbase_addr_1; + u32 cfg_sysbase_addr_2; + u32 cfg_sysbase_addr_3; + u32 cfg_sysbase_addr_4; + u32 reserved44[4]; + u32 mcusys_base; /* 0x2260 */ + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 ext_l3c_sram_base; + u32 ext_gic_periph_base; + u32 mcusys_qos_shaper_degree; + u32 mcusys_qos_shaper_others; + u32 mcusys_qos_age_set_enable; + u32 sspm_cpueb_turbo_pll_ctl; + u32 cpu_eb_apb_base; + u32 cpu_eb_tcm_btb_delsel; + u32 cpu_eb_mem_misc; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u32 cpu_plldiv_cfg2; + u32 cpu_plldiv_cfg3; + u32 cpu_plldiv_cfg4; + u32 reserved45[11]; + u32 bus_plldiv_cfg; /* 0x22e0 */ + u32 reserved46[3]; + u32 plldiv_ctl0; /* 0x22f0 */ + u32 reserved47[3]; + u32 mcsi_ram_delsel0; /* 0x2300 */ + u32 mcsi_ram_delsel1; + u32 reserved48[30]; + u32 etb_cfg0; /* 0x2380 */ + u32 reserved49[3]; + u32 bus_parity_gen_en; /* 0x2390 */ + u32 bus_parity_clr; + u32 bus_parity_chk_en; + u32 bus_parity_fail; + u32 dsu2biu_addr_remap_cfg; + u32 dsu2biu_addr_remap_sta; + u32 reserved50[2]; + u32 dsu2biu_addr_remap_0_cfg0; /* 0x23b0 */ + u32 dsu2biu_addr_remap_0_cfg1; + u32 dsu2biu_addr_remap_0_cfg2; + u32 reserved51[1]; + u32 dsu2biu_addr_remap_1_cfg0; /* 0x23c0 */ + u32 dsu2biu_addr_remap_1_cfg1; + u32 dsu2biu_addr_remap_1_cfg2; + u32 reserved52[1]; + u32 dsu2biu_addr_remap_magic; /* 0x23d0 */ + u32 reserved53[11]; + u32 cci_rgu; /* 0x2400 */ + u32 reserved54[3]; + u32 mcsi_cfg0; /* 0x2410 */ + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u32 reserved55[7]; + u32 mcsic_dcm0; /* 0x2440 */ + u32 mcsic_dcm1; + u32 reserved56[18]; + u32 apmcu2emi_early_cke_ctl01; /* 0x2490 */ + u32 reserved57[1]; + u32 apmcu2emi_early_ebg_ctl0; /* 0x2498 */ + u32 apmcu2emi_early_ebg_ctl1; + u32 apmcu2emi_early_ebg_ctl2; + u32 apmcu2emi_early_ebg_ctl3; + u32 apmcu2emi_early_ebg_ctl4; + u32 apmcu2emi_early_ebg_ctl5; + u32 reserved58[20]; + u32 mp_adb_dcm_cfg0; /* 0x2500 */ + u32 reserved59[1]; + u32 mp_adb_dcm_cfg2; /* 0x2508 */ + u32 reserved60[1]; + u32 mp_adb_dcm_cfg4; /* 0x2510 */ + u32 reserved61[1]; + u32 mp_misc_dcm_cfg0; /* 0x2518 */ + u32 reserved62[9]; + u32 etb_ck_ctl; /* 0x2540 */ + u32 reserved63[15]; + u32 dcc_cpu_con0; /* 0x2580 */ + u32 dcc_cpu_con1; + u32 reserved64[6]; + u32 dcc_bus_con0; /* 0x25a0 */ + u32 reserved65[7]; + u32 mcusys_dcm_cfg0; /* 0x25c0 */ + u32 reserved66[79]; + u32 fcm_spmc_sw_cfg1; /* 0x2700 */ + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u32 reserved67[9]; + u32 mcusys_spmc_sw_cfg; /* 0x2740 */ + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u32 reserved68[45]; + u32 cpc_pllbuck_req_ctrl; /* 0x2800 */ + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u32 reserved69[1]; + u32 cpc_mcusys_last_core_resp; /* 0x2824 */ + u32 cpc_pwr_on_mask; + u32 reserved70[5]; + u32 cpc_spmc_pwr_status; /* 0x2840 */ + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u32 reserved71[1]; + u32 cpc_gp0_gp1_status; /* 0x2854 */ + u32 reserved72[1]; + u32 cpc_turbo_ctrl; /* 0x285c */ + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u32 reserved73[1]; + u32 cpc_turbo_gp0_resp; /* 0x2880 */ + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u32 reserved74[20]; + u32 emi_wfifo; /* 0x2900 */ + u32 axi1to4_cfg; + u32 apb_cfg; + u32 emi_adb_edge_sel; + u32 reserved75[4]; + u32 sclk_cfg_slow_down_ck; /* 0x2920 */ + u32 reserved76[3]; + u32 acpwakeup; /* 0x2930 */ + u32 reserved77[1]; + u32 l3gic_idle_bypass; /* 0x2938 */ + u32 reserved78[21]; + u32 mcusys_dbg_mon_sel; /* 0x2990 */ + u32 mcusys_dbg_mon; + u32 reserved79[58]; + u32 gic_acao_ctl0; /* 0x2a80 */ + u32 reserved80[1]; + u32 gic_acao_ctl2; /* 0x2a88 */ + u32 reserved81[29]; + u32 spmc_dbg_setting; /* 0x2b00 */ + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u32 reserved82[2]; + u32 trace_data_entry0_l; /* 0x2b20 */ + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u32 reserved83[1]; + u32 cluster_off_dormant_counter; /* 0x2b70 */ + u32 cluster_off_dormant_counter_clear; + u32 turbo_gp0_gp1_latency; + u32 turbo_gp2_latency; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u32 reserved84[4]; + u32 cpc_wdt_latch_info6; /* 0x2bb0 */ + u32 cpc_wdt_latch_info7; + u32 cpc_ptm_event_en_ctrl; + u32 cpc_ptm_event_en_ctrl1; + u32 cpc_ptm_trace_sel; + u32 cpc_ptm_trace_status_l; + u32 cpc_ptm_trace_status_h; + u32 reserved85[29]; + u32 sesv6_bg_ctrl; /* 0x2c40 */ + u32 reserved86[3]; + u32 dsu_sesv6_ao_reg0; /* 0x2c50 */ + u32 dsu_sesv6_ao_reg1; + u32 dsu_sesv6_ao_reg2; + u32 dsu_sesv6_ao_reg3; + u32 dsu_sesv6_ao_reg4; + u32 reserved87[39]; + u32 ildo_dout_sel; /* 0x2d00 */ + u32 reserved88[31]; + u32 dreq20_little_en; /* 0x2d80 */ + u32 reserved89[2]; + u32 dreq20_big_vproc_iso; /* 0x2d8c */ + u32 reserved90[28]; + u32 pikachu_event; /* 0x2e00 */ + u32 pikachu_status; + u32 reserved91[126]; + u32 cpu0_drcc_ao_config; /* 0x3000 */ + u32 reserved92[3]; + u32 cpu0_sesv6_ao_reg0; /* 0x3010 */ + u32 cpu0_sesv6_ao_reg1; + u32 cpu0_sesv6_ao_reg2; + u32 cpu0_sesv6_ao_reg3; + u32 cpu0_sesv6_ao_reg4; + u32 reserved93[7]; + u32 cpu0_dfs_cfg; /* 0x3040 */ + u32 reserved94[3]; + u32 cpu0_turbo_cfg; /* 0x3050 */ + u32 reserved95[105]; + u32 cpu0_resereved_reg; /* 0x31f8 */ + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u32 reserved96[3]; + u32 cpu1_sesv6_ao_reg0; /* 0x3210 */ + u32 cpu1_sesv6_ao_reg1; + u32 cpu1_sesv6_ao_reg2; + u32 cpu1_sesv6_ao_reg3; + u32 cpu1_sesv6_ao_reg4; + u32 reserved97[7]; + u32 cpu1_dfs_cfg; /* 0x3240 */ + u32 reserved98[3]; + u32 cpu1_turbo_cfg; /* 0x3250 */ + u32 reserved99[105]; + u32 cpu1_resereved_reg; /* 0x33f8 */ + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u32 reserved100[3]; + u32 cpu2_sesv6_ao_reg0; /* 0x3410 */ + u32 cpu2_sesv6_ao_reg1; + u32 cpu2_sesv6_ao_reg2; + u32 cpu2_sesv6_ao_reg3; + u32 cpu2_sesv6_ao_reg4; + u32 reserved101[7]; + u32 cpu2_dfs_cfg; /* 0x3440 */ + u32 reserved102[3]; + u32 cpu2_turbo_cfg; /* 0x3450 */ + u32 reserved103[105]; + u32 cpu2_resereved_reg; /* 0x35f8 */ + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u32 reserved104[3]; + u32 cpu3_sesv6_ao_reg0; /* 0x3610 */ + u32 cpu3_sesv6_ao_reg1; + u32 cpu3_sesv6_ao_reg2; + u32 cpu3_sesv6_ao_reg3; + u32 cpu3_sesv6_ao_reg4; + u32 reserved105[7]; + u32 cpu3_dfs_cfg; /* 0x3640 */ + u32 reserved106[3]; + u32 cpu3_turbo_cfg; /* 0x3650 */ + u32 reserved107[105]; + u32 cpu3_resereved_reg; /* 0x37f8 */ + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u32 reserved108[3]; + u32 cpu4_sesv6_ao_reg0; /* 0x3810 */ + u32 cpu4_sesv6_ao_reg1; + u32 cpu4_sesv6_ao_reg2; + u32 cpu4_sesv6_ao_reg3; + u32 cpu4_sesv6_ao_reg4; + u32 reserved109[3]; + u32 cpu4_didt_reg; /* 0x3830 */ + u32 cpu4_mem_lre_reg; + u32 reserved110[2]; + u32 cpu4_dfs_cfg; /* 0x3840 */ + u32 reserved111[3]; + u32 cpu4_turbo_cfg; /* 0x3850 */ + u32 reserved112[105]; + u32 cpu4_resereved_reg; /* 0x39f8 */ + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u32 reserved113[3]; + u32 cpu5_sesv6_ao_reg0; /* 0x3a10 */ + u32 cpu5_sesv6_ao_reg1; + u32 cpu5_sesv6_ao_reg2; + u32 cpu5_sesv6_ao_reg3; + u32 cpu5_sesv6_ao_reg4; + u32 reserved114[3]; + u32 cpu5_didt_reg; /* 0x3a30 */ + u32 cpu5_mem_lre_reg; + u32 reserved115[2]; + u32 cpu5_dfs_cfg; /* 0x3a40 */ + u32 reserved116[3]; + u32 cpu5_turbo_cfg; /* 0x3a50 */ + u32 reserved117[105]; + u32 cpu5_resereved_reg; /* 0x3bf8 */ + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u32 reserved118[3]; + u32 cpu6_sesv6_ao_reg0; /* 0x3c10 */ + u32 cpu6_sesv6_ao_reg1; + u32 cpu6_sesv6_ao_reg2; + u32 cpu6_sesv6_ao_reg3; + u32 cpu6_sesv6_ao_reg4; + u32 reserved119[3]; + u32 cpu6_didt_reg; /* 0x3c30 */ + u32 cpu6_mem_lre_reg; + u32 reserved120[2]; + u32 cpu6_dfs_cfg; /* 0x3c40 */ + u32 reserved121[3]; + u32 cpu6_turbo_cfg; /* 0x3c50 */ + u32 reserved122[105]; + u32 cpu6_resereved_reg; /* 0x3df8 */ + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u32 reserved123[3]; + u32 cpu7_sesv6_ao_reg0; /* 0x3e10 */ + u32 cpu7_sesv6_ao_reg1; + u32 cpu7_sesv6_ao_reg2; + u32 cpu7_sesv6_ao_reg3; + u32 cpu7_sesv6_ao_reg4; + u32 reserved124[3]; + u32 cpu7_didt_reg; /* 0x3e30 */ + u32 cpu7_mem_lre_reg; + u32 reserved125[2]; + u32 cpu7_dfs_cfg; /* 0x3e40 */ + u32 reserved126[3]; + u32 cpu7_turbo_cfg; /* 0x3e50 */ + u32 reserved127[105]; + u32 cpu7_resereved_reg; /* 0x3ff8 */ + u32 cpu7_resereved_reg_rd; + u32 reserved128[512]; + u32 mp0_mbist_cfg; /* 0x4800 */ + u32 reserved129[15]; + u32 mp0_l3_data_ram_delsel; /* 0x4840 */ + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u32 reserved130[12]; + u32 mp0_dcm_cfg0; /* 0x4880 */ + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u32 reserved131[7]; + u32 mp0_l3_cache_parity1; /* 0x48c0 */ + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u32 reserved132[1]; + u32 mp0_cluster_cfg0; /* 0x48d0 */ + u32 reserved133[3]; + u32 mp0_cluster_cfg4; /* 0x48e0 */ + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u32 reserved134[4]; + u32 mp0_cluster_cfg8; /* 0x4900 */ + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 mp0_mem_dreq_cfg; + u32 mp0_victim_rd_mask; + u32 reserved135[174]; + u32 cpu_type0_spmc0_cfg; /* 0x4c00 */ + u32 reserved136[7]; + u32 cpu_type0_ram_delsel0_cfg; /* 0x4c20 */ + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 reserved137[53]; + u32 cpu_type1_spmc0_cfg; /* 0x4d00 */ + u32 reserved138[3]; + u32 cpu_type1_mpmmen; /* 0x4d10 */ + u32 reserved139[3]; + u32 cpu_type1_ram_delsel0_cfg; /* 0x4d20 */ + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 reserved140[5]; + u32 cpu_type1_drss_cfg0; /* 0x4d40 */ + u32 cpu_type1_drss_cfg1; + u32 reserved141[302]; + u32 mcusys_pwr_con; /* 0x5200 */ + u32 mp0_cputop_pwr_con; + u32 mp0_cpu0_pwr_con; + u32 mp0_cpu1_pwr_con; + u32 mp0_cpu2_pwr_con; + u32 mp0_cpu3_pwr_con; + u32 mp0_cpu4_pwr_con; + u32 mp0_cpu5_pwr_con; + u32 mp0_cpu6_pwr_con; + u32 mp0_cpu7_pwr_con; + u32 reserved142[246]; + u32 sec_pol_ctl_en0; /* 0x5600 */ + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 reserved143[7]; + u32 int_pol_ctl0; /* 0x5668 */ + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 reserved144[7]; + u32 int_msk_ctl0; /* 0x56d0 */ + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 reserved145[10]; + u32 int_msk_ctl_all; /* 0x5744 */ + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u32 reserved146[572]; + u32 dfd_internal_ctl; /* 0x6040 */ + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_finish_wait_time; + u32 dfd_internal_chain_group; + u32 dfd_internal_chain_inv_info_ll; + u32 dfd_internal_chain_inv_info_lh; + u32 dfd_internal_chain_inv_info_hl; + u32 dfd_internal_chain_inv_info_hh; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 dfd_v35_enable; + u32 dfd_v35_tap_number; + u32 dfd_v35_tap_en; + u32 dfd_v35_ctl; + u32 dfd_v35_tap_seq0; + u32 dfd_v35_tap_seq1; + u32 dfd_v35_seq0_0; + u32 dfd_v35_seq0_1; + u32 dfd_v35_seq1_0; + u32 dfd_v35_seq1_1; + u32 dfd_v35_seq2_0; + u32 dfd_v35_seq2_1; + u32 reserved147[6]; + u32 dfd_soc_clock_stop_mask; /* 0x60f0 */ + u32 reserved148[2]; + u32 dfd_hw_trigger_mask; /* 0x60fc */ + u32 dfd_v50_enable; + u32 dfd_v50_self_trigger_iteration; + u32 dfd_v50_start_trigger; + u32 dfd_v50_cpuck_halt; + u32 dfd_v50_26m_resume; + u32 dfd_v50_26m_halt_release; + u32 dfd_v50_system_halt_time; + u32 dfd_v50_group_0_1_diff; + u32 dfd_v50_group_0_2_diff; + u32 dfd_v50_group_0_3_diff; + u32 dfd_v50_group_0_4_diff; + u32 dfd_v50_group_0_5_diff; + u32 dfd_v50_group_0_6_diff; + u32 dfd_v50_group_0_7_diff; + u32 dfd_v50_group_0_8_diff; + u32 dfd_v50_group_0_9_diff; + u32 dfd_v50_group_0_10_diff; + u32 dfd_v50_group_0_11_diff; + u32 dfd_v50_group_0_12_diff; + u32 dfd_v50_group_0_13_diff; + u32 dfd_v50_group_0_14_diff; + u32 dfd_v50_group_0_15_diff; + u32 dfd_v50_group_0_16_diff; + u32 dfd_v50_group_0_17_diff; + u32 dfd_v50_group_0_18_diff; + u32 dfd_v50_group_0_19_diff; + u32 dfd_v50_group_0_20_diff; + u32 dfd_v50_group_0_21_diff; + u32 dfd_v50_group_0_22_diff; + u32 dfd_v50_group_0_23_diff; + u32 dfd_v50_group_0_24_diff; + u32 dfd_v50_group_0_25_diff; + u32 dfd_v50_group_0_26_diff; + u32 dfd_v50_group_0_27_diff; + u32 dfd_v50_group_0_28_diff; + u32 dfd_v50_group_0_29_diff; + u32 dfd_v50_group_0_30_diff; + u32 dfd_v50_group_0_31_diff; + u32 dfd_v50_chain_group_3_0_info; + u32 dfd_v50_chain_group_7_4_info; + u32 dfd_v50_chain_group_11_8_info; + u32 dfd_v50_chain_group_15_12_info; + u32 dfd_v50_chain_group_19_16_info; + u32 dfd_v50_chain_group_23_20_info; + u32 dfd_v50_chain_group_27_24_info; + u32 dfd_v50_chain_group_31_28_info; + u32 dfd_v50_chain_group_35_32_info; + u32 dfd_v50_chain_group_39_36_info; + u32 dfd_v50_chain_group_43_40_info; + u32 dfd_v50_chain_group_47_44_info; + u32 dfd_v50_chain_group_51_48_info; + u32 dfd_v50_chain_group_55_52_info; + u32 dfd_v50_chain_group_59_56_info; + u32 dfd_v50_chain_group_63_60_info; + u32 dfd_v50_chain_group_67_64_info; + u32 dfd_v50_chain_group_71_68_info; + u32 dfd_v50_chain_group_75_72_info; + u32 dfd_v50_chain_group_79_76_info; + u32 dfd_v50_chain_group_83_80_info; + u32 dfd_v50_chain_group_87_84_info; + u32 dfd_v50_chain_group_91_88_info; + u32 dfd_v50_chain_group_95_92_info; + u32 dfd_v50_chain_group_99_96_info; + u32 dfd_v50_chain_group_103_100_info; + u32 dfd_v50_chain_group_107_104_info; + u32 dfd_v50_chain_group_111_108_info; + u32 dfd_v50_chain_group_115_112_info; + u32 dfd_v50_chain_group_119_116_info; + u32 dfd_v50_chain_group_123_120_info; + u32 dfd_v50_chain_group_127_124_info; + u32 dfd_test_si_2; + u32 dfd_test_si_3; + u32 dfd_test_so; + u32 dfd_bus_halt_time; + u32 dfd_read_addr; + u32 dfd_v50_clk_stop_time; + u32 dfd_v50_group_0_32_diff; + u32 dfd_v50_group_0_33_diff; + u32 dfd_v50_group_0_34_diff; + u32 dfd_v50_group_0_35_diff; + u32 dfd_v50_group_0_36_diff; + u32 dfd_v50_group_0_37_diff; + u32 dfd_v50_group_0_38_diff; + u32 dfd_v50_group_0_39_diff; + u32 dfd_v50_group_0_40_diff; + u32 dfd_v50_group_0_41_diff; + u32 dfd_v50_group_0_42_diff; + u32 dfd_v50_group_0_43_diff; + u32 dfd_v50_group_0_44_diff; + u32 dfd_v50_group_0_45_diff; + u32 dfd_v50_group_0_46_diff; + u32 dfd_v50_group_0_47_diff; + u32 dfd_v50_group_0_48_diff; + u32 dfd_v50_group_0_49_diff; + u32 dfd_v50_group_0_50_diff; + u32 dfd_v50_group_0_51_diff; + u32 dfd_v50_group_0_52_diff; + u32 dfd_v50_group_0_53_diff; + u32 dfd_v50_group_0_54_diff; + u32 dfd_v50_group_0_55_diff; + u32 dfd_v50_group_0_56_diff; + u32 dfd_v50_group_0_57_diff; + u32 dfd_v50_group_0_58_diff; + u32 dfd_v50_group_0_59_diff; + u32 dfd_v50_group_0_60_diff; + u32 dfd_v50_group_0_61_diff; + u32 dfd_v50_group_0_62_diff; + u32 dfd_v50_group_0_63_diff; + u32 reserved149[20]; + u32 dfd_v50_spare; /* 0x6300 */ + u32 reserved150[1843]; + u32 mcusys_reserved_reg4; /* 0x7fd0 */ + u32 mcusys_reserved_reg4_rd; + u32 reserved151[2]; + u32 mcusys_reserved_reg0; /* 0x7fe0 */ + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8192_mcucfg_regs, mbista_mcsi_sf1_con, 0x0008); +check_member(mt8192_mcucfg_regs, mbist_trigger_mux_ctl, 0x0030); +check_member(mt8192_mcucfg_regs, dfd_ctrl, 0x0040); +check_member(mt8192_mcucfg_regs, mp_top_dbg_mon_sel, 0x0060); +check_member(mt8192_mcucfg_regs, mp0_ptp_sensor_sel, 0x00e0); +check_member(mt8192_mcucfg_regs, armpll_jit_clk_out_sel, 0x00f8); +check_member(mt8192_mcucfg_regs, cci_tra_cfg5, 0x0114); +check_member(mt8192_mcucfg_regs, cci_m0_tra, 0x0200); +check_member(mt8192_mcucfg_regs, cci_s1_tra, 0x0220); +check_member(mt8192_mcucfg_regs, cci_m0_tra_latch, 0x0240); +check_member(mt8192_mcucfg_regs, cci_s1_tra_latch, 0x0260); +check_member(mt8192_mcucfg_regs, cci_m0_if, 0x02c0); +check_member(mt8192_mcucfg_regs, cci_s1_if, 0x02e0); +check_member(mt8192_mcucfg_regs, cci_m0_if_latch, 0x0320); +check_member(mt8192_mcucfg_regs, cci_s1_if_latch, 0x0340); +check_member(mt8192_mcucfg_regs, l3c_share_status0, 0x0400); +check_member(mt8192_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x0500); +check_member(mt8192_mcucfg_regs, mp0_ses_apb_trig, 0x0600); +check_member(mt8192_mcucfg_regs, wfx_ret_met_dbc_sel, 0x0610); +check_member(mt8192_mcucfg_regs, adb_bist_cfg1, 0x0620); +check_member(mt8192_mcucfg_regs, axi2acp_cfg_ctrl, 0x0700); +check_member(mt8192_mcucfg_regs, axi2acp_ar_def_set, 0x0710); +check_member(mt8192_mcucfg_regs, mst_ccim0_inject_fault, 0x0800); +check_member(mt8192_mcucfg_regs, slv_1to2_inject_fault, 0x0860); +check_member(mt8192_mcucfg_regs, slv_1to2_log_wd0, 0x0890); +check_member(mt8192_mcucfg_regs, ildo_vin_big0, 0x0a00); +check_member(mt8192_mcucfg_regs, ildo_vin_big1, 0x0a30); +check_member(mt8192_mcucfg_regs, ildo_vin_big2, 0x0a60); +check_member(mt8192_mcucfg_regs, ildo_vin_big3, 0x0a90); +check_member(mt8192_mcucfg_regs, l3c_share_cfg0, 0x2210); +check_member(mt8192_mcucfg_regs, mcusys_core_status, 0x2230); +check_member(mt8192_mcucfg_regs, mcusys_base, 0x2260); +check_member(mt8192_mcucfg_regs, bus_plldiv_cfg, 0x22e0); +check_member(mt8192_mcucfg_regs, plldiv_ctl0, 0x22f0); +check_member(mt8192_mcucfg_regs, mcsi_ram_delsel0, 0x2300); +check_member(mt8192_mcucfg_regs, etb_cfg0, 0x2380); +check_member(mt8192_mcucfg_regs, bus_parity_gen_en, 0x2390); +check_member(mt8192_mcucfg_regs, dsu2biu_addr_remap_0_cfg0, 0x23b0); +check_member(mt8192_mcucfg_regs, cci_rgu, 0x2400); +check_member(mt8192_mcucfg_regs, mcsi_cfg0, 0x2410); +check_member(mt8192_mcucfg_regs, mcsic_dcm0, 0x2440); +check_member(mt8192_mcucfg_regs, apmcu2emi_early_cke_ctl01, 0x2490); +check_member(mt8192_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500); +check_member(mt8192_mcucfg_regs, etb_ck_ctl, 0x2540); +check_member(mt8192_mcucfg_regs, dcc_cpu_con0, 0x2580); +check_member(mt8192_mcucfg_regs, dcc_bus_con0, 0x25a0); +check_member(mt8192_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0); +check_member(mt8192_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700); +check_member(mt8192_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740); +check_member(mt8192_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800); +check_member(mt8192_mcucfg_regs, cpc_spmc_pwr_status, 0x2840); +check_member(mt8192_mcucfg_regs, emi_wfifo, 0x2900); +check_member(mt8192_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920); +check_member(mt8192_mcucfg_regs, acpwakeup, 0x2930); +check_member(mt8192_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990); +check_member(mt8192_mcucfg_regs, gic_acao_ctl0, 0x2a80); +check_member(mt8192_mcucfg_regs, spmc_dbg_setting, 0x2b00); +check_member(mt8192_mcucfg_regs, trace_data_entry0_l, 0x2b20); +check_member(mt8192_mcucfg_regs, cpc_wdt_latch_info6, 0x2bb0); +check_member(mt8192_mcucfg_regs, sesv6_bg_ctrl, 0x2c40); +check_member(mt8192_mcucfg_regs, dsu_sesv6_ao_reg0, 0x2c50); +check_member(mt8192_mcucfg_regs, ildo_dout_sel, 0x2d00); +check_member(mt8192_mcucfg_regs, dreq20_little_en, 0x2d80); +check_member(mt8192_mcucfg_regs, dreq20_big_vproc_iso, 0x2d8c); +check_member(mt8192_mcucfg_regs, pikachu_event, 0x2e00); +check_member(mt8192_mcucfg_regs, cpu0_drcc_ao_config, 0x3000); +check_member(mt8192_mcucfg_regs, cpu0_sesv6_ao_reg0, 0x3010); +check_member(mt8192_mcucfg_regs, cpu0_dfs_cfg, 0x3040); +check_member(mt8192_mcucfg_regs, cpu0_turbo_cfg, 0x3050); +check_member(mt8192_mcucfg_regs, cpu0_resereved_reg, 0x31f8); +check_member(mt8192_mcucfg_regs, cpu1_sesv6_ao_reg0, 0x3210); +check_member(mt8192_mcucfg_regs, cpu1_dfs_cfg, 0x3240); +check_member(mt8192_mcucfg_regs, cpu1_turbo_cfg, 0x3250); +check_member(mt8192_mcucfg_regs, cpu1_resereved_reg, 0x33f8); +check_member(mt8192_mcucfg_regs, cpu2_sesv6_ao_reg0, 0x3410); +check_member(mt8192_mcucfg_regs, cpu2_dfs_cfg, 0x3440); +check_member(mt8192_mcucfg_regs, cpu2_turbo_cfg, 0x3450); +check_member(mt8192_mcucfg_regs, cpu2_resereved_reg, 0x35f8); +check_member(mt8192_mcucfg_regs, cpu3_sesv6_ao_reg0, 0x3610); +check_member(mt8192_mcucfg_regs, cpu3_dfs_cfg, 0x3640); +check_member(mt8192_mcucfg_regs, cpu3_turbo_cfg, 0x3650); +check_member(mt8192_mcucfg_regs, cpu3_resereved_reg, 0x37f8); +check_member(mt8192_mcucfg_regs, cpu4_sesv6_ao_reg0, 0x3810); +check_member(mt8192_mcucfg_regs, cpu4_didt_reg, 0x3830); +check_member(mt8192_mcucfg_regs, cpu4_dfs_cfg, 0x3840); +check_member(mt8192_mcucfg_regs, cpu4_turbo_cfg, 0x3850); +check_member(mt8192_mcucfg_regs, cpu4_resereved_reg, 0x39f8); +check_member(mt8192_mcucfg_regs, cpu5_sesv6_ao_reg0, 0x3a10); +check_member(mt8192_mcucfg_regs, cpu5_didt_reg, 0x3a30); +check_member(mt8192_mcucfg_regs, cpu5_dfs_cfg, 0x3a40); +check_member(mt8192_mcucfg_regs, cpu5_turbo_cfg, 0x3a50); +check_member(mt8192_mcucfg_regs, cpu5_resereved_reg, 0x3bf8); +check_member(mt8192_mcucfg_regs, cpu6_sesv6_ao_reg0, 0x3c10); +check_member(mt8192_mcucfg_regs, cpu6_didt_reg, 0x3c30); +check_member(mt8192_mcucfg_regs, cpu6_dfs_cfg, 0x3c40); +check_member(mt8192_mcucfg_regs, cpu6_turbo_cfg, 0x3c50); +check_member(mt8192_mcucfg_regs, cpu6_resereved_reg, 0x3df8); +check_member(mt8192_mcucfg_regs, cpu7_sesv6_ao_reg0, 0x3e10); +check_member(mt8192_mcucfg_regs, cpu7_didt_reg, 0x3e30); +check_member(mt8192_mcucfg_regs, cpu7_dfs_cfg, 0x3e40); +check_member(mt8192_mcucfg_regs, cpu7_turbo_cfg, 0x3e50); +check_member(mt8192_mcucfg_regs, cpu7_resereved_reg, 0x3ff8); +check_member(mt8192_mcucfg_regs, mp0_mbist_cfg, 0x4800); +check_member(mt8192_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840); +check_member(mt8192_mcucfg_regs, mp0_dcm_cfg0, 0x4880); +check_member(mt8192_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg4, 0x48e0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg8, 0x4900); +check_member(mt8192_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00); +check_member(mt8192_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20); +check_member(mt8192_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00); +check_member(mt8192_mcucfg_regs, cpu_type1_mpmmen, 0x4d10); +check_member(mt8192_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20); +check_member(mt8192_mcucfg_regs, cpu_type1_drss_cfg0, 0x4d40); +check_member(mt8192_mcucfg_regs, mcusys_pwr_con, 0x5200); +check_member(mt8192_mcucfg_regs, sec_pol_ctl_en0, 0x5600); +check_member(mt8192_mcucfg_regs, int_pol_ctl0, 0x5668); +check_member(mt8192_mcucfg_regs, int_msk_ctl0, 0x56d0); +check_member(mt8192_mcucfg_regs, int_msk_ctl_all, 0x5744); +check_member(mt8192_mcucfg_regs, dfd_internal_ctl, 0x6040); +check_member(mt8192_mcucfg_regs, dfd_soc_clock_stop_mask, 0x60f0); +check_member(mt8192_mcucfg_regs, dfd_hw_trigger_mask, 0x60fc); +check_member(mt8192_mcucfg_regs, dfd_v50_spare, 0x6300); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg4, 0x7fd0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); + +static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h new file mode 100755 index 0000000..9089996 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PLL_H +#define SOC_MEDIATEK_MT8192_PLL_H + +#include <device/mmio.h> +#include <types.h> +#include <soc/pll_common.h> + +struct mtk_topckgen_regs { + u32 clk_mode; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 clk_cfg_update2; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved1[1]; + u32 clk_cfg_1; /* 0x0020 */ + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved2[1]; + u32 clk_cfg_2; /* 0x0030 */ + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved3[1]; + u32 clk_cfg_3; /* 0x0040 */ + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved4[1]; + u32 clk_cfg_4; /* 0x0050 */ + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved5[1]; + u32 clk_cfg_5; /* 0x0060 */ + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved6[1]; + u32 clk_cfg_6; /* 0x0070 */ + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved7[1]; + u32 clk_cfg_7; /* 0x0080 */ + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved8[1]; + u32 clk_cfg_8; /* 0x0090 */ + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 reserved9[1]; + u32 clk_cfg_9; /* 0x00a0 */ + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 reserved10[1]; + u32 clk_cfg_10; /* 0x00b0 */ + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 reserved11[1]; + u32 clk_cfg_11; /* 0x00c0 */ + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 reserved12[1]; + u32 clk_cfg_12; /* 0x00d0 */ + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved13[1]; + u32 clk_cfg_13; /* 0x00e0 */ + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved14[1]; + u32 clk_cfg_14; /* 0x00f0 */ + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 reserved15[1]; + u32 clk_cfg_15; /* 0x0100 */ + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 reserved16[1]; + u32 clk_cfg_16; /* 0x0110 */ + u32 clk_cfg_16_set; + u32 clk_cfg_16_clr; + u32 reserved17[9]; + u32 clk_misc_cfg_0; /* 0x0140 */ + u32 reserved18[3]; + u32 clk_misc_cfg_1; /* 0x0150 */ + u32 reserved19[10]; + u32 clk_dbg_cfg; /* 0x017c */ + u32 reserved20[32]; + u32 clk_scp_cfg_0; /* 0x0200 */ + u32 reserved21[3]; + u32 clk_scp_cfg_1; /* 0x0210 */ + u32 reserved22[3]; + u32 clk26cali_0; /* 0x0220 */ + u32 clk26cali_1; + u32 reserved23[2]; + u32 cksta_reg; /* 0x0230 */ + u32 cksta_reg1; + u32 cksta_reg2; + u32 reserved24[49]; + u32 clkmon_clk_sel_reg; /* 0x0300 */ + u32 clkmon_k1_reg; + u32 reserved25[6]; + u32 clk_auddiv_0; /* 0x0320 */ + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 aud_top_cfg; + u32 aud_top_mon; + u32 clk_auddiv_3; + u32 clk_auddiv_4; + u32 reserved26[113]; + u32 clk_extck_reg; /* 0x0500 */ +}; + +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0150); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017c); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200); +check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x0210); +check_member(mtk_topckgen_regs, clk26cali_0, 0x0220); +check_member(mtk_topckgen_regs, cksta_reg, 0x0230); +check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x0300); +check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x0500); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 reserved0[2]; + u32 pllon_con0; + u32 pllon_con1; + u32 pllon_con2; + u32 pllon_con3; + u32 reserved1[104]; + u32 ap_pllgp1_con0; /* 0x0200 */ + u32 ap_pllgp1_con1; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl0_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 armpll_bl1_con0; + u32 armpll_bl1_con1; + u32 armpll_bl1_con2; + u32 armpll_bl1_con3; + u32 armpll_bl2_con0; + u32 armpll_bl2_con1; + u32 armpll_bl2_con2; + u32 armpll_bl2_con3; + u32 armpll_bl3_con0; + u32 armpll_bl3_con1; + u32 armpll_bl3_con2; + u32 armpll_bl3_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 ap_pllgp1_con2; + u32 reserved2[33]; + u32 ap_pllgp2_con0; /* 0x0300 */ + u32 ap_pllgp2_con1; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 apupll_con0; + u32 apupll_con1; + u32 apupll_con2; + u32 apupll_con3; + u32 ap_pllgp3_con0; + u32 npupll_con0; + u32 npupll_con1; + u32 npupll_con2; + u32 npupll_con3; + u32 usbpll_con0; + u32 usbpll_con1; + u32 usbpll_con2; +}; + +check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); +check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); +check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); + +enum { + USBPLL_EN = 0x1 << 2, + + PLL_DIV_EN = 0xff << 24, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, +}; + +enum { + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 1075 * MHz, + ARMPLL_BL_HZ = 774 * MHz, + CCIPLL_HZ = 730 * MHz, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + USBPLL_HZ = 192UL * 13 * MHz, + MSDCPLL_HZ = 384 * MHz, + MMPLL_HZ = 2750UL * MHz, + ADSPPLL_HZ = 750 * MHz, + MFGPLL_HZ = 358 * MHz, + TVDPLL_HZ = 594 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, + APUPLL_HZ = 832 * MHz, + NPUPLL_HZ = 728 * MHz, +}; + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, + MAINPLL_D5_D4_HZ = MAINPLL_D5_HZ / 4, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_D4_HZ, + UART_HZ = CLK26M_HZ, +}; + +DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) +DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) + +#endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c new file mode 100755 index 0000000..6a57d07 --- /dev/null +++ b/src/soc/mediatek/mt8192/pll.c @@ -0,0 +1,468 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <delay.h> +#include <stddef.h> + +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/pll.h> + +enum mux_id { + TOP_AXI_SEL, + TOP_SPM_SEL, + TOP_SCP_SEL, + TOP_BUS_AXIMEM_SEL, + TOP_DISP_SEL, + TOP_MDP_SEL, + TOP_IMG1_SEL, + TOP_IMG2_SEL, + TOP_IPE_SEL, + TOP_DPE_SEL, + TOP_CAM_SEL, + TOP_CCU_SEL, + TOP_DSP_SEL, + TOP_DSP1_SEL, + TOP_DSP1_NPUPLL_SEL, + TOP_DSP2_SEL, + TOP_DSP2_NPUPLL_SEL, + TOP_DSP5_SEL, + TOP_DSP5_APUPLL_SEL, + TOP_DSP7_SEL, + TOP_IPU_IF_SEL, + TOP_MFG_REF_SEL, + TOP_MFG_PLL_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_CAMTG4_SEL, + TOP_CAMTG5_SEL, + TOP_CAMTG6_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HCLK_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_MSDC30_2_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_ATB_SEL, + TOP_PWRMCU_SEL, + TOP_DPI_SEL, + TOP_SCAM_SEL, + TOP_DISP_PWM_SEL, + TOP_USB_TOP_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_I2C_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_SENINF2_SEL, + TOP_SENINF3_SEL, + TOP_TL_SEL, + TOP_DXCC_SEL, + TOP_AUD_ENGEN1_SEL, + TOP_AUD_ENGEN2_SEL, + TOP_AES_UFSFDE_SEL, + TOP_UFS_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_ADSP_SEL, + TOP_DPMAIF_MAIN_SEL, + TOP_VENC_SEL, + TOP_VDEC_SEL, + TOP_CAMTM_SEL, + TOP_PWM_SEL, + TOP_AUDIO_H_SEL, + TOP_SPMI_MST_SEL, + TOP_DVFSRC_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_MCUPM_SEL, + TOP_SFLASH_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _set_reg, _clr_reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_set_reg, \ + .clr_reg = &mtk_topckgen->_clr_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = NULL, \ + .upd_shift = 0, \ + } + +#define MUX_UPD(_id, _reg, _set_reg, _clr_reg, _mux_shift, _mux_width, \ + _upd_reg, _upd_shift) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_set_reg, \ + .clr_reg = &mtk_topckgen->_clr_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 0, 3, clk_cfg_update, 0), + MUX_UPD(TOP_SPM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 8, 2, clk_cfg_update, 1), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 16, 3, clk_cfg_update, 2), + MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_DISP_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 0, 4, clk_cfg_update, 4), + MUX_UPD(TOP_MDP_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 8, 4, clk_cfg_update, 5), + MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 16, 4, clk_cfg_update, 6), + MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, clk_cfg_1_set, clk_cfg_1_clr, 24, 4, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_IPE_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 0, 4, clk_cfg_update, 8), + MUX_UPD(TOP_DPE_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 8, 3, clk_cfg_update, 9), + MUX_UPD(TOP_CAM_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 16, 4, clk_cfg_update, 10), + MUX_UPD(TOP_CCU_SEL, clk_cfg_2, clk_cfg_2_set, clk_cfg_2_clr, 24, 4, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_DSP_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 0, 3, clk_cfg_update, 12), + MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 8, 3, clk_cfg_update, 13), + MUX(TOP_DSP1_NPUPLL_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 11, 1), + MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 16, 3, clk_cfg_update, 14), + MUX(TOP_DSP2_NPUPLL_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 19, 1), + MUX_UPD(TOP_DSP5_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 24, 3, clk_cfg_update, 15), + MUX(TOP_DSP5_APUPLL_SEL, clk_cfg_3, clk_cfg_3_set, clk_cfg_3_clr, 27, 1), + /* CLK_CFG_4 */ + MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 0, 3, clk_cfg_update, 16), + MUX_UPD(TOP_IPU_IF_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 8, 3, clk_cfg_update, 17), + MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 16, 2, clk_cfg_update, 18), + MUX(TOP_MFG_PLL_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 18, 1), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, clk_cfg_4_set, clk_cfg_4_clr, 24, 3, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 0, 3, clk_cfg_update, 20), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, clk_cfg_5_set, clk_cfg_5_clr, 24, 3, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 0, 3, clk_cfg_update, 24), + MUX_UPD(TOP_UART_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 8, 1, clk_cfg_update, 25), + MUX_UPD(TOP_SPI_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 16, 2, clk_cfg_update, 26), + MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, clk_cfg_6_set, clk_cfg_6_clr, 24, 2, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 0, 3, clk_cfg_update, 28), + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 8, 3, clk_cfg_update, 29), + MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 16, 3, clk_cfg_update, 30), + MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, clk_cfg_7_set, clk_cfg_7_clr, 24, 2, clk_cfg_update1, 0), + /* CLK_CFG_8 */ + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 0, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 8, 3, clk_cfg_update1, 2), + MUX_UPD(TOP_ATB_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 16, 2, clk_cfg_update1, 3), + MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, clk_cfg_8_set, clk_cfg_8_clr, 24, 3, clk_cfg_update1, 4), + /* CLK_CFG_9 */ + MUX_UPD(TOP_DPI_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 0, 3, clk_cfg_update1, 5), + MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 8, 1, clk_cfg_update1, 6), + MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 16, 3, clk_cfg_update1, 7), + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, clk_cfg_9_set, clk_cfg_9_clr, 24, 2, clk_cfg_update1, 8), + /* CLK_CFG_10 */ + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 0, 2, clk_cfg_update1, 9), + MUX_UPD(TOP_I2C_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 8, 2, clk_cfg_update1, 10), + MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 16, 3, clk_cfg_update1, 11), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, clk_cfg_10_set, clk_cfg_10_clr, 24, 3, clk_cfg_update1, 12), + /* CLK_CFG_11 */ + MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 0, 3, clk_cfg_update1, 13), + MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 8, 3, clk_cfg_update1, 14), + MUX_UPD(TOP_TL_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 16, 2, clk_cfg_update1, 15), + MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, clk_cfg_11_set, clk_cfg_11_clr, 24, 2, clk_cfg_update1, 16), + /* CLK_CFG_12 */ + MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 0, 2, clk_cfg_update1, 17), + MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 8, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 16, 3, clk_cfg_update1, 19), + MUX_UPD(TOP_UFS_SEL, clk_cfg_12, clk_cfg_12_set, clk_cfg_12_clr, 24, 3, clk_cfg_update1, 20), + /* CLK_CFG_13 */ + MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 0, 1, clk_cfg_update1, 21), + MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 8, 1, clk_cfg_update1, 22), + MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 16, 3, clk_cfg_update1, 23), + MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, clk_cfg_13_set, clk_cfg_13_clr, 24, 3, clk_cfg_update1, 24), + /* CLK_CFG_14 */ + MUX_UPD(TOP_VENC_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 0, 4, clk_cfg_update1, 25), + MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 8, 4, clk_cfg_update1, 26), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 16, 2, clk_cfg_update1, 27), + MUX_UPD(TOP_PWM_SEL, clk_cfg_14, clk_cfg_14_set, clk_cfg_14_clr, 24, 1, clk_cfg_update1, 28), + /* CLK_CFG_15 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 0, 2, clk_cfg_update1, 29), + MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 8, 3, clk_cfg_update1, 30), + MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 16, 1, clk_cfg_update2, 0), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, clk_cfg_15_set, clk_cfg_15_clr, 24, 3, clk_cfg_update2, 1), + /* CLK_CFG_16 */ + MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, clk_cfg_16_set, clk_cfg_16_clr, 0, 2, clk_cfg_update2, 2), + MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, clk_cfg_16_set, clk_cfg_16_clr, 8, 2, clk_cfg_update2, 3), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ + { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ + { .id = TOP_SCP_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + /* CLK_CFG_1 */ + { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mainpll_d4 */ + { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: tvdpll_ck */ + { .id = TOP_IMG1_SEL, .sel = 1 }, /* 1: univpll_d4 */ + { .id = TOP_IMG2_SEL, .sel = 1 }, /* 1: univpll_d4 */ + /* CLK_CFG_2 */ + { .id = TOP_IPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_DPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_CAM_SEL, .sel = 3 }, /* 3: univpll_d4 */ + { .id = TOP_CCU_SEL, .sel = 8 }, /* 8: univpll_d5 */ + /* CLK_CFG_3 */ + { .id = TOP_DSP_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + { .id = TOP_DSP1_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */ + { .id = TOP_DSP1_NPUPLL_SEL, .sel = 0 }, /* 0: dsp1_sel */ + { .id = TOP_DSP2_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */ + { .id = TOP_DSP2_NPUPLL_SEL, .sel = 0 }, /* 0: dsp2_sel */ + { .id = TOP_DSP5_SEL, .sel = 2 }, /* 2: univpll_d4_d2 */ + { .id = TOP_DSP5_APUPLL_SEL, .sel = 0 }, /* 0: dsp5_sel */ + /* CLK_CFG_4 */ + { .id = TOP_DSP7_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_IPU_IF_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + { .id = TOP_MFG_REF_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + { .id = TOP_MFG_PLL_SEL, .sel = 1 }, /* 1: mfgpll */ + { .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_5 */ + { .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG5_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_6 */ + { .id = TOP_CAMTG6_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_7 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + { .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_MSDC30_2_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_8 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: osc_d10 */ + { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_d2 */ + { .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + /* CLK_CFG_10 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ + { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */ + /* CLK_CFG_11 */ + { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_TL_SEL, .sel = 1 }, /* 1: univpll_192m_d2 */ + { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_12 */ + { .id = TOP_AUD_ENGEN1_SEL, .sel = 2 }, /* 2: apll1_d4 */ + { .id = TOP_AUD_ENGEN2_SEL, .sel = 2 }, /* 2: apll2_d4 */ + { .id = TOP_AES_UFSFDE_SEL, .sel = 6 }, /* 6: univpll_d6 */ + { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */ + /* CLK_CFG_13 */ + { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ + { .id = TOP_ADSP_SEL, .sel = 7 }, /* 7: adsppll_ck */ + { .id = TOP_DPMAIF_MAIN_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_14 */ + { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ + { .id = TOP_VDEC_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ + { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ + { .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_15 */ + { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ + { .id = TOP_SPMI_MST_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ + /* CLK_CFG_16 */ + { .id = TOP_MCUPM_SEL, .sel = 2 }, /* 2: mainpll_d6_d2 */ + { .id = TOP_SFLASH_SEL, .sel = 1 }, /* 1: mainpll_d7_d8 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_MAINPLL, + APMIXED_UNIVPLL, + APMIXED_USBPLL, + APMIXED_MSDCPLL, + APMIXED_MMPLL, + APMIXED_ADSPPLL, + APMIXED_MFGPLL, + APMIXED_TVDPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_APUPLL, + APMIXED_NPUPLL, + APMIXED_PLL_MAX +}; + +const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl0_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, + 23, 22, univpll_con1, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_USBPLL, usbpll_con0, usbpll_con2, + NO_RSTB_SHIFT, 22, usbpll_con0, 24, usbpll_con0, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + 23, 22, mmpll_con1, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, + NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, + pll_div_rate), + PLL(APMIXED_APUPLL, apupll_con0, apupll_con3, + NO_RSTB_SHIFT, 22, apupll_con1, 24, apupll_con1, 0, + pll_div_rate), + PLL(APMIXED_NPUPLL, npupll_con0, npupll_con3, + NO_RSTB_SHIFT, 22, npupll_con1, 24, npupll_con1, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, + { .id = APMIXED_USBPLL, .rate = USBPLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, + { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, + { .id = APMIXED_APUPLL, .rate = APUPLL_HZ }, + { .id = APMIXED_NPUPLL, .rate = NPUPLL_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, 0x2); + + /* reduce PLL current */ + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp1_con1, PLLGP1_LVRREF, 1); + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp2_con1, PLLGP2_LVRREF, 1); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (i == APMIXED_USBPLL) + setbits32(plls[APMIXED_USBPLL].pwr_reg, USBPLL_EN); + else + setbits32(plls[i].reg, PLL_EN); + } + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* enable infrasys DCM */ + setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + + /* initialize SPM request */ + setbits32(&mtk_topckgen->clk_scp_cfg_0 , 0x3ff); + clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); + + /* + * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! + */ + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* enable [14] dramc_pll104m_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Gerrit-Change-Number: 43958 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: soc/mediatek/mt8192: Add gpio driver
by CK HU (Code Review) 12 Aug '20

12 Aug '20

Hello Po Xu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43959 to review the following change. Change subject: soc/mediatek/mt8192: Add gpio driver ...................................................................... soc/mediatek/mt8192: Add gpio driver Add MT8192 GPIO driver. Signed-off-by: Po Xu <jg_poxu(a)mediatek.com> Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b --- A src/soc/mediatek/mt8192/gpio.c A src/soc/mediatek/mt8192/include/soc/gpio.h A src/soc/mediatek/mt8192/include/soc/gpio_base.h 3 files changed, 887 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/43959/1 diff --git a/src/soc/mediatek/mt8192/gpio.c b/src/soc/mediatek/mt8192/gpio.c new file mode 100755 index 0000000..717e21e --- /dev/null +++ b/src/soc/mediatek/mt8192/gpio.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <gpio.h> +#include <assert.h> + +static void* gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + switch(gpio.base & 0x0f) { + case 0: + reg_addr = (void *)IOCFG_RM_BASE; + break; + case 1: + reg_addr = (void *)IOCFG_BM_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_BL_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_BR_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_LB_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_RT_BASE; + break; + case 7: + reg_addr = (void *)IOCFG_LT_BASE; + break; + case 8: + reg_addr = (void *)IOCFG_TL_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, 1 << bit); + else + clrbits32(reg1, 1 << bit); + } + + if (enable == GPIO_PULL_ENABLE) + setbits32(reg2, 1 << bit); + else { + clrbits32(reg2, 1 << bit); + clrbits32(reg2 + 0x010, 1 << bit); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, 1 << bit); + setbits32(reg2, 1 << bit); + } else { + clrbits32(reg2, 1 << bit); + setbits32(reg1, 1 << bit); + } + } else { + clrbits32(reg1, 1 << bit); + clrbits32(reg2, 1 << bit); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} + diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h new file mode 100644 index 0000000..c90f736 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/gpio.h @@ -0,0 +1,740 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8192_GPIO_H +#define SOC_MEDIATEK_MT8192_GPIO_H + +#include <soc/addressmap.h> +#include <soc/gpio_common.h> +#include <types.h> + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +enum { + PIN(0, EINT0, 0, 9, 0x23, 0xb0, + SPI6_CLK, I2S5_MCK, PWM_0, TDM_LRCK, + TP_GPIO0_AO, MD_INT0, RES7), + PIN(1, EINT1, 0, 10, 0x23, 0xb0, + SPI6_CSB, I2S5_BCK, PWM_1, TDM_BCK, + TP_GPIO1_AO, MD_INT1_C2K_UIM0_HOT_PLUG, DBG_MON_A9), + PIN(2, EINT2, 0, 11, 0x23, 0xb0, + SPI6_MI, I2S5_LRCK, PWM_2, TDM_MCK, + TP_GPIO2_AO, MD_INT2_C2K_UIM1_HOT_PLUG, DBG_MON_A10), + PIN(3, EINT3, 0, 12, 0x23, 0xb0, + SPI6_MO, I2S5_DO, PWM_3, TDM_DATA0, + TP_GPIO3_AO, CLKM0, DBG_MON_A11), + PIN(4, EINT4, 0, 13, 0x23, 0xb0, + SPI4_A_CLK, I2S2_MCK, DMIC1_CLK, TDM_DATA1, + TP_GPIO4_AO, PCM1_DI, IDDIG), + PIN(5, EINT5, 0, 14, 0x23, 0xb0, + SPI4_A_CSB, I2S2_BCK, DMIC1_DAT, + TDM_DATA2, TP_GPIO5_AO, PCM1_CLK, USB_DRVVBUS), + PIN(6, EINT6, 0, 15, 0x23, 0xb0, + SPI4_A_MI, I2S2_LRCK, DMIC_CLK, TDM_DATA3, + TP_GPIO6_AO, PCM1_SYNC, RES7), + PIN(7, EINT7, 0, 16, 0x23, 0xb0, + SPI4_A_MO, I2S2_DI, DMIC_DAT, WIFI_TXD, + TP_GPIO7_AO, PCM1_DO0, RES7), + PIN(8, EINT8, 0, 17, 0x23, 0xb0, + SRCLKENAI1, I2S2_DI2, KPCOL2, + CONN_TCXOENA_REQ, CLKM1, PCM1_DO1, DBG_MON_A12), + PIN(9, EINT9, 0, 18, 0x23, 0xb0, + SRCLKENAI0, DVFSRC_EXT_REQ, KPROW2, + CMMCLK4, CLKM3, PCM1_DO2, DBG_MON_A13), + PIN(10, EINT10, 1, 0, 0x15, 0x20, + MSDC2_CLK, SPI4_B_CLK, I2S8_MCK, + RES4, MD_INT0, TP_GPIO8_AO, RES7), + PIN(11, EINT11, 1, 1, 0x15, 0x20, + MSDC2_CMD, SPI4_B_CSB, I2S8_BCK, PCIE_CLKREQ_N, + MD_INT1_C2K_UIM0_HOT_PLUG, TP_GPIO9_AO, RES7), + PIN(12, EINT12, 1, 2, 0x15, 0x20, + MSDC2_DAT3, SPI4_B_MI, I2S8_LRCK, DMIC1_CLK, + MD_INT2_C2K_UIM1_HOT_PLUG, TP_GPIO10_AO, RES7), + PIN(13, EINT13, 1, 3, 0x15, 0x20, + DMSDC2_DAT0, SPI4_B_MO, I2S8_DI, DMIC1_DAT, + ANT_SEL10, TP_GPIO11_AO, RES7), + PIN(14, EINT14, 1, 4, 0x15, 0x20, + MSDC2_DAT2, IDDIG, SCL_6306, PCIE_PERESET_N, + ANT_SEL11, TP_GPIO12_AO, RES7), + PIN(15, EINT15, 1, 5, 0x15, 0x20, + MSDC2_DAT1, USB_DRVVBUS, SDA_6306, + PCIE_WAKE_N, ANT_SEL12, TP_GPIO13_AO, RES7), + PIN(16, EINT16, 0, 2, 0x17, 0x50, + SRCLKENAI1, IDDIG, TP_GPIO14_AO, KPCOL2, + GPS_L1_ELNA_EN, SPI7_A_MI, DBG_MON_A0), + PIN(17, EINT17, 0, 3, 0x17, 0x50, + SRCLKENAI0, USB_DRVVBUS, TP_GPIO15_AO, + KPROW2, RES5, SPI7_A_MO, DBG_MON_A1), + PIN(18, EINT18, 0, 21, 0x36, 0xa0, + SRCLKENAI0, SPI4_C_MI, SPI1_B_MI, + GPS_L1_ELNA_EN, ANT_SEL10, MD_INT0, DBG_MON_B2), + PIN(19, EINT19, 0, 22, 0x36, 0xa0, + SRCLKENAI1, SPI4_C_MO, SPI1_B_MO, RES4, + ANT_SEL11, MD_INT1_C2K_UIM0_HOT_PLUG, DBG_MON_B3), + PIN(20, EINT20, 0, 23, 0x36, 0xa0, + SRCLKENAI0, SPI4_C_CLK, SPI1_B_CLK, PWM_3, + ANT_SEL12, MD_INT2_C2K_UIM1_HOT_PLUG, DBG_MON_B4), + PIN(21, EINT21, 0, 24, 0x36, 0xa0, + RES1, SPI4_C_CSB, SPI1_B_CSB, RES4, + RES5, IDDIG, DBG_MON_B5), + PIN(22, EINT22, 0, 3, 0x21, 0x90, + RES1, SPI0_C_CLK, SPI7_B_CLK, I2S7_BCK, + I2S9_BCK, SCL_6306, RES7), + PIN(23, EINT23, 0, 4, 0x21, 0x90, + RES1, SPI0_C_CSB, SPI7_B_CSB, I2S7_LRCK, + I2S9_LRCK, SDA_6306, RES7), + PIN(24, EINT24, 0, 5, 0x21, 0x90, + SRCLKENAI1, SPI0_C_MI, SPI7_B_MI, I2S6_DI, + I2S8_DI, SPINOR_CS, RES7), + PIN(25, EINT25, 0, 6, 0x21, 0x90, + SRCLKENAI0, SPI0_C_MO, SPI7_B_MO, + I2S7_DO, I2S9_DO, SPINOR_CK, RES7), + PIN(26, PERIPHERAL_EN4, 0, 5, 0x22, 0x80, + PWM_2, CLKM0, USB_DRVVBUS, SPI5_C_MI, + I2S9_BCK, RES6, RES7), + PIN(27, PERIPHERAL_EN5, 0, 6, 0x22, 0x80, + PWM_3, CLKM1, RES3, SPI5_C_MO, + I2S9_LRCK, SPINOR_IO0, RES7), + PIN(28, PERIPHERAL_EN6, 0, 7, 0x22, 0x80, + PWM_0, CLKM2, RES3, SPI5_C_CSB, + I2S9_MCK, SPINOR_IO1, RES7), + PIN(29, PERIPHERAL_EN7, 0, 8, 0x22, 0x80, + PWM_1, CLKM3, RES3, SPI5_C_CLK, + I2S9_DO, SPINOR_IO2, RES7), + PIN(30, PERIPHERAL_EN8, 0, 9, 0x22, 0x80, + PWM_2, CLKM0, GPS_L1_ELNA_EN, I2S7_MCK, + I2S9_MCK, SPINOR_IO3, RES7), + PIN(31, I2S3_MCK, 0, 27, 0x22, 0x70, + I2S3_MCK, I2S1_MCK, I2S5_MCK, + SRCLKENAI0, I2S0_MCK, RES6, RES7), + PIN(32, I2S3_BCK, 0, 24, 0x22, 0x70, + I2S3_BCK, I2S1_BCK, I2S5_BCK, + PCM0_CLK, I2S0_BCK, RES6, RES7), + PIN(33, I2S3_LRCK, 0, 26, 0x22, 0x70, + I2S3_LRCK, I2S1_LRCK, I2S5_LRCK, + PCM0_SYNC, I2S0_LRCK, RES6, RES7), + PIN(34, I2S0_DI, 0, 23, 0x22, 0x70, + I2S3_DO, I2S1_DO, I2S5_DO, PCM0_DO, + RES5, RES6, RES7), + PIN(35, I2S3_DO, 0, 25, 0x22, 0x70, + I2S3_DO, I2S1_DO, I2S5_DO, + PCM0_DO, RES5, RES6, RES7), + PIN(36, SPI5_CLK, 0, 20, 0x21, 0x90, + SPI5_A_CLK, DMIC1_CLK, RES3, + MD_URXD0, UCTS0, URXD1, RES7), + PIN(37, SPI5_CSB, 0, 21, 0x21, 0x90, + SPI5_A_CSB, DMIC1_DAT, RES3, + MD_UTXD0, URTS0, UTXD1, RES7), + PIN(38, SPI5_MI, 0, 22, 0x21, 0x90, + SPI5_A_MI, DMIC_CLK, RES3, + MD_URXD1, URXD0, UCTS1, RES7), + PIN(39, SPI5_MO, 0, 23, 0x21, 0x90, + SPI5_A_MO, DMIC_DAT, RES3, + MD_UTXD1, UTXD0, URTS1, RES7), + PIN(40, DISP_PWM, 0, 0, 0x17, 0x50, + DISP_PWM, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A6), + PIN(41, DSI_TE, 0, 1, 0x17, 0x50, + DSI_TE, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A7), + PIN(42, LCM_RST, 0, 4, 0x17, 0x50, + LCM_RST, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A8), + PIN(43, INT_SIM1, 0, 25, 0x36, 0xa0, + MD_INT1_C2K_UIM0_HOT_PLUG, + MD_INT2_C2K_UIM1_HOT_PLUG, SCL_6306, ADSP_URXD0, PTA_RXD, SSPM_URXD_AO, DBG_MON_B0), + PIN(44, INT_SIM2, 0, 26, 0x36, 0xa0, + MD_INT2_C2K_UIM1_HOT_PLUG, MD_INT1_C2K_UIM0_HOT_PLUG, + SDA_6306, ADSP_UTXD0, PTA_TXD, SSPM_UTXD_AO, DBG_MON_B1), + PIN(45, SIM2_SCLK, 1, 9, 0x20, 0x60, + MD1_SIM2_SCLK, MD1_SIM1_SCLK, MCUPM_JTAG_TDI, + APU_JTAG_TDI, CCU_JTAG_TDI, LVTS_SCK, CONN_DSP_JDI), + PIN(46, SIM2_SRST, 1, 11, 0x20, 0x60, + MD1_SIM2_SRST, MD1_SIM1_SRST, MCUPM_JTAG_TMS, + APU_JTAG_TMS, CCU_JTAG_TMS, LVTS_SDI, CONN_DSP_JMS), + PIN(47, SIM2_SIO, 1, 10, 0x20, 0x60, + MD1_SIM2_SIO, MD1_SIM1_SIO, MCUPM_JTAG_TDO, + APU_JTAG_TDO, CCU_JTAG_TDO, LVTS_SCF, CONN_DSP_JDO), + PIN(48, SIM1_SIO, 1, 7, 0x20, 0x60, + MD1_SIM1_SIO, MD1_SIM2_SIO, MCUPM_JTAG_TRSTN, + APU_JTAG_TRST, CCU_JTAG_TRST, LVTS_FOUT, CONN_DSP_JINTP), + PIN(49, SIM1_SRST, 1, 8, 0x20, 0x60, + MD1_SIM1_SRST, MD1_SIM2_SRST, MCUPM_JTAG_TCK, + APU_JTAG_TCK, CCU_JTAG_TCK, LVTS_SDO, CONN_DSP_JCK), + PIN(50, SIM1_SCLK, 1, 6, 0x20, 0x60, + MD1_SIM1_SCLK, MD1_SIM2_SCLK, RES3, + RES4, RES5, LVTS_26M, RES7), + PIN(51, MSDC1_CLK, 1, 0, 0x20, 0x60, + MSDC1_CLK, PCM1_CLK, CONN_DSP_JCK, UDI_TCK, + IPU_JTAG_TCK, SSPM_JTAG_TCK, JTCK_SEL3), + PIN(52, MSDC1_CMD, 1, 1, 0x20, 0x60, + MSDC1_CMD, PCM1_SYNC, CONN_DSP_JMS, UDI_TMS, + IPU_JTAG_TMS, SSPM_JTAG_TMS, JTMS_SEL3), + PIN(53, MSDC1_DAT3, 1, 5, 0x20, 0x60, + MSDC1_DAT3, PCM1_DI, CONN_DSP_JINTP, + CONN_MCU_AICE_TMSC, , RES6, RES7), + PIN(54, MSDC1_DAT0, 1, 2, 0x20, 0x60, + MSDC1_DAT0, PCM1_DO0, CONN_DSP_JDI, + UDI_TDI, IPU_JTAG_TDI, SSPM_JTAG_TDI, JTDI_SEL3), + PIN(55, MSDC1_DAT2, 1, 4, 0x20, 0x60, + MSDC1_DAT2, PCM1_DO2, CONN_MCU_AICE_TCKC, + UDI_NTRST, IPU_JTAG_TRST, SSPM_JTAG_TRSTN, JTRSTN_SEL3), + PIN(56, MSDC1_DAT1, 1, 3, 0x20, 0x60, + MSDC1_DAT1, PCM1_DO1, CONN_DSP_JDO, UDI_TDO, + IPU_JTAG_TDO, SSPM_JTAG_TDO, JTDO_SEL3), + PIN(57,MIPI2_D_SCLK, 0, 1, 0x22, 0x80, + MIPI2_D_SCLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(58, MIPI2_D_SDATA, 0, 2, 0x22, 0x80, + MIPI2_D_SDATA, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(59, MIPI_M_SCLK, 0, 3, 0x22, 0x80, + MIPI_M_SCLK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(60, MIPI_M_SDATA, 0, 4, 0x22, 0x80, + MIPI_M_SDATA, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(61, MD_UCNT, 0, 28, 0x22, 0x70, + MD_UCNT_A_TGL, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(62, DIGRF_IRQ, 0, 22, 0x22, 0x70, + DIGRF_IRQ, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(63, BPI_D_BUS0, 0, 0, 0x22, 0x70, + BPI_BUS0, RES2, PCIE_WAKE_N, + RES4, RES5, RES6, RES7), + PIN(64, BPI_D_BUS1, 0, 1, 0x22, 0x70, + BPI_BUS1, RES2, PCIE_PERESET_N, + RES4, RES5, RES6, RES7), + PIN(65, BPI_D_BUS2, 0, 12, 0x22, 0x70, + BPI_BUS2, RES2, PCIE_CLKREQ_N, + RES4, RES5, RES6, RES7), + PIN(66, BPI_D_BUS3, 0, 15, 0x22, 0x70, + BPI_BUS3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(67, BPI_D_BUS4, 0, 16, 0x22, 0x70, + BPI_BUS4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(68, BPI_D_BUS5, 0, 17, 0x22, 0x70, + BPI_BUS5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(69, BPI_D_BUS6, 0, 18, 0x22, 0x70, + BPI_BUS6, CONN_BPI_BUS6, + RES3, RES4, RES5, RES6, RES7), + PIN(70, BPI_D_BUS7, 0, 19, 0x22, 0x70, + BPI_BUS7, CONN_BPI_BUS7, RES3, + RES4, RES5, RES6, RES7), + PIN(71, BPI_D_BUS8, 0, 20, 0x22, 0x70, + BPI_BUS8, CONN_BPI_BUS8, + RES3, RES4, RES5, RES6, RES7), + PIN(72, BPI_D_BUS9, 0, 21, 0x22, 0x70, + BPI_BUS9, CONN_BPI_BUS9, + RES3, RES4, RES5, RES6, RES7), + PIN(73, BPI_D_BUS10, 0, 2, 0x22, 0x70, + BPI_BUS10, CONN_BPI_BUS10, + RES3, RES4, RES5, RES6, RES7), + PIN(74, BPI_D_BUS11_OLAT0, 0, 3, 0x22, 0x70, + BPI_BUS11_OLAT0, CONN_BPI_BUS11_OLAT0, + RES3, RES4, RES5, RES6, RES7), + PIN(75, BPI_D_BUS12_OLAT1, 0, 4, 0x22, 0x70, + BPI_BUS12_OLAT1, CONN_BPI_BUS12_OLAT1, + RES3, RES4, RES5, RES6, RES7), + PIN(76, BPI_D_BUS13_OLAT2, 0, 5, 0x22, 0x70, + BPI_BUS13_OLAT2, CONN_BPI_BUS13_OLAT2, + RES3, RES4, RES5, RES6, RES7), + PIN(77, BPI_D_BUS14_OLAT3, 0, 6, 0x22, 0x70, + BPI_BUS14_OLAT3, CONN_BPI_BUS14_OLAT3, + RES3, RES4, RES5, RES6, RES7), + PIN(78, BPI_D_BUS15_OLAT4, 0, 7, 0x22, 0x70, + BPI_BUS15_OLAT4, CONN_BPI_BUS15_OLAT4, + RES3, RES4, RES5, RES6, RES7), + PIN(79, BPI_D_BUS16_OLAT5, 0, 8, 0x22, 0x70, + BPI_BUS16_OLAT5, CONN_BPI_BUS16_OLAT5, + RES3, RES4, RES5, RES6, RES7), + PIN(80, BPI_D_BUS17_ANT0, 0, 9, 0x22, 0x70, + BPI_BUS17_ANT0, CONN_BPI_BUS17_ANT0, + PCIE_WAKE_N, RES4, RES5, RES6, RES7), + PIN(81, BPI_D_BUS18_ANT1, 0, 10, 0x22, 0x70, + BPI_BUS18_ANT1, CONN_BPI_BUS18_ANT1, + PCIE_PERESET_N, RES4, RES5, RES6, RES7), + PIN(82, BPI_D_BUS19_ANT2, 0, 11, 0x22, 0x70, + BPI_BUS19_ANT2, CONN_BPI_BUS19_ANT2, + PCIE_CLKREQ_N, RES4, RES5, RES6, RES7), + PIN(83, BPI_D_BUS20_ANT3, 0, 13, 0x22, 0x70, + BPI_BUS20_ANT3, CONN_BPI_BUS20_ANT3, + RES3, RES4, RES5, RES6, RES7), + PIN(84, BPI_D_BUS21_ANT4, 0, 14, 0x22, 0x70, + BPI_BUS21_ANT4, CONN_BPI_BUS21_ANT4, + RES3, RES4, RES5, RES6, RES7), + PIN(85, MIPI1_D_SCLK, 0, 31, 0x22, 0x70, + MIPI1_D_SCLK, CONN_MIPI1_SCLK, + RES3, RES4, RES5, RES6, RES7), + PIN(86, MIPI1_D_SDATA, 0, 0, 0x22, 0x80, + MIPI1_D_SDATA, CONN_MIPI1_SDATA, + RES3, RES4, RES5, RES6, RES7), + PIN(87, MIPI0_D_SCLK, 0, 29, 0x22, 0x70, + MIPI0_D_SCLK, CONN_MIPI0_SCLK, + RES3, RES4, RES5, RES6, RES7), + PIN(88, MIPI0_D_SDATA, 0, 30, 0x22, 0x70, + SMIPI0_D_SDATA, CONN_MIPI0_SDATA, + RES3, RES4, RES5, RES6, RES7), + PIN(89, SPMI_SCL, 0, 24, 0x21, 0x90, + SPMI_SCL, SCL10, RES3, + RES4, RES5, RES6, RES7), + PIN(90, SPMI_SDA, 0, 25, 0x21, 0x90, + SPMI_SDA, SDA10, RES3, + RES4, RES5, RES6, RES7), + PIN(91, AP_GOOD, 0, 0, 0x21, 0x90, + AP_GOOD, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(92, URXD0, 0, 2, 0x21, 0xa0, + URXD0, MD_URXD0, MD_URXD1, + SSPM_URXD_AO, CONN_UART0_RXD, RES6, RES7), + PIN(93, UTXD0, 0, 4, 0x21, 0xa0, + UTXD0, MD_UTXD0, MD_UTXD1, SSPM_UTXD_AO, + CONN_UART0_TXD, WIFI_TXD, RES7), + PIN(94, URXD1, 0, 3, 0x21, 0xa0, + URXD1, ADSP_URXD0, MD32_0_RXD, + SSPM_URXD_AO, TP_URXD1_AO, TP_URXD2_AO, MBISTREADEN_TRIGGER), + PIN(95, UTXD1, 0, 5, 0x21, 0xa0, + UTXD1, ADSP_UTXD0, MD32_0_TXD, SSPM_UTXD_AO, + TP_UTXD1_AO, TP_UTXD2_AO, MBISTWRITEEN_TRIGGER), + PIN(96, TDM_LRCK, 0, 31, 0x21, 0x90, + TDM_LRCK, I2S7_LRCK, I2S9_LRCK, + DPI_D0, ADSP_JTAG0_TDI, RES6, IO_JTAG_TDI), + PIN(97, TDM_BCK, 0, 26, 0x21, 0x90, + TDM_BCK, I2S7_BCK, I2S9_BCK, DPI_D1, + ADSP_JTAG0_TRSTN, RES6, IO_JTAG_TRSTN), + PIN(98, TDM_MCLK, 0, 0, 0x21, 0xa0, + TDM_MCK, I2S7_MCK, I2S9_MCK, DPI_D2, + ADSP_JTAG0_TCK, RES6, IO_JTAG_TCK), + PIN(99, TDM_DATA0, 0, 27, 0x21, 0x90, + TDM_DATA0, I2S6_DI, I2S8_DI, DPI_D3, + ADSP_JTAG0_TDO, RES6, IO_JTAG_TDO), + PIN(100, TDM_DATA1, 0, 28, 0x21, 0x90, + TDM_DATA1, I2S7_DO, I2S9_DO, DPI_D4, + ADSP_JTAG0_TMS, RES6, IO_JTAG_TMS), + PIN(101, TDM_DATA2, 0, 29, 0x21, 0x90, + TDM_DATA2, DMIC1_CLK, SRCLKENAI0, DPI_D5, + CLKM0, RES6, DAP_MD32_SWD), + PIN(102, TDM_DATA3, 0, 30, 0x21, 0x90, + TDM_DATA3, DMIC1_DAT, SRCLKENAI1, + DPI_D6, RES5, DVFSRC_EXT_REQ, DAP_MD32_SWCK), + PIN(103, SPI0_MI, 0, 18, 0x21, 0x90, + SPI0_A_MI, SCP_SPI0_MI, RES3, DPI_D7, + DFD_TDO, SPM_JTAG_TDO, JTDO_SEL1), + PIN(104, SPI0_CSB, 0, 17, 0x21, 0x90, + SPI0_A_CSB, SCP_SPI0_CS, RES3, DPI_D8, DFD_TMS, + SPM_JTAG_TMS, JTMS_SEL1), + PIN(105, SPI0_MO, 0, 19, 0x21, 0x90, + SPI0_A_MO, SCP_SPI0_MO, SCP_SDA0, DPI_D9, + DFD_TDI, SPM_JTAG_TDI, JTDI_SEL1), + PIN(106, SPI0_CLK, 0, 16, 0x21, 0x90, + SPI0_A_CLK, SCP_SPI0_CK, SCP_SCL0, + DPI_D10, DFD_TCK_XI, SPM_JTAG_TCK, JTCK_SEL1), + PIN(107, DMIC_CLK, 0, 1, 0x21, 0x90, + DMIC_CLK, PWM_0, CLKM2, RES4, RES5, + SPM_JTAG_TRSTN, JTRSTN_SEL1), + PIN(108, DMIC_DAT, 0, 2, 0x21, 0x90, + DMIC_DAT, PWM_1, CLKM3, RES4, + RES5, RES6, DAP_SONIC_SWD), + PIN(109, I2S1_MCK, 0, 10, 0x21, 0x90, + I2S1_MCK, I2S3_MCK, I2S2_MCK, DPI_DE, + I2S2_MCK_1, SRCLKENAI0, DAP_SONIC_SWCK), + PIN(110, I2S1_BCK, 0, 7, 0x21, 0x90, + I2S1_BCK, I2S3_BCK, I2S2_BCK, DPI_D11, + I2S2_BCK_1, CONN_MCU_TDO, RES7), + PIN(111, I2S1_LRCK, 0, 9, 0x21, 0x90, + I2S1_LRCK, I2S3_LRCK, I2S2_LRCK, + DPI_VSYNC, I2S2_LRCK_1, CONN_MCU_TDI, RES7), + PIN(112, I2S2_DI, 0, 11, 0x21, 0x90, + I2S2_DI, I2S0_DI, I2S2_DI2, DPI_CK, + I2S2_DI_1, CONN_MCU_TMS, RES7), + PIN(113, I2S1_DO, 0, 8, 0x21, 0x90, + I2S1_DO, I2S3_DO, I2S5_DO, DPI_HSYNC, + I2S2_DI2, CONN_MCU_TCK, RES7), + PIN(114, SCP_SPI2_MI, 0, 14, 0x21, 0x90, + SPI2_MI, SCP_SPI2_MI, RES3, + PCM0_DI, RES5, CONN_MCU_TRST_B, RES7), + PIN(115, SCP_SPI2_CSB, 0, 13, 0x21, 0x90, + SPI2_CSB, SCP_SPI2_CS, RES3, PCM0_SYNC, + RES5, CONN_MCU_DBGI_N, RES7), + PIN(116, SCP_SPI2_MO, 0, 15, 0x21, 0x90, + SPI2_MO, SCP_SPI2_MO, SCP_SDA1, + PCM0_DO, RES5, CONN_MCU_DBGACK_N, RES7), + PIN(117, SCP_SPI2_CK, 0, 12, 0x21, 0x90, + SPI2_CLK, SCP_SPI2_CK, SCP_SCL1, + PCM0_CLK, RES5, RES6, RES7), + PIN(118, SCL1, 0, 23, 0x23, 0xb0, + SCL1, SCP_SCL0, SCP_SCL1, + RES4, RES5, RES6, RES7), + PIN(119, SDA1, 0, 29, 0x23, 0xb0, + SDA1, SCP_SDA0, SCP_SDA1, + RES4, RES5, RES6, RES7), + PIN(120, SCL9, 0, 28, 0x23, 0xb0, + SCL9, SCP_SCL0, RES3, + RES4, RES5, RES6, RES7), + PIN(121, SDA9, 0, 2, 0x23, 0xc0, + SDA9, SCP_SDA0, RES3, + RES4, RES5, RES6, RES7), + PIN(122, SCL8, 0, 27, 0x23, 0xb0, + SCL8, SCP_SDA0, RES3, + RES4, RES5, RES6, RES7), + PIN(123, SDA8, 0, 1, 0x23, 0xc0, + SDA8, SCP_SCL0, RES3, + RES4, RES5, RES6, RES7), + PIN(124, SCL7, 0, 26, 0x23, 0xb0, + SCL7, DMIC1_CLK, RES3, + RES4, RES5, RES6, RES7), + PIN(125, SDA7, 0, 0, 0x23, 0xc0, + SDA7, DMIC1_DAT, RES3, + RES4, RES5, RES6, RES7), + PIN(126, PERIPHERAL_EN0, 0, 19, 0x23, 0xb0, + CMFLASH0, PWM_2, TP_UCTS1_AO, + UCTS0, SCL11, GPS_L1_ELNA_EN, DBG_MON_A14), + PIN(127, PERIPHERAL_EN1, 0, 20, 0x23, 0xb0, + CMFLASH1, PWM_3, TP_URTS1_AO, URTS0, + SDA11, RES6, DBG_MON_A15), + PIN(128, PERIPHERAL_EN2, 0, 21, 0x23, 0xb0, + CMFLASH2, PWM_0, TP_UCTS2_AO, + UCTS1, SCL_6306, RES6, DBG_MON_A16), + PIN(129, PERIPHERAL_EN3, 0, 22, 0x23, 0xb0, + CMFLASH3, PWM_1, TP_URTS2_AO, URTS1, + SDA_6306, RES6, DBG_MON_A17), + PIN(130, CAM_RST3, 0, 6, 0x23, 0xb0, + CMVREF0, ANT_SEL10, SCP_JTAG0_TDO, + MD32_0_JTAG_TDO, SCL11, SPI5_B_CLK, DBG_MON_A22), + PIN(131, CAM_RST4, 0, 7, 0x23, 0xb0, + CMVREF1, ANT_SEL11, SCP_JTAG0_TDI, + MD32_0_JTAG_TDI, SDA11, SPI5_B_MO, DBG_MON_A25), + PIN(132, CAM_RST5, 0, 8, 0x23, 0xb0, + CMVREF2, ANT_SEL12, SCP_JTAG0_TMS, + MD32_0_JTAG_TMS, RES5, RES6, DBG_MON_A28), + PIN(133, CAM_PDN3, 0, 3, 0x23, 0xb0, + CMVREF3, GPS_L1_ELNA_EN, SCP_JTAG0_TCK, + MD32_0_JTAG_TCK, CMMCLK5, SPI5_B_CSB, DBG_MON_A23), + PIN(134, CAM_PDN4, 0, 4, 0x23, 0xb0, + CMVREF4, RES2, SCP_JTAG0_TRSTN, + MD32_0_JTAG_TRST, RES5, RES6, DBG_MON_A26), + PIN(135, CAM_PDN5, 0, 5, 0x23, 0xb0, + PWM_0, SRCLKENAI1, MD_URXD0, + MD32_0_RXD, CONN_TCXOENA_REQ, RES6, DBG_MON_A29), + PIN(136, CAM_CLK3, 0, 0, 0x23, 0xb0, + CMMCLK3, CLKM1, MD_UTXD0, MD32_0_TXD, + RES5, SPI5_B_MI, DBG_MON_A24), + PIN(137, CAM_CLK4, 0, 1, 0x23, 0xb0, + CMMCLK4, CLKM2, MD_URXD1, RES4, + RES5, CONN_UART0_RXD, DBG_MON_A27), + PIN(138, CAM_CLK5, 0, 2, 0x23, 0xb0, + CMMCLK5, CLKM3, MD_UTXD1, + RES4, RES5, CONN_UART0_TXD, DBG_MON_A30), + PIN(139, SCL4, 0, 25, 0x23, 0xb0, + SCL4, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A21), + PIN(140, SDA4, 0, 31, 0x23, 0xb0, + SDA4, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A20), + PIN(141, SCL2, 0, 24, 0x23, 0xb0, + SCL2, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A18), + PIN(142, SDA2, 0, 30, 0x23, 0xb0, + SDA2, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A19), + PIN(143, CAM_RST0, 0, 6, 0x20, 0x70, + CMVREF0, SPI3_CLK, ADSP_JTAG1_TDO, + SCP_JTAG1_TDO, RES5, RES6, DBG_MON_A31), + PIN(144, CAM_RST1, 0, 7, 0x20, 0x70, + CMVREF1, SPI3_CSB, ADSP_JTAG1_TDI, + SCP_JTAG1_TDI, RES5, RES6, RES7), + PIN(145, CAM_RST2, 0, 8, 0x20, 0x70, + CMVREF2, SPI3_MI, ADSP_JTAG1_TMS, + SCP_JTAG1_TMS, RES5, RES6, RES7), + PIN(146, CAM_PDN0, 0, 3, 0x20, 0x70, + CMVREF3, SPI3_MO, ADSP_JTAG1_TCK, + SCP_JTAG1_TCK, RES5, RES6, DBG_MON_A32), + PIN(147, CAM_PDN1, 0, 4, 0x20, 0x70, + CMVREF4, EXT_FRAME_SYNC, ADSP_JTAG1_TRSTN, + SCP_JTAG1_TRSTN, RES5, RES6, RES7), + PIN(148, CAM_PDN2, 0, 5, 0x20, 0x70, + PWM_1, AGPS_SYNC, RES3, RES4, + RES5, RES6, RES7), + PIN(149, CAM_CLK0, 0, 0, 0x20, 0x70, + CMMCLK0, CLKM0, MD32_0_GPIO0, + RES4, RES5, RES6, RES7), + PIN(150, CAM_CLK1, 0, 1, 0x20, 0x70, + CMMCLK1, CLKM1, MD32_0_GPIO1, + RES4, RES5, RES6, CONN_MCU_AICE_TMSC), + PIN(151, CAM_CLK2, 0, 2, 0x20, 0x70, + CMMCLK2, CLKM2, MD32_0_GPIO2, + RES4, RES5, RES6, CONN_MCU_AICE_TCKC), + PIN(152, KPROW1, 1, 3, 0x36, 0x90, + KPROW1, PWM_2, IDDIG, RES4, RES5, + MBISTREADEN_TRIGGER, DBG_MON_B9), + PIN(153, KPROW0, 1, 2, 0x36, 0x90, + KPROW0, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B8), + PIN(154, KPCOL0, 1, 0, 0x36, 0x90, + KPCOL0, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B6), + PIN(155, KPCOL1, 1, 1, 0x36, 0x90, + KPCOL1, PWM_3, USB_DRVVBUS, CONN_TCXOENA_REQ, + RES5, MBISTWRITEEN_TRIGGER, DBG_MON_B7), + PIN(156, SPI1_CLK, 0, 29, 0x36, 0xa0, + SPI1_A_CLK, SCP_SPI1_A_CK, MRG_CLK, + AGPS_SYNC, MD_URXD0, UDI_TMS, DBG_MON_B10), + PIN(157, SPI1_CSB, 0, 30, 0x36, 0xa0, + SPI1_A_CSB, SCP_SPI1_A_CS, MRG_SYNC, + EXT_FRAME_SYNC, MD_UTXD0, UDI_TCK, DBG_MON_B11), + PIN(158, SPI1_MI, 0, 31, 0x36, 0xa0, + SPI1_A_MI, SCP_SPI1_A_MI, MRG_DI, + PTA_RXD, MD_URXD1, UDI_TDO, DBG_MON_B12), + PIN(159, SPI1_MO, 0, 0, 0x36, 0xb0, + SPI1_A_MO, SCP_SPI1_A_MO, MRG_DO, PTA_TXD, + MD_UTXD1, UDI_NTRST, DBG_MON_B13), + PIN(160, SCL3, 0, 27, 0x36, 0xa0, + SCL3, RES2, SCP_SCL1, RES4, + RES5, RES6, DBG_MON_B14), + PIN(161, SDA3, 0, 28, 0x36, 0xa0, + SDA3, RES2, SCP_SDA1, RES4, + RES5, RES6, DBG_MON_B15), + PIN(162, ANT_SEL0, 0, 0, 0x36, 0xa0, + ANT_SEL0, GPS_L1_ELNA_EN, RES3, + RES4, RES5, UDI_TDI, DBG_MON_B16), + PIN(163, ANT_SEL1, 0, 1, 0x36, 0xa0, + ANT_SEL1, CONN_TCXOENA_REQ, RES3, + RES4, RES5, RES6, DBG_MON_B17), + PIN(164, ANT_SEL2, 0, 2, 0x36, 0xa0, + ANT_SEL2, SCP_SPI1_B_CK, TP_URXD1_AO, + RES4, UCTS0, RES6, DBG_MON_B18), + PIN(165, ANT_SEL3, 0, 3, 0x36, 0xa0, + ANT_SEL3, SCP_SPI1_B_CS, TP_UTXD1_AO, + CONN_TCXOENA_REQ, URTS0, RES6, DBG_MON_B19), + PIN(166, ANT_SEL4, 0, 4, 0x36, 0xa0, + ANT_SEL4, SCP_SPI1_B_MI, TP_URXD2_AO, + SRCLKENAI1, UCTS1, RES6, DBG_MON_B207), + PIN(167, ANT_SEL5, 0, 5, 0x36, 0xa0, + ANT_SEL5, SCP_SPI1_B_MO, TP_UTXD2_AO, + SRCLKENAI0, URTS1, RES6, DBG_MON_B21), + PIN(168, ANT_SEL6, 0, 6, 0x36, 0xa0, + ANT_SEL6, SPI0_B_CLK, TP_UCTS1_AO, + KPCOL2, MD_UCTS0, SCL11, DBG_MON_B22), + PIN(169, ANT_SEL7, 0, 7, 0x36, 0xa0, + ANT_SEL7, SPI0_B_CSB, TP_URTS1_AO, KPROW2, + MD_URTS0, SDA11, DBG_MON_B23), + PIN(170, ANT_SEL8, 0, 8, 0x36, 0xa0, + ANT_SEL8, SPI0_B_MI, TP_UCTS2_AO, + SRCLKENAI1, MD_UCTS1, RES6, DBG_MON_B24), + PIN(171, ANT_SEL9, 0, 9, 0x36, 0xa0, + ANT_SEL9, SPI0_B_MO, TP_URTS2_AO, + SRCLKENAI0, MD_URTS1, RES6, DBG_MON_B25), + PIN(172, CONN_TOP_CLK, 0, 13, 0x36, 0xa0, + CONN_TOP_CLK, AUXIF_CLK0, RES3, + RES4, RES5, RES6, DBG_MON_B29), + PIN(173, CONN_TOP_DATA, 0, 14, 0x36, 0xa0, + CONN_TOP_DATA, AUXIF_ST0, RES3, + RES4, RES5, RES6, DBG_MON_B30), + PIN(174, CONN_HRST_B, 0, 12, 0x36, 0xa0, + CONN_HRST_B, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B28), + PIN(175, CONN_WB_PTA, 0, 15, 0x36, 0xa0, + CONN_WB_PTA, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B31), + PIN(176, CONN_BT_CLK, 0, 10, 0x36, 0xa0, + CONN_BT_CLK, AUXIF_CLK1, RES3, RES4, + RES5, RES6, DBG_MON_B26), + PIN(177, CONN_BT_DATA, 0, 11, 0x36, 0xa0, + CONN_BT_DATA, AUXIF_ST1, RES3, + RES4, RES5, RES6, DBG_MON_B27), + PIN(178, CONN_WF_CTRL0, 0, 16, 0x36, 0xa0, + CONN_WF_CTRL0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(179, CONN_WF_CTRL1, 0, 17, 0x36, 0xa0, + CONN_WF_CTRL1, UFS_MPHY_SCL, + RES3, RES4, RES5, RES6, RES7), + PIN(180, CONN_WF_CTRL2, 0, 18, 0x36, 0xa0, + CONN_WF_CTRL2, UFS_MPHY_SDA, + RES3, RES4, RES5, RES6, RES7), + PIN(181, CONN_WF_CTRL3, 0, 19, 0x36, 0xa0, + CONN_WF_CTRL3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(182, CONN_WF_CTRL4, 0, 20, 0x36, 0xa0, + CONN_WF_CTRL4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(183, MSDC0_CMD, 1, 1, 0x18, 0x30, + MSDC0_CMD, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(184, MSDC0_DAT0, 1, 2, 0x18, 0x30, + MSDC0_DAT0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(185, MSDC0_DAT2, 1, 4, 0x18, 0x30, + MSDC0_DAT2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(186, MSDC0_DAT4, 1, 6, 0x18, 0x30, + MSDC0_DAT4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(187, MSDC0_DAT6, 1, 8, 0x18, 0x30, + MSDC0_DAT6, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(188, MSDC0_DAT1, 1, 3, 0x18, 0x30, + MSDC0_DAT1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(189, MSDC0_DAT5, 1, 7, 0x18, 0x30, + MSDC0_DAT5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(190, MSDC0_DAT7, 1, 9, 0x18, 0x30, + MSDC0_DAT7, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(191, MSDC0_DSL, 1, 10, 0x18, 0x30, + MSDC0_DSL, GPS_L1_ELNA_EN, + IDDIG, DMIC_CLK, RES5, RES6, RES7), + PIN(192, MSDC0_CLK, 1, 0, 0x18, 0x30, + MSDC0_CLK, RES2, USB_DRVVBUS, + DMIC_DAT, RES5, RES6, RES7), + PIN(193, MSDC0_DAT3, 1, 5, 0x18, 0x30, + MSDC0_DAT3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(194, MSDC0_RSTB, 1, 11, 0x18, 0x30, + MSDC0_RSTB, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(195, SCP_VREQ_VAO, 0, 16, 0x14, 0x50, + SCP_VREQ_VAO, DVFSRC_EXT_REQ, + RES3, RES4, RES5, RES6, RES7), + PIN(196, AUD_DAT_MOSI2, 0, 6, 0x14, 0x50, + AUD_DAT_MOSI2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(197, AUD_NLE_MOSI1, 0, 8, 0x14, 0x50, + AUD_NLE_MOSI1, AUD_CLK_MISO, + I2S2_MCK, I2S6_MCK, I2S8_MCK, RES6, RES7), + PIN(198, AUD_NLE_MOSI0, 0, 7, 0x14, 0x50, + AUD_NLE_MOSI0, AUD_SYNC_MISO, + I2S2_BCK, I2S6_BCK, I2S8_BCK, RES6, RES7), + PIN(199, AUD_DAT_MISO2, 0, 3, 0x14, 0x50, + AUD_DAT_MISO2, RES2, I2S2_DI2, + RES4, RES5, RES6, RES7), + PIN(200, SCL6, 0, 6, 0x17, 0x50, + SCL6, RES2, SCP_SCL1, SCL_6306, + RES5, RES6, DBG_MON_A4), + PIN(201, SDA6, 0, 8, 0x17, 0x50, + SDA6, RES2, SCP_SDA1, SDA_6306, + RES5, RES6, DBG_MON_A5), + PIN(202, SCL5, 0, 15, 0x14, 0x50, + SCL5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(203, SDA5, 0, 17, 0x14, 0x50, + SDA5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(204, SCL0, 0, 5, 0x17, 0x50, + SCL0, RES2, RES3, RES4, + RES5, SPI7_A_CLK, DBG_MON_A2), + PIN(205, SDA0, 0, 7, 0x17, 0x50, + SDA0, RES2, RES3, RES4, + RES5, SPI7_A_CSB, DBG_MON_A3), + PIN(206, SRCLKENA0, 0, 18, 0x14, 0x50, + SRCLKENA0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(207, SRCLKENA1, 0, 19, 0x14, 0x50, + SRCLKENA1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(208, WATCHDOG, 0, 20, 0x14, 0x50, + WATCHDOG, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(209, PWRAP_SPI0_MI, 0, 12, 0x14, 0x50, + PWRAP_SPI0_MI, PWRAP_SPI0_MO, + RES3, RES4, RES5, RES6, RES7), + PIN(210, PWRAP_SPI0_CSN, 0, 11, 0x14, 0x50, + PWRAP_SPI0_CSN, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(211, PWRAP_SPI0_MO, 0, 13, 0x14, 0x50, + PWRAP_SPI0_MO, PWRAP_SPI0_MI, + RES3, RES4, RES5, RES6, RES7), + PIN(212, PWRAP_SPI0_CK, 0, 10, 0x14, 0x50, + PWRAP_SPI0_CK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(213, RTC32K_CK, 0, 14, 0x14, 0x50, + RTC32K_CK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(214, AUD_CLK_MOSI, 0, 0, 0x14, 0x50, + AUD_CLK_MOSI, RES2, I2S1_MCK, + I2S7_MCK, I2S9_MCK, RES6, RES7), + PIN(215, AUD_SYNC_MOSI, 0, 9, 0x14, 0x50, + AUD_SYNC_MOSI, RES2, I2S1_BCK, + I2S7_BCK, I2S9_BCK, RES6, RES7), + PIN(216, AUD_DAT_MOSI0, 0, 4, 0x14, 0x50, + AUD_DAT_MOSI0, RES2, I2S1_LRCK, + I2S7_LRCK, I2S9_LRCK, RES6, RES7), + PIN(217, AUD_DAT_MOSI1, 0, 5, 0x14, 0x50, + AUD_DAT_MOSI1, RES2, I2S1_DO, + I2S7_DO, I2S9_DO, RES6, RES7), + PIN(218, AUD_DAT_MISO0, 0, 1, 0x14, 0x50, + AUD_DAT_MISO0, VOW_DAT_MISO, I2S2_LRCK, + I2S6_LRCK, I2S8_LRCK, RES6, RES7), + PIN(219, AUD_DAT_MISO1, 0, 2, 0x14, 0x50, + AUD_DAT_MISO1, VOW_CLK_MISO, I2S2_DI, + I2S6_DI, I2S8_DI, RES6, RES7), +}; + + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +struct gpio_regs { + struct val_regs dir[7]; + uint8_t rsv00[144]; + struct val_regs dout[7]; + uint8_t rsv01[144]; + struct val_regs din[7]; + uint8_t rsv02[144]; + struct val_regs mode[28]; + uint8_t rsv03[560]; + uint32_t dram_pinmux_trapping; +}; + +check_member(gpio_regs, mode[27].val, 0x4b0); +check_member(gpio_regs, dram_pinmux_trapping, 0x6f0); + +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/gpio_base.h b/src/soc/mediatek/mt8192/include/soc/gpio_base.h new file mode 100755 index 0000000..b62c7fe --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/gpio_base.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SOC_MEDIATEK_MT8192_GPIO_BASE_H +#define SOC_MEDIATEK_MT8192_GPIO_BASE_H + +#include <stdint.h> + +typedef union { + u32 raw; + struct { + u32 id : 8; + u32 flag : 3; + u32 bit : 5; + u32 base : 8; + u32 offset : 8; + }; +} gpio_t; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b Gerrit-Change-Number: 43959 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Po Xu <jg_poxu(a)mediatek.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: soc/mediatek/mt8183: Transfer ddr geometry type to dram blob
by Duan huayang (Code Review) 12 Aug '20

12 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43796 ) Change subject: soc/mediatek/mt8183: Transfer ddr geometry type to dram blob ...................................................................... soc/mediatek/mt8183: Transfer ddr geometry type to dram blob BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/43796/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index ff30f67..395a885 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -99,6 +99,7 @@ static int dram_run_full_calibration(struct dramc_param *dparam, u16 config) { + const struct sdram_params * sdram_cfg = get_sdram_config(); initialize_dramc_param(dparam, config); /* Load and run the provided blob for full-calibration if available */ @@ -111,6 +112,8 @@ return -2; dparam->do_putc = do_putchar; + dparam->freq_params[0].ddr_geometry = sdram_cfg->ddr_geometry; + printk(BIOS_INFO, "ddr_geometry:%d\n", sdram_cfg->ddr_geometry); prog_set_entry(&dram, prog_entry(&dram), dparam); prog_run(&dram); -- To view, visit https://review.coreboot.org/c/coreboot/+/43796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Gerrit-Change-Number: 43796 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 22

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2020